1 /* 2 * Copyright (C) 2008-2009 ST-Ericsson SA 3 * 4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2, as 8 * published by the Free Software Foundation. 9 * 10 */ 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/device.h> 14 #include <linux/amba/bus.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/mfd/abx500/ab8500.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <linux/regulator/machine.h> 23 24 #include <asm/pmu.h> 25 #include <asm/mach/map.h> 26 #include <asm/mach/arch.h> 27 #include <asm/hardware/gic.h> 28 #include <plat/gpio-nomadik.h> 29 #include <mach/hardware.h> 30 #include <mach/setup.h> 31 #include <mach/devices.h> 32 #include <linux/platform_data/usb-musb-ux500.h> 33 #include <mach/db8500-regs.h> 34 35 #include "devices-db8500.h" 36 #include "ste-dma40-db8500.h" 37 #include "board-mop500.h" 38 39 /* minimum static i/o mapping required to boot U8500 platforms */ 40 static struct map_desc u8500_uart_io_desc[] __initdata = { 41 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), 42 __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), 43 }; 44 /* U8500 and U9540 common io_desc */ 45 static struct map_desc u8500_common_io_desc[] __initdata = { 46 /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ 47 __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), 48 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), 49 __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), 50 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 51 __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), 52 53 __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), 54 __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K), 55 __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K), 56 __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K), 57 __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K), 58 59 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), 60 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 61 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 62 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 63 }; 64 65 /* U8500 IO map specific description */ 66 static struct map_desc u8500_io_desc[] __initdata = { 67 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), 68 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), 69 70 }; 71 72 /* U9540 IO map specific description */ 73 static struct map_desc u9540_io_desc[] __initdata = { 74 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K), 75 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K), 76 }; 77 78 void __init u8500_map_io(void) 79 { 80 /* 81 * Map the UARTs early so that the DEBUG_LL stuff continues to work. 82 */ 83 iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc)); 84 85 ux500_map_io(); 86 87 iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc)); 88 89 if (cpu_is_ux540_family()) 90 iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc)); 91 else 92 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 93 94 _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); 95 } 96 97 static struct resource db8500_pmu_resources[] = { 98 [0] = { 99 .start = IRQ_DB8500_PMU, 100 .end = IRQ_DB8500_PMU, 101 .flags = IORESOURCE_IRQ, 102 }, 103 }; 104 105 /* 106 * The PMU IRQ lines of two cores are wired together into a single interrupt. 107 * Bounce the interrupt to the other core if it's not ours. 108 */ 109 static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) 110 { 111 irqreturn_t ret = handler(irq, dev); 112 int other = !smp_processor_id(); 113 114 if (ret == IRQ_NONE && cpu_online(other)) 115 irq_set_affinity(irq, cpumask_of(other)); 116 117 /* 118 * We should be able to get away with the amount of IRQ_NONEs we give, 119 * while still having the spurious IRQ detection code kick in if the 120 * interrupt really starts hitting spuriously. 121 */ 122 return ret; 123 } 124 125 struct arm_pmu_platdata db8500_pmu_platdata = { 126 .handle_irq = db8500_pmu_handler, 127 }; 128 129 static struct platform_device db8500_pmu_device = { 130 .name = "arm-pmu", 131 .id = -1, 132 .num_resources = ARRAY_SIZE(db8500_pmu_resources), 133 .resource = db8500_pmu_resources, 134 .dev.platform_data = &db8500_pmu_platdata, 135 }; 136 137 static struct platform_device db8500_prcmu_device = { 138 .name = "db8500-prcmu", 139 }; 140 141 static struct platform_device *platform_devs[] __initdata = { 142 &u8500_dma40_device, 143 &db8500_pmu_device, 144 &db8500_prcmu_device, 145 }; 146 147 static resource_size_t __initdata db8500_gpio_base[] = { 148 U8500_GPIOBANK0_BASE, 149 U8500_GPIOBANK1_BASE, 150 U8500_GPIOBANK2_BASE, 151 U8500_GPIOBANK3_BASE, 152 U8500_GPIOBANK4_BASE, 153 U8500_GPIOBANK5_BASE, 154 U8500_GPIOBANK6_BASE, 155 U8500_GPIOBANK7_BASE, 156 U8500_GPIOBANK8_BASE, 157 }; 158 159 static void __init db8500_add_gpios(struct device *parent) 160 { 161 struct nmk_gpio_platform_data pdata = { 162 .supports_sleepmode = true, 163 }; 164 165 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), 166 IRQ_DB8500_GPIO0, &pdata); 167 dbx500_add_pinctrl(parent, "pinctrl-db8500"); 168 } 169 170 static int usb_db8500_rx_dma_cfg[] = { 171 DB8500_DMA_DEV38_USB_OTG_IEP_1_9, 172 DB8500_DMA_DEV37_USB_OTG_IEP_2_10, 173 DB8500_DMA_DEV36_USB_OTG_IEP_3_11, 174 DB8500_DMA_DEV19_USB_OTG_IEP_4_12, 175 DB8500_DMA_DEV18_USB_OTG_IEP_5_13, 176 DB8500_DMA_DEV17_USB_OTG_IEP_6_14, 177 DB8500_DMA_DEV16_USB_OTG_IEP_7_15, 178 DB8500_DMA_DEV39_USB_OTG_IEP_8 179 }; 180 181 static int usb_db8500_tx_dma_cfg[] = { 182 DB8500_DMA_DEV38_USB_OTG_OEP_1_9, 183 DB8500_DMA_DEV37_USB_OTG_OEP_2_10, 184 DB8500_DMA_DEV36_USB_OTG_OEP_3_11, 185 DB8500_DMA_DEV19_USB_OTG_OEP_4_12, 186 DB8500_DMA_DEV18_USB_OTG_OEP_5_13, 187 DB8500_DMA_DEV17_USB_OTG_OEP_6_14, 188 DB8500_DMA_DEV16_USB_OTG_OEP_7_15, 189 DB8500_DMA_DEV39_USB_OTG_OEP_8 190 }; 191 192 static const char *db8500_read_soc_id(void) 193 { 194 void __iomem *uid = __io_address(U8500_BB_UID_BASE); 195 196 return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x", 197 readl((u32 *)uid+1), 198 readl((u32 *)uid+1), readl((u32 *)uid+2), 199 readl((u32 *)uid+3), readl((u32 *)uid+4)); 200 } 201 202 static struct device * __init db8500_soc_device_init(void) 203 { 204 const char *soc_id = db8500_read_soc_id(); 205 206 return ux500_soc_device_init(soc_id); 207 } 208 209 /* 210 * This function is called from the board init 211 */ 212 struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) 213 { 214 struct device *parent; 215 int i; 216 217 parent = db8500_soc_device_init(); 218 219 db8500_add_rtc(parent); 220 db8500_add_gpios(parent); 221 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 222 223 platform_device_register_data(parent, 224 "cpufreq-u8500", -1, NULL, 0); 225 226 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) 227 platform_devs[i]->dev.parent = parent; 228 229 db8500_prcmu_device.dev.platform_data = ab8500; 230 231 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 232 233 return parent; 234 } 235 236 #ifdef CONFIG_MACH_UX500_DT 237 238 /* TODO: Once all pieces are DT:ed, remove completely. */ 239 static struct device * __init u8500_of_init_devices(void) 240 { 241 struct device *parent = db8500_soc_device_init(); 242 243 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 244 245 platform_device_register_data(parent, 246 "cpufreq-u8500", -1, NULL, 0); 247 248 u8500_dma40_device.dev.parent = parent; 249 250 /* 251 * Devices to be DT:ed: 252 * u8500_dma40_device = todo 253 * db8500_pmu_device = done 254 * db8500_prcmu_device = done 255 */ 256 platform_device_register(&u8500_dma40_device); 257 258 return parent; 259 } 260 261 static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { 262 /* Requires call-back bindings. */ 263 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), 264 /* Requires DMA and call-back bindings. */ 265 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), 266 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), 267 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), 268 /* Requires DMA bindings. */ 269 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), 270 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), 271 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), 272 OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data), 273 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), 274 /* Requires clock name bindings. */ 275 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), 276 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), 277 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL), 278 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL), 279 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL), 280 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL), 281 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), 282 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), 283 OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), 284 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL), 285 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL), 286 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), 287 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), 288 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), 289 /* Requires device name bindings. */ 290 OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), 291 /* Requires clock name and DMA bindings. */ 292 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, 293 "ux500-msp-i2s.0", &msp0_platform_data), 294 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000, 295 "ux500-msp-i2s.1", &msp1_platform_data), 296 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000, 297 "ux500-msp-i2s.2", &msp2_platform_data), 298 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000, 299 "ux500-msp-i2s.3", &msp3_platform_data), 300 {}, 301 }; 302 303 static const struct of_device_id u8500_local_bus_nodes[] = { 304 /* only create devices below soc node */ 305 { .compatible = "stericsson,db8500", }, 306 { .compatible = "stericsson,db8500-prcmu", }, 307 { .compatible = "simple-bus"}, 308 { }, 309 }; 310 311 static void __init u8500_init_machine(void) 312 { 313 struct device *parent = NULL; 314 315 /* Pinmaps must be in place before devices register */ 316 if (of_machine_is_compatible("st-ericsson,mop500")) 317 mop500_pinmaps_init(); 318 else if (of_machine_is_compatible("calaosystems,snowball-a9500")) 319 snowball_pinmaps_init(); 320 else if (of_machine_is_compatible("st-ericsson,hrefv60+")) 321 hrefv60_pinmaps_init(); 322 323 /* TODO: Export SoC, USB, cpu-freq and DMA40 */ 324 parent = u8500_of_init_devices(); 325 326 /* automatically probe child nodes of db8500 device */ 327 of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); 328 } 329 330 static const char * u8500_dt_board_compat[] = { 331 "calaosystems,snowball-a9500", 332 "st-ericsson,hrefv60+", 333 "st-ericsson,u8500", 334 "st-ericsson,mop500", 335 NULL, 336 }; 337 338 DT_MACHINE_START(U8500_DT, "ST-Ericsson U8500 platform (Device Tree Support)") 339 .map_io = u8500_map_io, 340 .init_irq = ux500_init_irq, 341 /* we re-use nomadik timer here */ 342 .timer = &ux500_timer, 343 .handle_irq = gic_handle_irq, 344 .init_machine = u8500_init_machine, 345 .init_late = NULL, 346 .dt_compat = u8500_dt_board_compat, 347 MACHINE_END 348 349 #endif 350