1 /* 2 * Copyright (C) 2008-2009 ST-Ericsson SA 3 * 4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2, as 8 * published by the Free Software Foundation. 9 * 10 */ 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/device.h> 14 #include <linux/amba/bus.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/mfd/abx500/ab8500.h> 20 21 #include <asm/pmu.h> 22 #include <asm/mach/map.h> 23 #include <plat/gpio-nomadik.h> 24 #include <mach/hardware.h> 25 #include <mach/setup.h> 26 #include <mach/devices.h> 27 #include <mach/usb.h> 28 #include <mach/db8500-regs.h> 29 30 #include "devices-db8500.h" 31 #include "ste-dma40-db8500.h" 32 33 /* minimum static i/o mapping required to boot U8500 platforms */ 34 static struct map_desc u8500_uart_io_desc[] __initdata = { 35 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), 36 __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), 37 }; 38 /* U8500 and U9540 common io_desc */ 39 static struct map_desc u8500_common_io_desc[] __initdata = { 40 /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ 41 __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), 42 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), 43 __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), 44 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 45 __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), 46 47 __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), 48 __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K), 49 __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K), 50 __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K), 51 __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K), 52 53 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), 54 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 55 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 56 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 57 }; 58 59 /* U8500 IO map specific description */ 60 static struct map_desc u8500_io_desc[] __initdata = { 61 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), 62 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), 63 64 }; 65 66 /* U9540 IO map specific description */ 67 static struct map_desc u9540_io_desc[] __initdata = { 68 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K), 69 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K), 70 }; 71 72 void __init u8500_map_io(void) 73 { 74 /* 75 * Map the UARTs early so that the DEBUG_LL stuff continues to work. 76 */ 77 iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc)); 78 79 ux500_map_io(); 80 81 iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc)); 82 83 if (cpu_is_u9540()) 84 iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc)); 85 else 86 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 87 88 _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); 89 } 90 91 static struct resource db8500_pmu_resources[] = { 92 [0] = { 93 .start = IRQ_DB8500_PMU, 94 .end = IRQ_DB8500_PMU, 95 .flags = IORESOURCE_IRQ, 96 }, 97 }; 98 99 /* 100 * The PMU IRQ lines of two cores are wired together into a single interrupt. 101 * Bounce the interrupt to the other core if it's not ours. 102 */ 103 static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) 104 { 105 irqreturn_t ret = handler(irq, dev); 106 int other = !smp_processor_id(); 107 108 if (ret == IRQ_NONE && cpu_online(other)) 109 irq_set_affinity(irq, cpumask_of(other)); 110 111 /* 112 * We should be able to get away with the amount of IRQ_NONEs we give, 113 * while still having the spurious IRQ detection code kick in if the 114 * interrupt really starts hitting spuriously. 115 */ 116 return ret; 117 } 118 119 struct arm_pmu_platdata db8500_pmu_platdata = { 120 .handle_irq = db8500_pmu_handler, 121 }; 122 123 static struct platform_device db8500_pmu_device = { 124 .name = "arm-pmu", 125 .id = -1, 126 .num_resources = ARRAY_SIZE(db8500_pmu_resources), 127 .resource = db8500_pmu_resources, 128 .dev.platform_data = &db8500_pmu_platdata, 129 }; 130 131 static struct platform_device db8500_prcmu_device = { 132 .name = "db8500-prcmu", 133 }; 134 135 static struct platform_device *platform_devs[] __initdata = { 136 &u8500_dma40_device, 137 &db8500_pmu_device, 138 &db8500_prcmu_device, 139 }; 140 141 static struct platform_device *of_platform_devs[] __initdata = { 142 &u8500_dma40_device, 143 }; 144 145 static resource_size_t __initdata db8500_gpio_base[] = { 146 U8500_GPIOBANK0_BASE, 147 U8500_GPIOBANK1_BASE, 148 U8500_GPIOBANK2_BASE, 149 U8500_GPIOBANK3_BASE, 150 U8500_GPIOBANK4_BASE, 151 U8500_GPIOBANK5_BASE, 152 U8500_GPIOBANK6_BASE, 153 U8500_GPIOBANK7_BASE, 154 U8500_GPIOBANK8_BASE, 155 }; 156 157 static void __init db8500_add_gpios(struct device *parent) 158 { 159 struct nmk_gpio_platform_data pdata = { 160 .supports_sleepmode = true, 161 }; 162 163 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), 164 IRQ_DB8500_GPIO0, &pdata); 165 dbx500_add_pinctrl(parent, "pinctrl-db8500"); 166 } 167 168 static int usb_db8500_rx_dma_cfg[] = { 169 DB8500_DMA_DEV38_USB_OTG_IEP_1_9, 170 DB8500_DMA_DEV37_USB_OTG_IEP_2_10, 171 DB8500_DMA_DEV36_USB_OTG_IEP_3_11, 172 DB8500_DMA_DEV19_USB_OTG_IEP_4_12, 173 DB8500_DMA_DEV18_USB_OTG_IEP_5_13, 174 DB8500_DMA_DEV17_USB_OTG_IEP_6_14, 175 DB8500_DMA_DEV16_USB_OTG_IEP_7_15, 176 DB8500_DMA_DEV39_USB_OTG_IEP_8 177 }; 178 179 static int usb_db8500_tx_dma_cfg[] = { 180 DB8500_DMA_DEV38_USB_OTG_OEP_1_9, 181 DB8500_DMA_DEV37_USB_OTG_OEP_2_10, 182 DB8500_DMA_DEV36_USB_OTG_OEP_3_11, 183 DB8500_DMA_DEV19_USB_OTG_OEP_4_12, 184 DB8500_DMA_DEV18_USB_OTG_OEP_5_13, 185 DB8500_DMA_DEV17_USB_OTG_OEP_6_14, 186 DB8500_DMA_DEV16_USB_OTG_OEP_7_15, 187 DB8500_DMA_DEV39_USB_OTG_OEP_8 188 }; 189 190 static const char *db8500_read_soc_id(void) 191 { 192 void __iomem *uid = __io_address(U8500_BB_UID_BASE); 193 194 return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x", 195 readl((u32 *)uid+1), 196 readl((u32 *)uid+1), readl((u32 *)uid+2), 197 readl((u32 *)uid+3), readl((u32 *)uid+4)); 198 } 199 200 static struct device * __init db8500_soc_device_init(void) 201 { 202 const char *soc_id = db8500_read_soc_id(); 203 204 return ux500_soc_device_init(soc_id); 205 } 206 207 /* 208 * This function is called from the board init 209 */ 210 struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500) 211 { 212 struct device *parent; 213 int i; 214 215 parent = db8500_soc_device_init(); 216 217 db8500_add_rtc(parent); 218 db8500_add_gpios(parent); 219 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 220 221 platform_device_register_data(parent, 222 "cpufreq-u8500", -1, NULL, 0); 223 224 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) 225 platform_devs[i]->dev.parent = parent; 226 227 db8500_prcmu_device.dev.platform_data = ab8500; 228 229 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 230 231 return parent; 232 } 233 234 /* TODO: Once all pieces are DT:ed, remove completely. */ 235 struct device * __init u8500_of_init_devices(void) 236 { 237 struct device *parent; 238 int i; 239 240 parent = db8500_soc_device_init(); 241 242 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 243 244 platform_device_register_data(parent, 245 "cpufreq-u8500", -1, NULL, 0); 246 247 for (i = 0; i < ARRAY_SIZE(of_platform_devs); i++) 248 of_platform_devs[i]->dev.parent = parent; 249 250 /* 251 * Devices to be DT:ed: 252 * u8500_dma40_device = todo 253 * db8500_pmu_device = done 254 * db8500_prcmu_device = done 255 */ 256 platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs)); 257 258 return parent; 259 } 260