1 /* 2 * Copyright (C) 2008-2009 ST-Ericsson 3 * 4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2, as 8 * published by the Free Software Foundation. 9 * 10 */ 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/device.h> 14 #include <linux/amba/bus.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/gpio.h> 18 #include <linux/platform_device.h> 19 #include <linux/io.h> 20 21 #include <asm/mach/map.h> 22 #include <asm/pmu.h> 23 #include <mach/hardware.h> 24 #include <mach/setup.h> 25 #include <mach/devices.h> 26 #include <mach/usb.h> 27 28 #include "devices-db8500.h" 29 #include "ste-dma40-db8500.h" 30 31 /* minimum static i/o mapping required to boot U8500 platforms */ 32 static struct map_desc u8500_uart_io_desc[] __initdata = { 33 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), 34 __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), 35 }; 36 37 static struct map_desc u8500_io_desc[] __initdata = { 38 __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K), 39 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), 40 __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), 41 __IO_DEV_DESC(U8500_TWD_BASE, SZ_4K), 42 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 43 __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), 44 __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), 45 46 __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), 47 __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K), 48 __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K), 49 __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K), 50 __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K), 51 52 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), 53 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), 54 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 55 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 56 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 57 }; 58 59 static struct map_desc u8500_ed_io_desc[] __initdata = { 60 __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), 61 __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K), 62 }; 63 64 static struct map_desc u8500_v1_io_desc[] __initdata = { 65 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 66 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K), 67 }; 68 69 static struct map_desc u8500_v2_io_desc[] __initdata = { 70 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), 71 }; 72 73 void __init u8500_map_io(void) 74 { 75 /* 76 * Map the UARTs early so that the DEBUG_LL stuff continues to work. 77 */ 78 iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc)); 79 80 ux500_map_io(); 81 82 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 83 84 if (cpu_is_u8500ed()) 85 iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc)); 86 else if (cpu_is_u8500v1()) 87 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); 88 else if (cpu_is_u8500v2()) 89 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); 90 } 91 92 static struct resource db8500_pmu_resources[] = { 93 [0] = { 94 .start = IRQ_DB8500_PMU, 95 .end = IRQ_DB8500_PMU, 96 .flags = IORESOURCE_IRQ, 97 }, 98 }; 99 100 /* 101 * The PMU IRQ lines of two cores are wired together into a single interrupt. 102 * Bounce the interrupt to the other core if it's not ours. 103 */ 104 static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) 105 { 106 irqreturn_t ret = handler(irq, dev); 107 int other = !smp_processor_id(); 108 109 if (ret == IRQ_NONE && cpu_online(other)) 110 irq_set_affinity(irq, cpumask_of(other)); 111 112 /* 113 * We should be able to get away with the amount of IRQ_NONEs we give, 114 * while still having the spurious IRQ detection code kick in if the 115 * interrupt really starts hitting spuriously. 116 */ 117 return ret; 118 } 119 120 static struct arm_pmu_platdata db8500_pmu_platdata = { 121 .handle_irq = db8500_pmu_handler, 122 }; 123 124 static struct platform_device db8500_pmu_device = { 125 .name = "arm-pmu", 126 .id = ARM_PMU_DEVICE_CPU, 127 .num_resources = ARRAY_SIZE(db8500_pmu_resources), 128 .resource = db8500_pmu_resources, 129 .dev.platform_data = &db8500_pmu_platdata, 130 }; 131 132 static struct platform_device *platform_devs[] __initdata = { 133 &u8500_dma40_device, 134 &db8500_pmu_device, 135 }; 136 137 static resource_size_t __initdata db8500_gpio_base[] = { 138 U8500_GPIOBANK0_BASE, 139 U8500_GPIOBANK1_BASE, 140 U8500_GPIOBANK2_BASE, 141 U8500_GPIOBANK3_BASE, 142 U8500_GPIOBANK4_BASE, 143 U8500_GPIOBANK5_BASE, 144 U8500_GPIOBANK6_BASE, 145 U8500_GPIOBANK7_BASE, 146 U8500_GPIOBANK8_BASE, 147 }; 148 149 static void __init db8500_add_gpios(void) 150 { 151 struct nmk_gpio_platform_data pdata = { 152 /* No custom data yet */ 153 }; 154 155 dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), 156 IRQ_DB8500_GPIO0, &pdata); 157 } 158 159 static int usb_db8500_rx_dma_cfg[] = { 160 DB8500_DMA_DEV38_USB_OTG_IEP_1_9, 161 DB8500_DMA_DEV37_USB_OTG_IEP_2_10, 162 DB8500_DMA_DEV36_USB_OTG_IEP_3_11, 163 DB8500_DMA_DEV19_USB_OTG_IEP_4_12, 164 DB8500_DMA_DEV18_USB_OTG_IEP_5_13, 165 DB8500_DMA_DEV17_USB_OTG_IEP_6_14, 166 DB8500_DMA_DEV16_USB_OTG_IEP_7_15, 167 DB8500_DMA_DEV39_USB_OTG_IEP_8 168 }; 169 170 static int usb_db8500_tx_dma_cfg[] = { 171 DB8500_DMA_DEV38_USB_OTG_OEP_1_9, 172 DB8500_DMA_DEV37_USB_OTG_OEP_2_10, 173 DB8500_DMA_DEV36_USB_OTG_OEP_3_11, 174 DB8500_DMA_DEV19_USB_OTG_OEP_4_12, 175 DB8500_DMA_DEV18_USB_OTG_OEP_5_13, 176 DB8500_DMA_DEV17_USB_OTG_OEP_6_14, 177 DB8500_DMA_DEV16_USB_OTG_OEP_7_15, 178 DB8500_DMA_DEV39_USB_OTG_OEP_8 179 }; 180 181 /* 182 * This function is called from the board init 183 */ 184 void __init u8500_init_devices(void) 185 { 186 if (cpu_is_u8500ed()) 187 dma40_u8500ed_fixup(); 188 189 db8500_add_rtc(); 190 db8500_add_gpios(); 191 db8500_add_usb(usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 192 193 platform_device_register_simple("cpufreq-u8500", -1, NULL, 0); 194 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 195 196 return ; 197 } 198