1cb165c52SRabin Vincent /* 2c15def1cSLinus Walleij * Copyright (C) 2008-2009 ST-Ericsson SA 3cb165c52SRabin Vincent * 4cb165c52SRabin Vincent * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> 5cb165c52SRabin Vincent * 6cb165c52SRabin Vincent * This program is free software; you can redistribute it and/or modify 7cb165c52SRabin Vincent * it under the terms of the GNU General Public License version 2, as 8cb165c52SRabin Vincent * published by the Free Software Foundation. 9cb165c52SRabin Vincent * 10cb165c52SRabin Vincent */ 11cb165c52SRabin Vincent #include <linux/types.h> 12cb165c52SRabin Vincent #include <linux/init.h> 13cb165c52SRabin Vincent #include <linux/device.h> 14cb165c52SRabin Vincent #include <linux/amba/bus.h> 15aa90eb9dSRabin Vincent #include <linux/interrupt.h> 16cb165c52SRabin Vincent #include <linux/irq.h> 17cb165c52SRabin Vincent #include <linux/platform_device.h> 18cb165c52SRabin Vincent #include <linux/io.h> 19cb165c52SRabin Vincent 20cb165c52SRabin Vincent #include <asm/mach/map.h> 21aa90eb9dSRabin Vincent #include <asm/pmu.h> 220f332861SLinus Walleij #include <plat/gpio-nomadik.h> 23cb165c52SRabin Vincent #include <mach/hardware.h> 24cb165c52SRabin Vincent #include <mach/setup.h> 25cb165c52SRabin Vincent #include <mach/devices.h> 266f3f3c3fSMian Yousaf Kaukab #include <mach/usb.h> 27cb165c52SRabin Vincent 28fbf1eadfSRabin Vincent #include "devices-db8500.h" 296f3f3c3fSMian Yousaf Kaukab #include "ste-dma40-db8500.h" 30fbf1eadfSRabin Vincent 31cb165c52SRabin Vincent /* minimum static i/o mapping required to boot U8500 platforms */ 32abf12d71SRabin Vincent static struct map_desc u8500_uart_io_desc[] __initdata = { 3392389ca8SRabin Vincent __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), 3492389ca8SRabin Vincent __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), 35abf12d71SRabin Vincent }; 36abf12d71SRabin Vincent 37abf12d71SRabin Vincent static struct map_desc u8500_io_desc[] __initdata = { 38215e83d9SLinus Walleij /* SCU base also covers GIC CPU BASE and TWD with its 4K page */ 39215e83d9SLinus Walleij __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), 4092389ca8SRabin Vincent __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), 4192389ca8SRabin Vincent __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), 4292389ca8SRabin Vincent __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 4392389ca8SRabin Vincent __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), 4492389ca8SRabin Vincent 4592389ca8SRabin Vincent __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), 4692389ca8SRabin Vincent __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K), 4792389ca8SRabin Vincent __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K), 4892389ca8SRabin Vincent __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K), 4992389ca8SRabin Vincent __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K), 5092389ca8SRabin Vincent 51cb165c52SRabin Vincent __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), 52cb165c52SRabin Vincent __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), 53cb165c52SRabin Vincent __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 54cb165c52SRabin Vincent __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 55cb165c52SRabin Vincent __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 56fcbd458eSMattias Wallin __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), 57cb165c52SRabin Vincent }; 58cb165c52SRabin Vincent 59cb165c52SRabin Vincent void __init u8500_map_io(void) 60cb165c52SRabin Vincent { 61abf12d71SRabin Vincent /* 62abf12d71SRabin Vincent * Map the UARTs early so that the DEBUG_LL stuff continues to work. 63abf12d71SRabin Vincent */ 64abf12d71SRabin Vincent iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc)); 65abf12d71SRabin Vincent 66abf12d71SRabin Vincent ux500_map_io(); 67abf12d71SRabin Vincent 68cb165c52SRabin Vincent iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 69cb165c52SRabin Vincent 7011871890SLinus Walleij _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); 71cb165c52SRabin Vincent } 72cb165c52SRabin Vincent 73aa90eb9dSRabin Vincent static struct resource db8500_pmu_resources[] = { 74aa90eb9dSRabin Vincent [0] = { 75aa90eb9dSRabin Vincent .start = IRQ_DB8500_PMU, 76aa90eb9dSRabin Vincent .end = IRQ_DB8500_PMU, 77aa90eb9dSRabin Vincent .flags = IORESOURCE_IRQ, 78aa90eb9dSRabin Vincent }, 79aa90eb9dSRabin Vincent }; 80aa90eb9dSRabin Vincent 81aa90eb9dSRabin Vincent /* 82aa90eb9dSRabin Vincent * The PMU IRQ lines of two cores are wired together into a single interrupt. 83aa90eb9dSRabin Vincent * Bounce the interrupt to the other core if it's not ours. 84aa90eb9dSRabin Vincent */ 85aa90eb9dSRabin Vincent static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) 86aa90eb9dSRabin Vincent { 87aa90eb9dSRabin Vincent irqreturn_t ret = handler(irq, dev); 88aa90eb9dSRabin Vincent int other = !smp_processor_id(); 89aa90eb9dSRabin Vincent 90aa90eb9dSRabin Vincent if (ret == IRQ_NONE && cpu_online(other)) 91aa90eb9dSRabin Vincent irq_set_affinity(irq, cpumask_of(other)); 92aa90eb9dSRabin Vincent 93aa90eb9dSRabin Vincent /* 94aa90eb9dSRabin Vincent * We should be able to get away with the amount of IRQ_NONEs we give, 95aa90eb9dSRabin Vincent * while still having the spurious IRQ detection code kick in if the 96aa90eb9dSRabin Vincent * interrupt really starts hitting spuriously. 97aa90eb9dSRabin Vincent */ 98aa90eb9dSRabin Vincent return ret; 99aa90eb9dSRabin Vincent } 100aa90eb9dSRabin Vincent 101aa90eb9dSRabin Vincent static struct arm_pmu_platdata db8500_pmu_platdata = { 102aa90eb9dSRabin Vincent .handle_irq = db8500_pmu_handler, 103aa90eb9dSRabin Vincent }; 104aa90eb9dSRabin Vincent 105aa90eb9dSRabin Vincent static struct platform_device db8500_pmu_device = { 106aa90eb9dSRabin Vincent .name = "arm-pmu", 107aa90eb9dSRabin Vincent .id = ARM_PMU_DEVICE_CPU, 108aa90eb9dSRabin Vincent .num_resources = ARRAY_SIZE(db8500_pmu_resources), 109aa90eb9dSRabin Vincent .resource = db8500_pmu_resources, 110aa90eb9dSRabin Vincent .dev.platform_data = &db8500_pmu_platdata, 111aa90eb9dSRabin Vincent }; 112aa90eb9dSRabin Vincent 1133df57bcfSMattias Nilsson static struct platform_device db8500_prcmu_device = { 1143df57bcfSMattias Nilsson .name = "db8500-prcmu", 1153df57bcfSMattias Nilsson }; 1163df57bcfSMattias Nilsson 117aa90eb9dSRabin Vincent static struct platform_device *platform_devs[] __initdata = { 118aa90eb9dSRabin Vincent &u8500_dma40_device, 119aa90eb9dSRabin Vincent &db8500_pmu_device, 1203df57bcfSMattias Nilsson &db8500_prcmu_device, 121aa90eb9dSRabin Vincent }; 122aa90eb9dSRabin Vincent 12301afdd13SRabin Vincent static resource_size_t __initdata db8500_gpio_base[] = { 12401afdd13SRabin Vincent U8500_GPIOBANK0_BASE, 12501afdd13SRabin Vincent U8500_GPIOBANK1_BASE, 12601afdd13SRabin Vincent U8500_GPIOBANK2_BASE, 12701afdd13SRabin Vincent U8500_GPIOBANK3_BASE, 12801afdd13SRabin Vincent U8500_GPIOBANK4_BASE, 12901afdd13SRabin Vincent U8500_GPIOBANK5_BASE, 13001afdd13SRabin Vincent U8500_GPIOBANK6_BASE, 13101afdd13SRabin Vincent U8500_GPIOBANK7_BASE, 13201afdd13SRabin Vincent U8500_GPIOBANK8_BASE, 13301afdd13SRabin Vincent }; 13401afdd13SRabin Vincent 13518403424SLee Jones static void __init db8500_add_gpios(struct device *parent) 13601afdd13SRabin Vincent { 13701afdd13SRabin Vincent struct nmk_gpio_platform_data pdata = { 138c15def1cSLinus Walleij .supports_sleepmode = true, 13901afdd13SRabin Vincent }; 14001afdd13SRabin Vincent 14118403424SLee Jones dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), 14201afdd13SRabin Vincent IRQ_DB8500_GPIO0, &pdata); 14301afdd13SRabin Vincent } 14401afdd13SRabin Vincent 1456f3f3c3fSMian Yousaf Kaukab static int usb_db8500_rx_dma_cfg[] = { 1466f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV38_USB_OTG_IEP_1_9, 1476f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV37_USB_OTG_IEP_2_10, 1486f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV36_USB_OTG_IEP_3_11, 1496f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV19_USB_OTG_IEP_4_12, 1506f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV18_USB_OTG_IEP_5_13, 1516f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV17_USB_OTG_IEP_6_14, 1526f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV16_USB_OTG_IEP_7_15, 1536f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV39_USB_OTG_IEP_8 1546f3f3c3fSMian Yousaf Kaukab }; 1556f3f3c3fSMian Yousaf Kaukab 1566f3f3c3fSMian Yousaf Kaukab static int usb_db8500_tx_dma_cfg[] = { 1576f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV38_USB_OTG_OEP_1_9, 1586f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV37_USB_OTG_OEP_2_10, 1596f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV36_USB_OTG_OEP_3_11, 1606f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV19_USB_OTG_OEP_4_12, 1616f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV18_USB_OTG_OEP_5_13, 1626f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV17_USB_OTG_OEP_6_14, 1636f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV16_USB_OTG_OEP_7_15, 1646f3f3c3fSMian Yousaf Kaukab DB8500_DMA_DEV39_USB_OTG_OEP_8 1656f3f3c3fSMian Yousaf Kaukab }; 1666f3f3c3fSMian Yousaf Kaukab 167cb165c52SRabin Vincent /* 168cb165c52SRabin Vincent * This function is called from the board init 169cb165c52SRabin Vincent */ 17018403424SLee Jones struct device* __init u8500_init_devices(void) 171cb165c52SRabin Vincent { 17218403424SLee Jones db8500_add_rtc(NULL); 17318403424SLee Jones db8500_add_gpios(NULL); 17418403424SLee Jones db8500_add_usb(NULL, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 175fbf1eadfSRabin Vincent 1767c1a70e9SMartin Persson platform_device_register_simple("cpufreq-u8500", -1, NULL, 0); 177cb165c52SRabin Vincent platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 178cb165c52SRabin Vincent 17918403424SLee Jones /* FIXME: Return value to be a real parent. */ 18018403424SLee Jones return NULL; 181cb165c52SRabin Vincent } 182