1cb165c52SRabin Vincent /* 2cb165c52SRabin Vincent * Copyright (C) 2008-2009 ST-Ericsson 3cb165c52SRabin Vincent * 4cb165c52SRabin Vincent * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com> 5cb165c52SRabin Vincent * 6cb165c52SRabin Vincent * This program is free software; you can redistribute it and/or modify 7cb165c52SRabin Vincent * it under the terms of the GNU General Public License version 2, as 8cb165c52SRabin Vincent * published by the Free Software Foundation. 9cb165c52SRabin Vincent * 10cb165c52SRabin Vincent */ 11cb165c52SRabin Vincent #include <linux/types.h> 12cb165c52SRabin Vincent #include <linux/init.h> 13cb165c52SRabin Vincent #include <linux/device.h> 14cb165c52SRabin Vincent #include <linux/amba/bus.h> 15cb165c52SRabin Vincent #include <linux/irq.h> 16cb165c52SRabin Vincent #include <linux/gpio.h> 17cb165c52SRabin Vincent #include <linux/platform_device.h> 18cb165c52SRabin Vincent #include <linux/io.h> 19cb165c52SRabin Vincent 20cb165c52SRabin Vincent #include <asm/mach/map.h> 21cb165c52SRabin Vincent #include <mach/hardware.h> 22cb165c52SRabin Vincent #include <mach/setup.h> 23cb165c52SRabin Vincent #include <mach/devices.h> 24cb165c52SRabin Vincent 25fbf1eadfSRabin Vincent #include "devices-db8500.h" 26fbf1eadfSRabin Vincent 27cb165c52SRabin Vincent static struct platform_device *platform_devs[] __initdata = { 287b8ddb06SLinus Walleij &u8500_dma40_device, 29cb165c52SRabin Vincent }; 30cb165c52SRabin Vincent 31cb165c52SRabin Vincent /* minimum static i/o mapping required to boot U8500 platforms */ 32cb165c52SRabin Vincent static struct map_desc u8500_io_desc[] __initdata = { 33cb165c52SRabin Vincent __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), 34cb165c52SRabin Vincent __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), 35cb165c52SRabin Vincent __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 36cb165c52SRabin Vincent __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 37cb165c52SRabin Vincent __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 38f946738cSLinus Walleij __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M), 39cb165c52SRabin Vincent }; 40cb165c52SRabin Vincent 41fcbd458eSMattias Wallin static struct map_desc u8500_ed_io_desc[] __initdata = { 42cb165c52SRabin Vincent __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), 43cb165c52SRabin Vincent __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K), 44cb165c52SRabin Vincent }; 45cb165c52SRabin Vincent 46fcbd458eSMattias Wallin static struct map_desc u8500_v1_io_desc[] __initdata = { 47cb165c52SRabin Vincent __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 48fcbd458eSMattias Wallin __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K), 49fcbd458eSMattias Wallin }; 50fcbd458eSMattias Wallin 51fcbd458eSMattias Wallin static struct map_desc u8500_v2_io_desc[] __initdata = { 52fcbd458eSMattias Wallin __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), 53cb165c52SRabin Vincent }; 54cb165c52SRabin Vincent 55f946738cSLinus Walleij /* 56f946738cSLinus Walleij * Functions to differentiate between later ASICs 57f946738cSLinus Walleij * We look into the end of the ROM to locate the hardcoded ASIC ID. 58f946738cSLinus Walleij * This is only needed to differentiate between minor revisions and 59f946738cSLinus Walleij * process variants of an ASIC, the major revisions are encoded in 60f946738cSLinus Walleij * the cpuid. 61f946738cSLinus Walleij */ 62f946738cSLinus Walleij #define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOT_ROM_BASE + 0x1FFF4) 63f946738cSLinus Walleij #define U8500_ASIC_ID_LOC_V2 (U8500_BOOT_ROM_BASE + 0x1DBF4) 64f946738cSLinus Walleij #define U8500_ASIC_REV_ED 0x01 65f946738cSLinus Walleij #define U8500_ASIC_REV_V10 0xA0 66f946738cSLinus Walleij #define U8500_ASIC_REV_V11 0xA1 67f946738cSLinus Walleij #define U8500_ASIC_REV_V20 0xB0 68f946738cSLinus Walleij 69f946738cSLinus Walleij /** 70f946738cSLinus Walleij * struct db8500_asic_id - fields of the ASIC ID 71f946738cSLinus Walleij * @process: the manufacturing process, 0x40 is 40 nm 72f946738cSLinus Walleij * 0x00 is "standard" 73f946738cSLinus Walleij * @partnumber: hithereto 0x8500 for DB8500 74f946738cSLinus Walleij * @revision: version code in the series 75f946738cSLinus Walleij * This field definion is not formally defined but makes 76f946738cSLinus Walleij * sense. 77f946738cSLinus Walleij */ 78f946738cSLinus Walleij struct db8500_asic_id { 79f946738cSLinus Walleij u8 process; 80f946738cSLinus Walleij u16 partnumber; 81f946738cSLinus Walleij u8 revision; 82f946738cSLinus Walleij }; 83f946738cSLinus Walleij 84f946738cSLinus Walleij /* This isn't going to change at runtime */ 85f946738cSLinus Walleij static struct db8500_asic_id db8500_id; 86f946738cSLinus Walleij 87f946738cSLinus Walleij static void __init get_db8500_asic_id(void) 88f946738cSLinus Walleij { 89f946738cSLinus Walleij u32 asicid; 90f946738cSLinus Walleij 91f946738cSLinus Walleij if (cpu_is_u8500v1() || cpu_is_u8500ed()) 92f946738cSLinus Walleij asicid = readl(__io_address(U8500_ASIC_ID_LOC_ED_V1)); 93f946738cSLinus Walleij else if (cpu_is_u8500v2()) 94f946738cSLinus Walleij asicid = readl(__io_address(U8500_ASIC_ID_LOC_V2)); 95f946738cSLinus Walleij else 96f946738cSLinus Walleij BUG(); 97f946738cSLinus Walleij 98f946738cSLinus Walleij db8500_id.process = (asicid >> 24); 99f946738cSLinus Walleij db8500_id.partnumber = (asicid >> 16) & 0xFFFFU; 100f946738cSLinus Walleij db8500_id.revision = asicid & 0xFFU; 101f946738cSLinus Walleij } 102f946738cSLinus Walleij 103f946738cSLinus Walleij bool cpu_is_u8500v10(void) 104f946738cSLinus Walleij { 105f946738cSLinus Walleij return (db8500_id.revision == U8500_ASIC_REV_V10); 106f946738cSLinus Walleij } 107f946738cSLinus Walleij 108f946738cSLinus Walleij bool cpu_is_u8500v11(void) 109f946738cSLinus Walleij { 110f946738cSLinus Walleij return (db8500_id.revision == U8500_ASIC_REV_V11); 111f946738cSLinus Walleij } 112f946738cSLinus Walleij 113f946738cSLinus Walleij bool cpu_is_u8500v20(void) 114f946738cSLinus Walleij { 115f946738cSLinus Walleij return (db8500_id.revision == U8500_ASIC_REV_V20); 116f946738cSLinus Walleij } 117f946738cSLinus Walleij 118cb165c52SRabin Vincent void __init u8500_map_io(void) 119cb165c52SRabin Vincent { 120cb165c52SRabin Vincent ux500_map_io(); 121cb165c52SRabin Vincent 122cb165c52SRabin Vincent iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 123cb165c52SRabin Vincent 124cb165c52SRabin Vincent if (cpu_is_u8500ed()) 125fcbd458eSMattias Wallin iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc)); 126fcbd458eSMattias Wallin else if (cpu_is_u8500v1()) 127fcbd458eSMattias Wallin iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); 128fcbd458eSMattias Wallin else if (cpu_is_u8500v2()) 129fcbd458eSMattias Wallin iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); 130f946738cSLinus Walleij 131f946738cSLinus Walleij /* Read out the ASIC ID as early as we can */ 132f946738cSLinus Walleij get_db8500_asic_id(); 133cb165c52SRabin Vincent } 134cb165c52SRabin Vincent 13501afdd13SRabin Vincent static resource_size_t __initdata db8500_gpio_base[] = { 13601afdd13SRabin Vincent U8500_GPIOBANK0_BASE, 13701afdd13SRabin Vincent U8500_GPIOBANK1_BASE, 13801afdd13SRabin Vincent U8500_GPIOBANK2_BASE, 13901afdd13SRabin Vincent U8500_GPIOBANK3_BASE, 14001afdd13SRabin Vincent U8500_GPIOBANK4_BASE, 14101afdd13SRabin Vincent U8500_GPIOBANK5_BASE, 14201afdd13SRabin Vincent U8500_GPIOBANK6_BASE, 14301afdd13SRabin Vincent U8500_GPIOBANK7_BASE, 14401afdd13SRabin Vincent U8500_GPIOBANK8_BASE, 14501afdd13SRabin Vincent }; 14601afdd13SRabin Vincent 14701afdd13SRabin Vincent static void __init db8500_add_gpios(void) 14801afdd13SRabin Vincent { 14901afdd13SRabin Vincent struct nmk_gpio_platform_data pdata = { 15001afdd13SRabin Vincent /* No custom data yet */ 15101afdd13SRabin Vincent }; 15201afdd13SRabin Vincent 15301afdd13SRabin Vincent dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), 15401afdd13SRabin Vincent IRQ_DB8500_GPIO0, &pdata); 15501afdd13SRabin Vincent } 15601afdd13SRabin Vincent 157cb165c52SRabin Vincent /* 158cb165c52SRabin Vincent * This function is called from the board init 159cb165c52SRabin Vincent */ 160cb165c52SRabin Vincent void __init u8500_init_devices(void) 161cb165c52SRabin Vincent { 162f946738cSLinus Walleij /* Display some ASIC boilerplate */ 163f946738cSLinus Walleij pr_info("DB8500: process: %02x, revision ID: 0x%02x\n", 164f946738cSLinus Walleij db8500_id.process, db8500_id.revision); 165f946738cSLinus Walleij if (cpu_is_u8500ed()) 166f946738cSLinus Walleij pr_info("DB8500: Early Drop (ED)\n"); 167f946738cSLinus Walleij else if (cpu_is_u8500v10()) 168f946738cSLinus Walleij pr_info("DB8500: version 1.0\n"); 169f946738cSLinus Walleij else if (cpu_is_u8500v11()) 170f946738cSLinus Walleij pr_info("DB8500: version 1.1\n"); 171f946738cSLinus Walleij else if (cpu_is_u8500v20()) 172f946738cSLinus Walleij pr_info("DB8500: version 2.0\n"); 173f946738cSLinus Walleij else 174f946738cSLinus Walleij pr_warning("ASIC: UNKNOWN SILICON VERSION!\n"); 175f946738cSLinus Walleij 1767b8ddb06SLinus Walleij if (cpu_is_u8500ed()) 1777b8ddb06SLinus Walleij dma40_u8500ed_fixup(); 1787b8ddb06SLinus Walleij 179fbf1eadfSRabin Vincent db8500_add_rtc(); 18001afdd13SRabin Vincent db8500_add_gpios(); 181fbf1eadfSRabin Vincent 182cb165c52SRabin Vincent platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 183cb165c52SRabin Vincent 184cb165c52SRabin Vincent return ; 185cb165c52SRabin Vincent } 186