1 /* 2 * NVIDIA Tegra SoC device tree board support 3 * 4 * Copyright (C) 2011, 2013, NVIDIA Corporation 5 * Copyright (C) 2010 Secret Lab Technologies, Ltd. 6 * Copyright (C) 2010 Google, Inc. 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clk/tegra.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/irqchip.h> 25 #include <linux/irqdomain.h> 26 #include <linux/kernel.h> 27 #include <linux/of_address.h> 28 #include <linux/of_fdt.h> 29 #include <linux/of.h> 30 #include <linux/of_platform.h> 31 #include <linux/pda_power.h> 32 #include <linux/platform_device.h> 33 #include <linux/serial_8250.h> 34 #include <linux/slab.h> 35 #include <linux/sys_soc.h> 36 #include <linux/usb/tegra_usb_phy.h> 37 38 #include <soc/tegra/fuse.h> 39 #include <soc/tegra/pmc.h> 40 41 #include <asm/hardware/cache-l2x0.h> 42 #include <asm/mach/arch.h> 43 #include <asm/mach/time.h> 44 #include <asm/mach-types.h> 45 #include <asm/setup.h> 46 #include <asm/trusted_foundations.h> 47 48 #include "board.h" 49 #include "common.h" 50 #include "cpuidle.h" 51 #include "iomap.h" 52 #include "irq.h" 53 #include "pm.h" 54 #include "reset.h" 55 #include "sleep.h" 56 57 /* 58 * Storage for debug-macro.S's state. 59 * 60 * This must be in .data not .bss so that it gets initialized each time the 61 * kernel is loaded. The data is declared here rather than debug-macro.S so 62 * that multiple inclusions of debug-macro.S point at the same data. 63 */ 64 u32 tegra_uart_config[3] = { 65 /* Debug UART initialization required */ 66 1, 67 /* Debug UART physical address */ 68 0, 69 /* Debug UART virtual address */ 70 0, 71 }; 72 73 static void __init tegra_init_early(void) 74 { 75 of_register_trusted_foundations(); 76 tegra_cpu_reset_handler_init(); 77 } 78 79 static void __init tegra_dt_init_irq(void) 80 { 81 tegra_init_irq(); 82 irqchip_init(); 83 } 84 85 static void __init tegra_dt_init(void) 86 { 87 struct device *parent = tegra_soc_device_register(); 88 89 of_platform_default_populate(NULL, NULL, parent); 90 } 91 92 static void __init tegra_dt_init_late(void) 93 { 94 tegra_init_suspend(); 95 tegra_cpuidle_init(); 96 97 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && 98 of_machine_is_compatible("compal,paz00")) 99 tegra_paz00_wifikill_init(); 100 101 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && 102 of_machine_is_compatible("nvidia,tegra20")) 103 platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); 104 } 105 106 static const char * const tegra_dt_board_compat[] = { 107 "nvidia,tegra124", 108 "nvidia,tegra114", 109 "nvidia,tegra30", 110 "nvidia,tegra20", 111 NULL 112 }; 113 114 DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") 115 .l2c_aux_val = 0x3c400001, 116 .l2c_aux_mask = 0xc20fc3fe, 117 .smp = smp_ops(tegra_smp_ops), 118 .map_io = tegra_map_common_io, 119 .init_early = tegra_init_early, 120 .init_irq = tegra_dt_init_irq, 121 .init_machine = tegra_dt_init, 122 .init_late = tegra_dt_init_late, 123 .dt_compat = tegra_dt_board_compat, 124 MACHINE_END 125