1 /* 2 * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __MACH_TEGRA_SLEEP_H 18 #define __MACH_TEGRA_SLEEP_H 19 20 #include "iomap.h" 21 22 #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \ 23 + IO_CPU_VIRT) 24 #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \ 25 + IO_PPSB_VIRT) 26 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \ 27 + IO_PPSB_VIRT) 28 #define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \ 29 + IO_APB_VIRT) 30 #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT) 31 32 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */ 33 #define PMC_SCRATCH37 0x130 34 #define PMC_SCRATCH38 0x134 35 #define PMC_SCRATCH39 0x138 36 #define PMC_SCRATCH41 0x140 37 38 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 39 #define CPU_RESETTABLE 2 40 #define CPU_RESETTABLE_SOON 1 41 #define CPU_NOT_RESETTABLE 0 42 #endif 43 44 /* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */ 45 #define TEGRA_FLUSH_CACHE_LOUIS 0 46 #define TEGRA_FLUSH_CACHE_ALL 1 47 48 #ifdef __ASSEMBLY__ 49 /* waits until the microsecond counter (base) is > rn */ 50 .macro wait_until, rn, base, tmp 51 add \rn, \rn, #1 52 1001: ldr \tmp, [\base] 53 cmp \tmp, \rn 54 bmi 1001b 55 .endm 56 57 /* returns the offset of the flow controller halt register for a cpu */ 58 .macro cpu_to_halt_reg rd, rcpu 59 cmp \rcpu, #0 60 subne \rd, \rcpu, #1 61 movne \rd, \rd, lsl #3 62 addne \rd, \rd, #0x14 63 moveq \rd, #0 64 .endm 65 66 /* returns the offset of the flow controller csr register for a cpu */ 67 .macro cpu_to_csr_reg rd, rcpu 68 cmp \rcpu, #0 69 subne \rd, \rcpu, #1 70 movne \rd, \rd, lsl #3 71 addne \rd, \rd, #0x18 72 moveq \rd, #8 73 .endm 74 75 /* returns the ID of the current processor */ 76 .macro cpu_id, rd 77 mrc p15, 0, \rd, c0, c0, 5 78 and \rd, \rd, #0xF 79 .endm 80 81 /* loads a 32-bit value into a register without a data access */ 82 .macro mov32, reg, val 83 movw \reg, #:lower16:\val 84 movt \reg, #:upper16:\val 85 .endm 86 87 /* Marco to check CPU part num */ 88 .macro check_cpu_part_num part_num, tmp1, tmp2 89 mrc p15, 0, \tmp1, c0, c0, 0 90 ubfx \tmp1, \tmp1, #4, #12 91 mov32 \tmp2, \part_num 92 cmp \tmp1, \tmp2 93 .endm 94 95 /* Macro to exit SMP coherency. */ 96 .macro exit_smp, tmp1, tmp2 97 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR 98 bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW 99 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR 100 isb 101 #ifdef CONFIG_HAVE_ARM_SCU 102 check_cpu_part_num 0xc09, \tmp1, \tmp2 103 mrceq p15, 0, \tmp1, c0, c0, 5 104 andeq \tmp1, \tmp1, #0xF 105 moveq \tmp1, \tmp1, lsl #2 106 moveq \tmp2, #0xf 107 moveq \tmp2, \tmp2, lsl \tmp1 108 ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC) 109 streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU 110 dsb 111 #endif 112 .endm 113 114 /* Macro to check Tegra revision */ 115 #define APB_MISC_GP_HIDREV 0x804 116 .macro tegra_get_soc_id base, tmp1 117 mov32 \tmp1, \base 118 ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV] 119 and \tmp1, \tmp1, #0xff00 120 mov \tmp1, \tmp1, lsr #8 121 .endm 122 123 /* Macro to resume & re-enable L2 cache */ 124 #ifndef L2X0_CTRL_EN 125 #define L2X0_CTRL_EN 1 126 #endif 127 128 #ifdef CONFIG_CACHE_L2X0 129 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs 130 W(adr) \tmp1, \phys_l2x0_saved_regs 131 ldr \tmp1, [\tmp1] 132 ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE] 133 ldr \tmp3, [\tmp2, #L2X0_CTRL] 134 tst \tmp3, #L2X0_CTRL_EN 135 bne exit_l2_resume 136 ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY] 137 str \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL] 138 ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY] 139 str \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL] 140 ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL] 141 str \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL] 142 ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL] 143 str \tmp3, [\tmp2, #L2X0_POWER_CTRL] 144 ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL] 145 str \tmp3, [\tmp2, #L2X0_AUX_CTRL] 146 mov \tmp3, #L2X0_CTRL_EN 147 str \tmp3, [\tmp2, #L2X0_CTRL] 148 exit_l2_resume: 149 .endm 150 #else /* CONFIG_CACHE_L2X0 */ 151 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs 152 .endm 153 #endif /* CONFIG_CACHE_L2X0 */ 154 #else 155 void tegra_pen_lock(void); 156 void tegra_pen_unlock(void); 157 void tegra_resume(void); 158 int tegra_sleep_cpu_finish(unsigned long); 159 void tegra_disable_clean_inv_dcache(u32 flag); 160 161 #ifdef CONFIG_HOTPLUG_CPU 162 void tegra20_hotplug_shutdown(void); 163 void tegra30_hotplug_shutdown(void); 164 void tegra_hotplug_init(void); 165 #else 166 static inline void tegra_hotplug_init(void) {} 167 #endif 168 169 void tegra20_cpu_shutdown(int cpu); 170 int tegra20_cpu_is_resettable_soon(void); 171 void tegra20_cpu_clear_resettable(void); 172 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 173 void tegra20_cpu_set_resettable_soon(void); 174 #else 175 static inline void tegra20_cpu_set_resettable_soon(void) {} 176 #endif 177 178 int tegra20_sleep_cpu_secondary_finish(unsigned long); 179 void tegra20_tear_down_cpu(void); 180 int tegra30_sleep_cpu_secondary_finish(unsigned long); 181 void tegra30_tear_down_cpu(void); 182 183 #endif 184 #endif 185