1/* 2 * arch/arm/mach-tegra/sleep.S 3 * 4 * Copyright (c) 2010-2011, NVIDIA Corporation. 5 * Copyright (c) 2011, Google, Inc. 6 * 7 * Author: Colin Cross <ccross@android.com> 8 * Gary King <gking@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 23 */ 24 25#include <linux/linkage.h> 26 27#include <asm/assembler.h> 28#include <asm/cache.h> 29#include <asm/cp15.h> 30#include <asm/hardware/cache-l2x0.h> 31 32#include "iomap.h" 33 34#include "flowctrl.h" 35#include "sleep.h" 36 37#define CLK_RESET_CCLK_BURST 0x20 38#define CLK_RESET_CCLK_DIVIDER 0x24 39 40#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) 41/* 42 * tegra_disable_clean_inv_dcache 43 * 44 * disable, clean & invalidate the D-cache 45 * 46 * Corrupted registers: r1-r3, r6, r8, r9-r11 47 */ 48ENTRY(tegra_disable_clean_inv_dcache) 49 stmfd sp!, {r0, r4-r5, r7, r9-r11, lr} 50 dmb @ ensure ordering 51 52 /* Disable the D-cache */ 53 mrc p15, 0, r2, c1, c0, 0 54 bic r2, r2, #CR_C 55 mcr p15, 0, r2, c1, c0, 0 56 isb 57 58 /* Flush the D-cache */ 59 bl v7_flush_dcache_louis 60 61 /* Trun off coherency */ 62 exit_smp r4, r5 63 64 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc} 65ENDPROC(tegra_disable_clean_inv_dcache) 66#endif 67 68#ifdef CONFIG_PM_SLEEP 69/* 70 * tegra_sleep_cpu_finish(unsigned long v2p) 71 * 72 * enters suspend in LP2 by turning off the mmu and jumping to 73 * tegra?_tear_down_cpu 74 */ 75ENTRY(tegra_sleep_cpu_finish) 76 /* Flush and disable the L1 data cache */ 77 bl tegra_disable_clean_inv_dcache 78 79 mov32 r6, tegra_tear_down_cpu 80 ldr r1, [r6] 81 add r1, r1, r0 82 83 mov32 r3, tegra_shut_off_mmu 84 add r3, r3, r0 85 mov r0, r1 86 87 mov pc, r3 88ENDPROC(tegra_sleep_cpu_finish) 89 90/* 91 * tegra_shut_off_mmu 92 * 93 * r0 = physical address to jump to with mmu off 94 * 95 * called with VA=PA mapping 96 * turns off MMU, icache, dcache and branch prediction 97 */ 98 .align L1_CACHE_SHIFT 99 .pushsection .idmap.text, "ax" 100ENTRY(tegra_shut_off_mmu) 101 mrc p15, 0, r3, c1, c0, 0 102 movw r2, #CR_I | CR_Z | CR_C | CR_M 103 bic r3, r3, r2 104 dsb 105 mcr p15, 0, r3, c1, c0, 0 106 isb 107#ifdef CONFIG_CACHE_L2X0 108 /* Disable L2 cache */ 109 check_cpu_part_num 0xc09, r9, r10 110 movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) 111 movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) 112 moveq r5, #0 113 streq r5, [r4, #L2X0_CTRL] 114#endif 115 mov pc, r0 116ENDPROC(tegra_shut_off_mmu) 117 .popsection 118 119/* 120 * tegra_switch_cpu_to_pllp 121 * 122 * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp 123 */ 124ENTRY(tegra_switch_cpu_to_pllp) 125 /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */ 126 mov32 r5, TEGRA_CLK_RESET_BASE 127 mov r0, #(2 << 28) @ burst policy = run mode 128 orr r0, r0, #(4 << 4) @ use PLLP in run mode burst 129 str r0, [r5, #CLK_RESET_CCLK_BURST] 130 mov r0, #0 131 str r0, [r5, #CLK_RESET_CCLK_DIVIDER] 132 mov pc, lr 133ENDPROC(tegra_switch_cpu_to_pllp) 134#endif 135