1/* 2 * arch/arm/mach-tegra/sleep.S 3 * 4 * Copyright (c) 2010-2011, NVIDIA Corporation. 5 * Copyright (c) 2011, Google, Inc. 6 * 7 * Author: Colin Cross <ccross@android.com> 8 * Gary King <gking@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 23 */ 24 25#include <linux/linkage.h> 26 27#include <asm/assembler.h> 28#include <asm/cache.h> 29#include <asm/cp15.h> 30#include <asm/hardware/cache-l2x0.h> 31 32#include "iomap.h" 33#include "sleep.h" 34 35#define CLK_RESET_CCLK_BURST 0x20 36#define CLK_RESET_CCLK_DIVIDER 0x24 37 38#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) 39/* 40 * tegra_disable_clean_inv_dcache 41 * 42 * disable, clean & invalidate the D-cache 43 * 44 * Corrupted registers: r1-r3, r6, r8, r9-r11 45 */ 46ENTRY(tegra_disable_clean_inv_dcache) 47 stmfd sp!, {r0, r4-r5, r7, r9-r11, lr} 48 dmb @ ensure ordering 49 50 /* Disable the D-cache */ 51 mrc p15, 0, r2, c1, c0, 0 52 bic r2, r2, #CR_C 53 mcr p15, 0, r2, c1, c0, 0 54 isb 55 56 /* Flush the D-cache */ 57 cmp r0, #TEGRA_FLUSH_CACHE_ALL 58 blne v7_flush_dcache_louis 59 bleq v7_flush_dcache_all 60 61 /* Trun off coherency */ 62 exit_smp r4, r5 63 64 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc} 65ENDPROC(tegra_disable_clean_inv_dcache) 66#endif 67 68#ifdef CONFIG_PM_SLEEP 69/* 70 * tegra_init_l2_for_a15 71 * 72 * set up the correct L2 cache data RAM latency 73 */ 74ENTRY(tegra_init_l2_for_a15) 75 mrc p15, 0, r0, c0, c0, 5 76 ubfx r0, r0, #8, #4 77 tst r0, #1 @ only need for cluster 0 78 bne _exit_init_l2_a15 79 80 mrc p15, 0x1, r0, c9, c0, 2 81 and r0, r0, #7 82 cmp r0, #2 83 bicne r0, r0, #7 84 orrne r0, r0, #2 85 mcrne p15, 0x1, r0, c9, c0, 2 86_exit_init_l2_a15: 87 88 ret lr 89ENDPROC(tegra_init_l2_for_a15) 90 91/* 92 * tegra_sleep_cpu_finish(unsigned long v2p) 93 * 94 * enters suspend in LP2 by turning off the mmu and jumping to 95 * tegra?_tear_down_cpu 96 */ 97ENTRY(tegra_sleep_cpu_finish) 98 mov r4, r0 99 /* Flush and disable the L1 data cache */ 100 mov r0, #TEGRA_FLUSH_CACHE_ALL 101 bl tegra_disable_clean_inv_dcache 102 103 mov r0, r4 104 mov32 r6, tegra_tear_down_cpu 105 ldr r1, [r6] 106 add r1, r1, r0 107 108 mov32 r3, tegra_shut_off_mmu 109 add r3, r3, r0 110 mov r0, r1 111 112 ret r3 113ENDPROC(tegra_sleep_cpu_finish) 114 115/* 116 * tegra_shut_off_mmu 117 * 118 * r0 = physical address to jump to with mmu off 119 * 120 * called with VA=PA mapping 121 * turns off MMU, icache, dcache and branch prediction 122 */ 123 .align L1_CACHE_SHIFT 124 .pushsection .idmap.text, "ax" 125ENTRY(tegra_shut_off_mmu) 126 mrc p15, 0, r3, c1, c0, 0 127 movw r2, #CR_I | CR_Z | CR_C | CR_M 128 bic r3, r3, r2 129 dsb 130 mcr p15, 0, r3, c1, c0, 0 131 isb 132#ifdef CONFIG_CACHE_L2X0 133 /* Disable L2 cache */ 134 check_cpu_part_num 0xc09, r9, r10 135 movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) 136 movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) 137 moveq r3, #0 138 streq r3, [r2, #L2X0_CTRL] 139#endif 140 ret r0 141ENDPROC(tegra_shut_off_mmu) 142 .popsection 143 144/* 145 * tegra_switch_cpu_to_pllp 146 * 147 * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp 148 */ 149ENTRY(tegra_switch_cpu_to_pllp) 150 /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */ 151 mov32 r5, TEGRA_CLK_RESET_BASE 152 mov r0, #(2 << 28) @ burst policy = run mode 153 orr r0, r0, #(4 << 4) @ use PLLP in run mode burst 154 str r0, [r5, #CLK_RESET_CCLK_BURST] 155 mov r0, #0 156 str r0, [r5, #CLK_RESET_CCLK_DIVIDER] 157 ret lr 158ENDPROC(tegra_switch_cpu_to_pllp) 159#endif 160