1/* 2 * arch/arm/mach-tegra/sleep.S 3 * 4 * Copyright (c) 2010-2011, NVIDIA Corporation. 5 * Copyright (c) 2011, Google, Inc. 6 * 7 * Author: Colin Cross <ccross@android.com> 8 * Gary King <gking@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 23 */ 24 25#include <linux/linkage.h> 26 27#include <asm/assembler.h> 28#include <asm/cache.h> 29#include <asm/cp15.h> 30#include <asm/hardware/cache-l2x0.h> 31 32#include "iomap.h" 33 34#include "flowctrl.h" 35#include "sleep.h" 36 37#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) 38/* 39 * tegra_disable_clean_inv_dcache 40 * 41 * disable, clean & invalidate the D-cache 42 * 43 * Corrupted registers: r1-r3, r6, r8, r9-r11 44 */ 45ENTRY(tegra_disable_clean_inv_dcache) 46 stmfd sp!, {r0, r4-r5, r7, r9-r11, lr} 47 dmb @ ensure ordering 48 49 /* Disable the D-cache */ 50 mrc p15, 0, r2, c1, c0, 0 51 bic r2, r2, #CR_C 52 mcr p15, 0, r2, c1, c0, 0 53 isb 54 55 /* Flush the D-cache */ 56 bl v7_flush_dcache_louis 57 58 /* Trun off coherency */ 59 exit_smp r4, r5 60 61 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc} 62ENDPROC(tegra_disable_clean_inv_dcache) 63#endif 64 65#ifdef CONFIG_PM_SLEEP 66/* 67 * tegra_sleep_cpu_finish(unsigned long v2p) 68 * 69 * enters suspend in LP2 by turning off the mmu and jumping to 70 * tegra?_tear_down_cpu 71 */ 72ENTRY(tegra_sleep_cpu_finish) 73 /* Flush and disable the L1 data cache */ 74 bl tegra_disable_clean_inv_dcache 75 76 mov32 r6, tegra_tear_down_cpu 77 ldr r1, [r6] 78 add r1, r1, r0 79 80 mov32 r3, tegra_shut_off_mmu 81 add r3, r3, r0 82 mov r0, r1 83 84 mov pc, r3 85ENDPROC(tegra_sleep_cpu_finish) 86 87/* 88 * tegra_shut_off_mmu 89 * 90 * r0 = physical address to jump to with mmu off 91 * 92 * called with VA=PA mapping 93 * turns off MMU, icache, dcache and branch prediction 94 */ 95 .align L1_CACHE_SHIFT 96 .pushsection .idmap.text, "ax" 97ENTRY(tegra_shut_off_mmu) 98 mrc p15, 0, r3, c1, c0, 0 99 movw r2, #CR_I | CR_Z | CR_C | CR_M 100 bic r3, r3, r2 101 dsb 102 mcr p15, 0, r3, c1, c0, 0 103 isb 104#ifdef CONFIG_CACHE_L2X0 105 /* Disable L2 cache */ 106 mov32 r4, TEGRA_ARM_PERIF_BASE + 0x3000 107 mov r5, #0 108 str r5, [r4, #L2X0_CTRL] 109#endif 110 mov pc, r0 111ENDPROC(tegra_shut_off_mmu) 112 .popsection 113#endif 114