xref: /openbmc/linux/arch/arm/mach-tegra/sleep.S (revision 54cbac81) 
1/*
2 * arch/arm/mach-tegra/sleep.S
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 * Copyright (c) 2011, Google, Inc.
6 *
7 * Author: Colin Cross <ccross@android.com>
8 *         Gary King <gking@nvidia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
23 */
24
25#include <linux/linkage.h>
26
27#include <asm/assembler.h>
28#include <asm/cache.h>
29#include <asm/cp15.h>
30#include <asm/hardware/cache-l2x0.h>
31
32#include "iomap.h"
33
34#include "flowctrl.h"
35#include "sleep.h"
36
37#ifdef CONFIG_PM_SLEEP
38/*
39 * tegra_disable_clean_inv_dcache
40 *
41 * disable, clean & invalidate the D-cache
42 *
43 * Corrupted registers: r1-r3, r6, r8, r9-r11
44 */
45ENTRY(tegra_disable_clean_inv_dcache)
46	stmfd	sp!, {r0, r4-r5, r7, r9-r11, lr}
47	dmb					@ ensure ordering
48
49	/* Disable the D-cache */
50	mrc	p15, 0, r2, c1, c0, 0
51	bic	r2, r2, #CR_C
52	mcr	p15, 0, r2, c1, c0, 0
53	isb
54
55	/* Flush the D-cache */
56	bl	v7_flush_dcache_louis
57
58	/* Trun off coherency */
59	exit_smp r4, r5
60
61	ldmfd	sp!, {r0, r4-r5, r7, r9-r11, pc}
62ENDPROC(tegra_disable_clean_inv_dcache)
63
64/*
65 * tegra_sleep_cpu_finish(unsigned long v2p)
66 *
67 * enters suspend in LP2 by turning off the mmu and jumping to
68 * tegra?_tear_down_cpu
69 */
70ENTRY(tegra_sleep_cpu_finish)
71	/* Flush and disable the L1 data cache */
72	bl	tegra_disable_clean_inv_dcache
73
74	mov32	r6, tegra_tear_down_cpu
75	ldr	r1, [r6]
76	add	r1, r1, r0
77
78	mov32	r3, tegra_shut_off_mmu
79	add	r3, r3, r0
80	mov	r0, r1
81
82	mov	pc, r3
83ENDPROC(tegra_sleep_cpu_finish)
84
85/*
86 * tegra_shut_off_mmu
87 *
88 * r0 = physical address to jump to with mmu off
89 *
90 * called with VA=PA mapping
91 * turns off MMU, icache, dcache and branch prediction
92 */
93	.align	L1_CACHE_SHIFT
94	.pushsection	.idmap.text, "ax"
95ENTRY(tegra_shut_off_mmu)
96	mrc	p15, 0, r3, c1, c0, 0
97	movw	r2, #CR_I | CR_Z | CR_C | CR_M
98	bic	r3, r3, r2
99	dsb
100	mcr	p15, 0, r3, c1, c0, 0
101	isb
102#ifdef CONFIG_CACHE_L2X0
103	/* Disable L2 cache */
104	mov32	r4, TEGRA_ARM_PERIF_BASE + 0x3000
105	mov	r5, #0
106	str	r5, [r4, #L2X0_CTRL]
107#endif
108	mov	pc, r0
109ENDPROC(tegra_shut_off_mmu)
110	.popsection
111#endif
112