1/* 2 * arch/arm/mach-tegra/sleep.S 3 * 4 * Copyright (c) 2010-2011, NVIDIA Corporation. 5 * Copyright (c) 2011, Google, Inc. 6 * 7 * Author: Colin Cross <ccross@android.com> 8 * Gary King <gking@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 23 */ 24 25#include <linux/linkage.h> 26 27#include <asm/assembler.h> 28#include <asm/cache.h> 29#include <asm/cp15.h> 30#include <asm/hardware/cache-l2x0.h> 31 32#include "iomap.h" 33#include "sleep.h" 34 35#define CLK_RESET_CCLK_BURST 0x20 36#define CLK_RESET_CCLK_DIVIDER 0x24 37 38#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) 39/* 40 * tegra_disable_clean_inv_dcache 41 * 42 * disable, clean & invalidate the D-cache 43 * 44 * Corrupted registers: r1-r3, r6, r8, r9-r11 45 */ 46ENTRY(tegra_disable_clean_inv_dcache) 47 stmfd sp!, {r0, r4-r5, r7, r9-r11, lr} 48 dmb @ ensure ordering 49 50 /* Disable the D-cache */ 51 mrc p15, 0, r2, c1, c0, 0 52 tst r2, #CR_C @ see tegra_sleep_cpu() 53 bic r2, r2, #CR_C 54 mcrne p15, 0, r2, c1, c0, 0 55 isb 56 57 /* Flush the D-cache */ 58 cmp r0, #TEGRA_FLUSH_CACHE_ALL 59 blne v7_flush_dcache_louis 60 bleq v7_flush_dcache_all 61 62 /* Trun off coherency */ 63 exit_smp r4, r5 64 65 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc} 66ENDPROC(tegra_disable_clean_inv_dcache) 67#endif 68 69#ifdef CONFIG_PM_SLEEP 70/* 71 * tegra_init_l2_for_a15 72 * 73 * set up the correct L2 cache data RAM latency 74 */ 75ENTRY(tegra_init_l2_for_a15) 76 mrc p15, 0, r0, c0, c0, 5 77 ubfx r0, r0, #8, #4 78 tst r0, #1 @ only need for cluster 0 79 bne _exit_init_l2_a15 80 81 mrc p15, 0x1, r0, c9, c0, 2 82 and r0, r0, #7 83 cmp r0, #2 84 bicne r0, r0, #7 85 orrne r0, r0, #2 86 mcrne p15, 0x1, r0, c9, c0, 2 87_exit_init_l2_a15: 88 89 ret lr 90ENDPROC(tegra_init_l2_for_a15) 91 92/* 93 * tegra_sleep_cpu_finish(unsigned long v2p) 94 * 95 * enters suspend in LP2 by turning off the mmu and jumping to 96 * tegra?_tear_down_cpu 97 */ 98ENTRY(tegra_sleep_cpu_finish) 99 mov r4, r0 100 /* Flush and disable the L1 data cache */ 101 mov r0, #TEGRA_FLUSH_CACHE_ALL 102 bl tegra_disable_clean_inv_dcache 103 104 mov r0, r4 105 mov32 r6, tegra_tear_down_cpu 106 ldr r1, [r6] 107 add r1, r1, r0 108 109 mov32 r3, tegra_shut_off_mmu 110 add r3, r3, r0 111 mov r0, r1 112 113 ret r3 114ENDPROC(tegra_sleep_cpu_finish) 115 116/* 117 * tegra_shut_off_mmu 118 * 119 * r0 = physical address to jump to with mmu off 120 * 121 * called with VA=PA mapping 122 * turns off MMU, icache, dcache and branch prediction 123 */ 124 .align L1_CACHE_SHIFT 125 .pushsection .idmap.text, "ax" 126ENTRY(tegra_shut_off_mmu) 127 mrc p15, 0, r3, c1, c0, 0 128 movw r2, #CR_I | CR_Z | CR_C | CR_M 129 bic r3, r3, r2 130 dsb 131 mcr p15, 0, r3, c1, c0, 0 132 isb 133#ifdef CONFIG_CACHE_L2X0 134 /* Disable L2 cache */ 135 check_cpu_part_num 0xc09, r9, r10 136 retne r0 137 138 mov32 r2, TEGRA_ARM_PERIF_BASE + 0x3000 139 ldr r3, [r2, #L2X0_CTRL] 140 tst r3, #L2X0_CTRL_EN @ see tegra_sleep_cpu() 141 mov r3, #0 142 strne r3, [r2, #L2X0_CTRL] 143#endif 144 ret r0 145ENDPROC(tegra_shut_off_mmu) 146 .popsection 147 148/* 149 * tegra_switch_cpu_to_pllp 150 * 151 * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp 152 */ 153ENTRY(tegra_switch_cpu_to_pllp) 154 /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */ 155 mov32 r5, TEGRA_CLK_RESET_BASE 156 mov r0, #(2 << 28) @ burst policy = run mode 157 orr r0, r0, #(4 << 4) @ use PLLP in run mode burst 158 str r0, [r5, #CLK_RESET_CCLK_BURST] 159 mov r0, #0 160 str r0, [r5, #CLK_RESET_CCLK_DIVIDER] 161 ret lr 162ENDPROC(tegra_switch_cpu_to_pllp) 163#endif 164