1/* 2 * arch/arm/mach-tegra/sleep.S 3 * 4 * Copyright (c) 2010-2011, NVIDIA Corporation. 5 * Copyright (c) 2011, Google, Inc. 6 * 7 * Author: Colin Cross <ccross@android.com> 8 * Gary King <gking@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18 * more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 23 */ 24 25#include <linux/linkage.h> 26 27#include <asm/assembler.h> 28#include <asm/cache.h> 29#include <asm/cp15.h> 30#include <asm/hardware/cache-l2x0.h> 31 32#include "iomap.h" 33 34#include "flowctrl.h" 35#include "sleep.h" 36 37#define CLK_RESET_CCLK_BURST 0x20 38#define CLK_RESET_CCLK_DIVIDER 0x24 39 40#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) 41/* 42 * tegra_disable_clean_inv_dcache 43 * 44 * disable, clean & invalidate the D-cache 45 * 46 * Corrupted registers: r1-r3, r6, r8, r9-r11 47 */ 48ENTRY(tegra_disable_clean_inv_dcache) 49 stmfd sp!, {r0, r4-r5, r7, r9-r11, lr} 50 dmb @ ensure ordering 51 52 /* Disable the D-cache */ 53 mrc p15, 0, r2, c1, c0, 0 54 bic r2, r2, #CR_C 55 mcr p15, 0, r2, c1, c0, 0 56 isb 57 58 /* Flush the D-cache */ 59 cmp r0, #TEGRA_FLUSH_CACHE_ALL 60 blne v7_flush_dcache_louis 61 bleq v7_flush_dcache_all 62 63 /* Trun off coherency */ 64 exit_smp r4, r5 65 66 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc} 67ENDPROC(tegra_disable_clean_inv_dcache) 68#endif 69 70#ifdef CONFIG_PM_SLEEP 71/* 72 * tegra_init_l2_for_a15 73 * 74 * set up the correct L2 cache data RAM latency 75 */ 76ENTRY(tegra_init_l2_for_a15) 77 mrc p15, 0, r0, c0, c0, 5 78 ubfx r0, r0, #8, #4 79 tst r0, #1 @ only need for cluster 0 80 bne _exit_init_l2_a15 81 82 mrc p15, 0x1, r0, c9, c0, 2 83 and r0, r0, #7 84 cmp r0, #2 85 bicne r0, r0, #7 86 orrne r0, r0, #2 87 mcrne p15, 0x1, r0, c9, c0, 2 88_exit_init_l2_a15: 89 90 ret lr 91ENDPROC(tegra_init_l2_for_a15) 92 93/* 94 * tegra_sleep_cpu_finish(unsigned long v2p) 95 * 96 * enters suspend in LP2 by turning off the mmu and jumping to 97 * tegra?_tear_down_cpu 98 */ 99ENTRY(tegra_sleep_cpu_finish) 100 mov r4, r0 101 /* Flush and disable the L1 data cache */ 102 mov r0, #TEGRA_FLUSH_CACHE_ALL 103 bl tegra_disable_clean_inv_dcache 104 105 mov r0, r4 106 mov32 r6, tegra_tear_down_cpu 107 ldr r1, [r6] 108 add r1, r1, r0 109 110 mov32 r3, tegra_shut_off_mmu 111 add r3, r3, r0 112 mov r0, r1 113 114 ret r3 115ENDPROC(tegra_sleep_cpu_finish) 116 117/* 118 * tegra_shut_off_mmu 119 * 120 * r0 = physical address to jump to with mmu off 121 * 122 * called with VA=PA mapping 123 * turns off MMU, icache, dcache and branch prediction 124 */ 125 .align L1_CACHE_SHIFT 126 .pushsection .idmap.text, "ax" 127ENTRY(tegra_shut_off_mmu) 128 mrc p15, 0, r3, c1, c0, 0 129 movw r2, #CR_I | CR_Z | CR_C | CR_M 130 bic r3, r3, r2 131 dsb 132 mcr p15, 0, r3, c1, c0, 0 133 isb 134#ifdef CONFIG_CACHE_L2X0 135 /* Disable L2 cache */ 136 check_cpu_part_num 0xc09, r9, r10 137 movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) 138 movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) 139 moveq r3, #0 140 streq r3, [r2, #L2X0_CTRL] 141#endif 142 ret r0 143ENDPROC(tegra_shut_off_mmu) 144 .popsection 145 146/* 147 * tegra_switch_cpu_to_pllp 148 * 149 * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp 150 */ 151ENTRY(tegra_switch_cpu_to_pllp) 152 /* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */ 153 mov32 r5, TEGRA_CLK_RESET_BASE 154 mov r0, #(2 << 28) @ burst policy = run mode 155 orr r0, r0, #(4 << 4) @ use PLLP in run mode burst 156 str r0, [r5, #CLK_RESET_CCLK_BURST] 157 mov r0, #0 158 str r0, [r5, #CLK_RESET_CCLK_DIVIDER] 159 ret lr 160ENDPROC(tegra_switch_cpu_to_pllp) 161#endif 162