1/* 2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/linkage.h> 18 19#include <soc/tegra/flowctrl.h> 20#include <soc/tegra/fuse.h> 21 22#include <asm/asm-offsets.h> 23#include <asm/assembler.h> 24#include <asm/cache.h> 25 26#include "irammap.h" 27#include "sleep.h" 28 29#define EMC_CFG 0xc 30#define EMC_ADR_CFG 0x10 31#define EMC_TIMING_CONTROL 0x28 32#define EMC_NOP 0xdc 33#define EMC_SELF_REF 0xe0 34#define EMC_MRW 0xe8 35#define EMC_FBIO_CFG5 0x104 36#define EMC_AUTO_CAL_CONFIG 0x2a4 37#define EMC_AUTO_CAL_INTERVAL 0x2a8 38#define EMC_AUTO_CAL_STATUS 0x2ac 39#define EMC_REQ_CTRL 0x2b0 40#define EMC_CFG_DIG_DLL 0x2bc 41#define EMC_EMC_STATUS 0x2b4 42#define EMC_ZCAL_INTERVAL 0x2e0 43#define EMC_ZQ_CAL 0x2ec 44#define EMC_XM2VTTGENPADCTRL 0x310 45#define EMC_XM2VTTGENPADCTRL2 0x314 46 47#define MC_EMEM_ARB_CFG 0x90 48 49#define PMC_CTRL 0x0 50#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */ 51 52#define PMC_PLLP_WB0_OVERRIDE 0xf8 53#define PMC_IO_DPD_REQ 0x1b8 54#define PMC_IO_DPD_STATUS 0x1bc 55 56#define CLK_RESET_CCLK_BURST 0x20 57#define CLK_RESET_CCLK_DIVIDER 0x24 58#define CLK_RESET_SCLK_BURST 0x28 59#define CLK_RESET_SCLK_DIVIDER 0x2c 60 61#define CLK_RESET_PLLC_BASE 0x80 62#define CLK_RESET_PLLC_MISC 0x8c 63#define CLK_RESET_PLLM_BASE 0x90 64#define CLK_RESET_PLLM_MISC 0x9c 65#define CLK_RESET_PLLP_BASE 0xa0 66#define CLK_RESET_PLLP_MISC 0xac 67#define CLK_RESET_PLLA_BASE 0xb0 68#define CLK_RESET_PLLA_MISC 0xbc 69#define CLK_RESET_PLLX_BASE 0xe0 70#define CLK_RESET_PLLX_MISC 0xe4 71#define CLK_RESET_PLLX_MISC3 0x518 72#define CLK_RESET_PLLX_MISC3_IDDQ 3 73#define CLK_RESET_PLLM_MISC_IDDQ 5 74#define CLK_RESET_PLLC_MISC_IDDQ 26 75 76#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4 77 78#define MSELECT_CLKM (0x3 << 30) 79 80#define LOCK_DELAY 50 /* safety delay after lock is detected */ 81 82#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ 83 84.macro emc_device_mask, rd, base 85 ldr \rd, [\base, #EMC_ADR_CFG] 86 tst \rd, #0x1 87 moveq \rd, #(0x1 << 8) @ just 1 device 88 movne \rd, #(0x3 << 8) @ 2 devices 89.endm 90 91.macro emc_timing_update, rd, base 92 mov \rd, #1 93 str \rd, [\base, #EMC_TIMING_CONTROL] 941001: 95 ldr \rd, [\base, #EMC_EMC_STATUS] 96 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear 97 bne 1001b 98.endm 99 100.macro pll_enable, rd, r_car_base, pll_base, pll_misc 101 ldr \rd, [\r_car_base, #\pll_base] 102 tst \rd, #(1 << 30) 103 orreq \rd, \rd, #(1 << 30) 104 streq \rd, [\r_car_base, #\pll_base] 105 /* Enable lock detector */ 106 .if \pll_misc 107 ldr \rd, [\r_car_base, #\pll_misc] 108 bic \rd, \rd, #(1 << 18) 109 str \rd, [\r_car_base, #\pll_misc] 110 ldr \rd, [\r_car_base, #\pll_misc] 111 ldr \rd, [\r_car_base, #\pll_misc] 112 orr \rd, \rd, #(1 << 18) 113 str \rd, [\r_car_base, #\pll_misc] 114 .endif 115.endm 116 117.macro pll_locked, rd, r_car_base, pll_base 1181: 119 ldr \rd, [\r_car_base, #\pll_base] 120 tst \rd, #(1 << 27) 121 beq 1b 122.endm 123 124.macro pll_iddq_exit, rd, car, iddq, iddq_bit 125 ldr \rd, [\car, #\iddq] 126 bic \rd, \rd, #(1<<\iddq_bit) 127 str \rd, [\car, #\iddq] 128.endm 129 130.macro pll_iddq_entry, rd, car, iddq, iddq_bit 131 ldr \rd, [\car, #\iddq] 132 orr \rd, \rd, #(1<<\iddq_bit) 133 str \rd, [\car, #\iddq] 134.endm 135 136#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) 137/* 138 * tegra30_hotplug_shutdown(void) 139 * 140 * Powergates the current CPU. 141 * Should never return. 142 */ 143ENTRY(tegra30_hotplug_shutdown) 144 /* Powergate this CPU */ 145 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN 146 bl tegra30_cpu_shutdown 147 ret lr @ should never get here 148ENDPROC(tegra30_hotplug_shutdown) 149 150/* 151 * tegra30_cpu_shutdown(unsigned long flags) 152 * 153 * Puts the current CPU in wait-for-event mode on the flow controller 154 * and powergates it -- flags (in R0) indicate the request type. 155 * 156 * r10 = SoC ID 157 * corrupts r0-r4, r10-r12 158 */ 159ENTRY(tegra30_cpu_shutdown) 160 cpu_id r3 161 tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10 162 cmp r10, #TEGRA30 163 bne _no_cpu0_chk @ It's not Tegra30 164 165 cmp r3, #0 166 reteq lr @ Must never be called for CPU 0 167_no_cpu0_chk: 168 169 ldr r12, =TEGRA_FLOW_CTRL_VIRT 170 cpu_to_csr_reg r1, r3 171 add r1, r1, r12 @ virtual CSR address for this CPU 172 cpu_to_halt_reg r2, r3 173 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU 174 175 /* 176 * Clear this CPU's "event" and "interrupt" flags and power gate 177 * it when halting but not before it is in the "WFE" state. 178 */ 179 movw r12, \ 180 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ 181 FLOW_CTRL_CSR_ENABLE 182 cmp r10, #TEGRA30 183 moveq r4, #(1 << 4) @ wfe bitmap 184 movne r4, #(1 << 8) @ wfi bitmap 185 ARM( orr r12, r12, r4, lsl r3 ) 186 THUMB( lsl r4, r4, r3 ) 187 THUMB( orr r12, r12, r4 ) 188 str r12, [r1] 189 190 /* Halt this CPU. */ 191 mov r3, #0x400 192delay_1: 193 subs r3, r3, #1 @ delay as a part of wfe war. 194 bge delay_1; 195 cpsid a @ disable imprecise aborts. 196 ldr r3, [r1] @ read CSR 197 str r3, [r1] @ clear CSR 198 199 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN 200 beq flow_ctrl_setting_for_lp2 201 202 /* flow controller set up for hotplug */ 203 mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug 204 b flow_ctrl_done 205flow_ctrl_setting_for_lp2: 206 /* flow controller set up for LP2 */ 207 cmp r10, #TEGRA30 208 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 209 movne r3, #FLOW_CTRL_WAITEVENT 210 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ 211 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ 212flow_ctrl_done: 213 cmp r10, #TEGRA30 214 str r3, [r2] 215 ldr r0, [r2] 216 b wfe_war 217 218__cpu_reset_again: 219 dsb 220 .align 5 221 wfeeq @ CPU should be power gated here 222 wfine 223wfe_war: 224 b __cpu_reset_again 225 226 /* 227 * 38 nop's, which fills rest of wfe cache line and 228 * 4 more cachelines with nop 229 */ 230 .rept 38 231 nop 232 .endr 233 b . @ should never get here 234 235ENDPROC(tegra30_cpu_shutdown) 236#endif 237 238#ifdef CONFIG_PM_SLEEP 239/* 240 * tegra30_sleep_core_finish(unsigned long v2p) 241 * 242 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to 243 * tegra30_tear_down_core in IRAM 244 */ 245ENTRY(tegra30_sleep_core_finish) 246 mov r4, r0 247 /* Flush, disable the L1 data cache and exit SMP */ 248 mov r0, #TEGRA_FLUSH_CACHE_ALL 249 bl tegra_disable_clean_inv_dcache 250 mov r0, r4 251 252 /* 253 * Preload all the address literals that are needed for the 254 * CPU power-gating process, to avoid loading from SDRAM which 255 * are not supported once SDRAM is put into self-refresh. 256 * LP0 / LP1 use physical address, since the MMU needs to be 257 * disabled before putting SDRAM into self-refresh to avoid 258 * memory access due to page table walks. 259 */ 260 mov32 r4, TEGRA_PMC_BASE 261 mov32 r5, TEGRA_CLK_RESET_BASE 262 mov32 r6, TEGRA_FLOW_CTRL_BASE 263 mov32 r7, TEGRA_TMRUS_BASE 264 265 mov32 r3, tegra_shut_off_mmu 266 add r3, r3, r0 267 268 mov32 r0, tegra30_tear_down_core 269 mov32 r1, tegra30_iram_start 270 sub r0, r0, r1 271 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA 272 add r0, r0, r1 273 274 ret r3 275ENDPROC(tegra30_sleep_core_finish) 276 277/* 278 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p) 279 * 280 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. 281 */ 282ENTRY(tegra30_sleep_cpu_secondary_finish) 283 mov r7, lr 284 285 /* Flush and disable the L1 data cache */ 286 mov r0, #TEGRA_FLUSH_CACHE_LOUIS 287 bl tegra_disable_clean_inv_dcache 288 289 /* Powergate this CPU. */ 290 mov r0, #0 @ power mode flags (!hotplug) 291 bl tegra30_cpu_shutdown 292 mov r0, #1 @ never return here 293 ret r7 294ENDPROC(tegra30_sleep_cpu_secondary_finish) 295 296/* 297 * tegra30_tear_down_cpu 298 * 299 * Switches the CPU to enter sleep. 300 */ 301ENTRY(tegra30_tear_down_cpu) 302 mov32 r6, TEGRA_FLOW_CTRL_BASE 303 304 b tegra30_enter_sleep 305ENDPROC(tegra30_tear_down_cpu) 306 307/* START OF ROUTINES COPIED TO IRAM */ 308 .align L1_CACHE_SHIFT 309 .globl tegra30_iram_start 310tegra30_iram_start: 311 312/* 313 * tegra30_lp1_reset 314 * 315 * reset vector for LP1 restore; copied into IRAM during suspend. 316 * Brings the system back up to a safe staring point (SDRAM out of 317 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX, 318 * system clock running on the same PLL that it suspended at), and 319 * jumps to tegra_resume to restore virtual addressing. 320 * The physical address of tegra_resume expected to be stored in 321 * PMC_SCRATCH41. 322 * 323 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA. 324 */ 325ENTRY(tegra30_lp1_reset) 326 /* 327 * The CPU and system bus are running at 32KHz and executing from 328 * IRAM when this code is executed; immediately switch to CLKM and 329 * enable PLLP, PLLM, PLLC, PLLA and PLLX. 330 */ 331 mov32 r0, TEGRA_CLK_RESET_BASE 332 333 mov r1, #(1 << 28) 334 str r1, [r0, #CLK_RESET_SCLK_BURST] 335 str r1, [r0, #CLK_RESET_CCLK_BURST] 336 mov r1, #0 337 str r1, [r0, #CLK_RESET_CCLK_DIVIDER] 338 str r1, [r0, #CLK_RESET_SCLK_DIVIDER] 339 340 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 341 cmp r10, #TEGRA30 342 beq _no_pll_iddq_exit 343 344 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ 345 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ 346 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ 347 348 mov32 r7, TEGRA_TMRUS_BASE 349 ldr r1, [r7] 350 add r1, r1, #2 351 wait_until r1, r7, r3 352 353 /* enable PLLM via PMC */ 354 mov32 r2, TEGRA_PMC_BASE 355 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] 356 orr r1, r1, #(1 << 12) 357 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] 358 359 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0 360 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0 361 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0 362 363 b _pll_m_c_x_done 364 365_no_pll_iddq_exit: 366 /* enable PLLM via PMC */ 367 mov32 r2, TEGRA_PMC_BASE 368 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] 369 orr r1, r1, #(1 << 12) 370 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] 371 372 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC 373 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC 374 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC 375 376_pll_m_c_x_done: 377 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC 378 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC 379 380 pll_locked r1, r0, CLK_RESET_PLLM_BASE 381 pll_locked r1, r0, CLK_RESET_PLLP_BASE 382 pll_locked r1, r0, CLK_RESET_PLLA_BASE 383 pll_locked r1, r0, CLK_RESET_PLLC_BASE 384 pll_locked r1, r0, CLK_RESET_PLLX_BASE 385 386 mov32 r7, TEGRA_TMRUS_BASE 387 ldr r1, [r7] 388 add r1, r1, #LOCK_DELAY 389 wait_until r1, r7, r3 390 391 adr r5, tegra_sdram_pad_save 392 393 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT 394 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] 395 396 ldr r4, [r5, #0x1C] @ restore SCLK_BURST 397 str r4, [r0, #CLK_RESET_SCLK_BURST] 398 399 cmp r10, #TEGRA30 400 movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX 401 movteq r4, #:upper16:((1 << 28) | (0x8)) 402 movwne r4, #:lower16:((1 << 28) | (0xe)) 403 movtne r4, #:upper16:((1 << 28) | (0xe)) 404 str r4, [r0, #CLK_RESET_CCLK_BURST] 405 406 /* Restore pad power state to normal */ 407 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS 408 mvn r1, r1 409 bic r1, r1, #(1 << 31) 410 orr r1, r1, #(1 << 30) 411 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF 412 413 cmp r10, #TEGRA30 414 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base 415 movteq r0, #:upper16:TEGRA_EMC_BASE 416 cmp r10, #TEGRA114 417 movweq r0, #:lower16:TEGRA_EMC0_BASE 418 movteq r0, #:upper16:TEGRA_EMC0_BASE 419 cmp r10, #TEGRA124 420 movweq r0, #:lower16:TEGRA124_EMC_BASE 421 movteq r0, #:upper16:TEGRA124_EMC_BASE 422 423 cmp r10, #TEGRA30 424 moveq r2, #0x20 425 movweq r4, #:lower16:TEGRA_MC_BASE 426 movteq r4, #:upper16:TEGRA_MC_BASE 427 cmp r10, #TEGRA114 428 moveq r2, #0x34 429 movweq r4, #:lower16:TEGRA114_MC_BASE 430 movteq r4, #:upper16:TEGRA114_MC_BASE 431 cmp r10, #TEGRA124 432 moveq r2, #0x20 433 movweq r4, #:lower16:TEGRA124_MC_BASE 434 movteq r4, #:upper16:TEGRA124_MC_BASE 435 436 ldr r1, [r5, r2] @ restore MC_EMEM_ARB_CFG 437 str r1, [r4, #MC_EMEM_ARB_CFG] 438 439exit_self_refresh: 440 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL 441 str r1, [r0, #EMC_XM2VTTGENPADCTRL] 442 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2 443 str r1, [r0, #EMC_XM2VTTGENPADCTRL2] 444 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL 445 str r1, [r0, #EMC_AUTO_CAL_INTERVAL] 446 447 /* Relock DLL */ 448 ldr r1, [r0, #EMC_CFG_DIG_DLL] 449 orr r1, r1, #(1 << 30) @ set DLL_RESET 450 str r1, [r0, #EMC_CFG_DIG_DLL] 451 452 emc_timing_update r1, r0 453 454 cmp r10, #TEGRA114 455 movweq r1, #:lower16:TEGRA_EMC1_BASE 456 movteq r1, #:upper16:TEGRA_EMC1_BASE 457 cmpeq r0, r1 458 459 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG] 460 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE 461 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1 462 str r1, [r0, #EMC_AUTO_CAL_CONFIG] 463 464emc_wait_auto_cal_onetime: 465 ldr r1, [r0, #EMC_AUTO_CAL_STATUS] 466 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared 467 bne emc_wait_auto_cal_onetime 468 469 ldr r1, [r0, #EMC_CFG] 470 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD 471 str r1, [r0, #EMC_CFG] 472 473 mov r1, #0 474 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh 475 mov r1, #1 476 cmp r10, #TEGRA30 477 streq r1, [r0, #EMC_NOP] 478 streq r1, [r0, #EMC_NOP] 479 480 emc_device_mask r1, r0 481 482exit_selfrefresh_loop: 483 ldr r2, [r0, #EMC_EMC_STATUS] 484 ands r2, r2, r1 485 bne exit_selfrefresh_loop 486 487 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1 488 489 mov32 r7, TEGRA_TMRUS_BASE 490 ldr r2, [r0, #EMC_FBIO_CFG5] 491 492 and r2, r2, #3 @ check DRAM_TYPE 493 cmp r2, #2 494 beq emc_lpddr2 495 496 /* Issue a ZQ_CAL for dev0 - DDR3 */ 497 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1 498 str r2, [r0, #EMC_ZQ_CAL] 499 ldr r2, [r7] 500 add r2, r2, #10 501 wait_until r2, r7, r3 502 503 tst r1, #2 504 beq zcal_done 505 506 /* Issue a ZQ_CAL for dev1 - DDR3 */ 507 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1 508 str r2, [r0, #EMC_ZQ_CAL] 509 ldr r2, [r7] 510 add r2, r2, #10 511 wait_until r2, r7, r3 512 b zcal_done 513 514emc_lpddr2: 515 /* Issue a ZQ_CAL for dev0 - LPDDR2 */ 516 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB 517 str r2, [r0, #EMC_MRW] 518 ldr r2, [r7] 519 add r2, r2, #1 520 wait_until r2, r7, r3 521 522 tst r1, #2 523 beq zcal_done 524 525 /* Issue a ZQ_CAL for dev0 - LPDDR2 */ 526 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB 527 str r2, [r0, #EMC_MRW] 528 ldr r2, [r7] 529 add r2, r2, #1 530 wait_until r2, r7, r3 531 532zcal_done: 533 mov r1, #0 @ unstall all transactions 534 str r1, [r0, #EMC_REQ_CTRL] 535 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL 536 str r1, [r0, #EMC_ZCAL_INTERVAL] 537 ldr r1, [r5, #0x0] @ restore EMC_CFG 538 str r1, [r0, #EMC_CFG] 539 540 emc_timing_update r1, r0 541 542 /* Tegra114 had dual EMC channel, now config the other one */ 543 cmp r10, #TEGRA114 544 bne __no_dual_emc_chanl 545 mov32 r1, TEGRA_EMC1_BASE 546 cmp r0, r1 547 movne r0, r1 548 addne r5, r5, #0x20 549 bne exit_self_refresh 550__no_dual_emc_chanl: 551 552 mov32 r0, TEGRA_PMC_BASE 553 ldr r0, [r0, #PMC_SCRATCH41] 554 ret r0 @ jump to tegra_resume 555ENDPROC(tegra30_lp1_reset) 556 557 .align L1_CACHE_SHIFT 558tegra30_sdram_pad_address: 559 .word TEGRA_EMC_BASE + EMC_CFG @0x0 560 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4 561 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 562 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc 563 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 564 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 565 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 566 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c 567 .word TEGRA_MC_BASE + MC_EMEM_ARB_CFG @0x20 568tegra30_sdram_pad_address_end: 569 570tegra114_sdram_pad_address: 571 .word TEGRA_EMC0_BASE + EMC_CFG @0x0 572 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4 573 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8 574 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc 575 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 576 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 577 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 578 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c 579 .word TEGRA_EMC1_BASE + EMC_CFG @0x20 580 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24 581 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28 582 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c 583 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 584 .word TEGRA114_MC_BASE + MC_EMEM_ARB_CFG @0x34 585tegra114_sdram_pad_adress_end: 586 587tegra124_sdram_pad_address: 588 .word TEGRA124_EMC_BASE + EMC_CFG @0x0 589 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4 590 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 591 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc 592 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 593 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 594 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 595 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c 596 .word TEGRA124_MC_BASE + MC_EMEM_ARB_CFG @0x20 597tegra124_sdram_pad_address_end: 598 599tegra30_sdram_pad_size: 600 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address 601 602tegra114_sdram_pad_size: 603 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address 604 605 .type tegra_sdram_pad_save, %object 606tegra_sdram_pad_save: 607 .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4 608 .long 0 609 .endr 610 611/* 612 * tegra30_tear_down_core 613 * 614 * copied into and executed from IRAM 615 * puts memory in self-refresh for LP0 and LP1 616 */ 617tegra30_tear_down_core: 618 bl tegra30_sdram_self_refresh 619 bl tegra30_switch_cpu_to_clk32k 620 b tegra30_enter_sleep 621 622/* 623 * tegra30_switch_cpu_to_clk32k 624 * 625 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK 626 * to the 32KHz clock. 627 * r4 = TEGRA_PMC_BASE 628 * r5 = TEGRA_CLK_RESET_BASE 629 * r6 = TEGRA_FLOW_CTRL_BASE 630 * r7 = TEGRA_TMRUS_BASE 631 * r10= SoC ID 632 */ 633tegra30_switch_cpu_to_clk32k: 634 /* 635 * start by jumping to CLKM to safely disable PLLs, then jump to 636 * CLKS. 637 */ 638 mov r0, #(1 << 28) 639 str r0, [r5, #CLK_RESET_SCLK_BURST] 640 /* 2uS delay delay between changing SCLK and CCLK */ 641 ldr r1, [r7] 642 add r1, r1, #2 643 wait_until r1, r7, r9 644 str r0, [r5, #CLK_RESET_CCLK_BURST] 645 mov r0, #0 646 str r0, [r5, #CLK_RESET_CCLK_DIVIDER] 647 str r0, [r5, #CLK_RESET_SCLK_DIVIDER] 648 649 /* switch the clock source of mselect to be CLK_M */ 650 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] 651 orr r0, r0, #MSELECT_CLKM 652 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT] 653 654 /* 2uS delay delay between changing SCLK and disabling PLLs */ 655 ldr r1, [r7] 656 add r1, r1, #2 657 wait_until r1, r7, r9 658 659 /* disable PLLM via PMC in LP1 */ 660 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] 661 bic r0, r0, #(1 << 12) 662 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] 663 664 /* disable PLLP, PLLA, PLLC and PLLX */ 665 ldr r0, [r5, #CLK_RESET_PLLP_BASE] 666 bic r0, r0, #(1 << 30) 667 str r0, [r5, #CLK_RESET_PLLP_BASE] 668 ldr r0, [r5, #CLK_RESET_PLLA_BASE] 669 bic r0, r0, #(1 << 30) 670 str r0, [r5, #CLK_RESET_PLLA_BASE] 671 ldr r0, [r5, #CLK_RESET_PLLC_BASE] 672 bic r0, r0, #(1 << 30) 673 str r0, [r5, #CLK_RESET_PLLC_BASE] 674 ldr r0, [r5, #CLK_RESET_PLLX_BASE] 675 bic r0, r0, #(1 << 30) 676 str r0, [r5, #CLK_RESET_PLLX_BASE] 677 678 cmp r10, #TEGRA30 679 beq _no_pll_in_iddq 680 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ 681_no_pll_in_iddq: 682 683 /* switch to CLKS */ 684 mov r0, #0 /* brust policy = 32KHz */ 685 str r0, [r5, #CLK_RESET_SCLK_BURST] 686 687 ret lr 688 689/* 690 * tegra30_enter_sleep 691 * 692 * uses flow controller to enter sleep state 693 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1 694 * executes from SDRAM with target state is LP2 695 * r6 = TEGRA_FLOW_CTRL_BASE 696 */ 697tegra30_enter_sleep: 698 cpu_id r1 699 700 cpu_to_csr_reg r2, r1 701 ldr r0, [r6, r2] 702 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG 703 orr r0, r0, #FLOW_CTRL_CSR_ENABLE 704 str r0, [r6, r2] 705 706 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 707 cmp r10, #TEGRA30 708 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT 709 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ 710 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ 711 712 cpu_to_halt_reg r2, r1 713 str r0, [r6, r2] 714 dsb 715 ldr r0, [r6, r2] /* memory barrier */ 716 717halted: 718 isb 719 dsb 720 wfi /* CPU should be power gated here */ 721 722 /* !!!FIXME!!! Implement halt failure handler */ 723 b halted 724 725/* 726 * tegra30_sdram_self_refresh 727 * 728 * called with MMU off and caches disabled 729 * must be executed from IRAM 730 * r4 = TEGRA_PMC_BASE 731 * r5 = TEGRA_CLK_RESET_BASE 732 * r6 = TEGRA_FLOW_CTRL_BASE 733 * r7 = TEGRA_TMRUS_BASE 734 * r10= SoC ID 735 */ 736tegra30_sdram_self_refresh: 737 738 adr r8, tegra_sdram_pad_save 739 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 740 cmp r10, #TEGRA30 741 adreq r2, tegra30_sdram_pad_address 742 ldreq r3, tegra30_sdram_pad_size 743 cmp r10, #TEGRA114 744 adreq r2, tegra114_sdram_pad_address 745 ldreq r3, tegra114_sdram_pad_size 746 cmp r10, #TEGRA124 747 adreq r2, tegra124_sdram_pad_address 748 ldreq r3, tegra30_sdram_pad_size 749 750 mov r9, #0 751 752padsave: 753 ldr r0, [r2, r9] @ r0 is the addr in the pad_address 754 755 ldr r1, [r0] 756 str r1, [r8, r9] @ save the content of the addr 757 758 add r9, r9, #4 759 cmp r3, r9 760 bne padsave 761padsave_done: 762 763 dsb 764 765 cmp r10, #TEGRA30 766 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr 767 cmp r10, #TEGRA114 768 ldreq r0, =TEGRA_EMC0_BASE 769 cmp r10, #TEGRA124 770 ldreq r0, =TEGRA124_EMC_BASE 771 772enter_self_refresh: 773 cmp r10, #TEGRA30 774 mov r1, #0 775 str r1, [r0, #EMC_ZCAL_INTERVAL] 776 str r1, [r0, #EMC_AUTO_CAL_INTERVAL] 777 ldr r1, [r0, #EMC_CFG] 778 bic r1, r1, #(1 << 28) 779 bicne r1, r1, #(1 << 29) 780 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF 781 782 emc_timing_update r1, r0 783 784 ldr r1, [r7] 785 add r1, r1, #5 786 wait_until r1, r7, r2 787 788emc_wait_auto_cal: 789 ldr r1, [r0, #EMC_AUTO_CAL_STATUS] 790 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared 791 bne emc_wait_auto_cal 792 793 mov r1, #3 794 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests 795 796emcidle: 797 ldr r1, [r0, #EMC_EMC_STATUS] 798 tst r1, #4 799 beq emcidle 800 801 mov r1, #1 802 str r1, [r0, #EMC_SELF_REF] 803 804 emc_device_mask r1, r0 805 806emcself: 807 ldr r2, [r0, #EMC_EMC_STATUS] 808 and r2, r2, r1 809 cmp r2, r1 810 bne emcself @ loop until DDR in self-refresh 811 812 /* Put VTTGEN in the lowest power mode */ 813 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL] 814 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN 815 and r1, r1, r2 816 str r1, [r0, #EMC_XM2VTTGENPADCTRL] 817 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2] 818 cmp r10, #TEGRA30 819 orreq r1, r1, #7 @ set E_NO_VTTGEN 820 orrne r1, r1, #0x3f 821 str r1, [r0, #EMC_XM2VTTGENPADCTRL2] 822 823 emc_timing_update r1, r0 824 825 /* Tegra114 had dual EMC channel, now config the other one */ 826 cmp r10, #TEGRA114 827 bne no_dual_emc_chanl 828 mov32 r1, TEGRA_EMC1_BASE 829 cmp r0, r1 830 movne r0, r1 831 bne enter_self_refresh 832no_dual_emc_chanl: 833 834 ldr r1, [r4, #PMC_CTRL] 835 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0 836 bne pmc_io_dpd_skip 837 /* 838 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK 839 * and COMP in the lowest power mode when LP1. 840 */ 841 mov32 r1, 0x8EC00000 842 str r1, [r4, #PMC_IO_DPD_REQ] 843pmc_io_dpd_skip: 844 845 dsb 846 847 ret lr 848 849 .ltorg 850/* dummy symbol for end of IRAM */ 851 .align L1_CACHE_SHIFT 852 .global tegra30_iram_end 853tegra30_iram_end: 854 b . 855#endif 856