1/*
2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/linkage.h>
18
19#include <soc/tegra/flowctrl.h>
20#include <soc/tegra/fuse.h>
21
22#include <asm/asm-offsets.h>
23#include <asm/assembler.h>
24#include <asm/cache.h>
25
26#include "irammap.h"
27#include "sleep.h"
28
29#define EMC_CFG				0xc
30#define EMC_ADR_CFG			0x10
31#define EMC_TIMING_CONTROL		0x28
32#define EMC_NOP				0xdc
33#define EMC_SELF_REF			0xe0
34#define EMC_MRW				0xe8
35#define EMC_FBIO_CFG5			0x104
36#define EMC_AUTO_CAL_CONFIG		0x2a4
37#define EMC_AUTO_CAL_INTERVAL		0x2a8
38#define EMC_AUTO_CAL_STATUS		0x2ac
39#define EMC_REQ_CTRL			0x2b0
40#define EMC_CFG_DIG_DLL			0x2bc
41#define EMC_EMC_STATUS			0x2b4
42#define EMC_ZCAL_INTERVAL		0x2e0
43#define EMC_ZQ_CAL			0x2ec
44#define EMC_XM2VTTGENPADCTRL		0x310
45#define EMC_XM2VTTGENPADCTRL2		0x314
46
47#define PMC_CTRL			0x0
48#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
49
50#define PMC_PLLP_WB0_OVERRIDE		0xf8
51#define PMC_IO_DPD_REQ			0x1b8
52#define PMC_IO_DPD_STATUS		0x1bc
53
54#define CLK_RESET_CCLK_BURST		0x20
55#define CLK_RESET_CCLK_DIVIDER		0x24
56#define CLK_RESET_SCLK_BURST		0x28
57#define CLK_RESET_SCLK_DIVIDER		0x2c
58
59#define CLK_RESET_PLLC_BASE		0x80
60#define CLK_RESET_PLLC_MISC		0x8c
61#define CLK_RESET_PLLM_BASE		0x90
62#define CLK_RESET_PLLM_MISC		0x9c
63#define CLK_RESET_PLLP_BASE		0xa0
64#define CLK_RESET_PLLP_MISC		0xac
65#define CLK_RESET_PLLA_BASE		0xb0
66#define CLK_RESET_PLLA_MISC		0xbc
67#define CLK_RESET_PLLX_BASE		0xe0
68#define CLK_RESET_PLLX_MISC		0xe4
69#define CLK_RESET_PLLX_MISC3		0x518
70#define CLK_RESET_PLLX_MISC3_IDDQ	3
71#define CLK_RESET_PLLM_MISC_IDDQ	5
72#define CLK_RESET_PLLC_MISC_IDDQ	26
73
74#define CLK_RESET_CLK_SOURCE_MSELECT	0x3b4
75
76#define MSELECT_CLKM			(0x3 << 30)
77
78#define LOCK_DELAY 50 /* safety delay after lock is detected */
79
80#define TEGRA30_POWER_HOTPLUG_SHUTDOWN	(1 << 27) /* Hotplug shutdown */
81
82.macro emc_device_mask, rd, base
83	ldr	\rd, [\base, #EMC_ADR_CFG]
84	tst	\rd, #0x1
85	moveq	\rd, #(0x1 << 8)		@ just 1 device
86	movne	\rd, #(0x3 << 8)		@ 2 devices
87.endm
88
89.macro emc_timing_update, rd, base
90	mov	\rd, #1
91	str	\rd, [\base, #EMC_TIMING_CONTROL]
921001:
93	ldr	\rd, [\base, #EMC_EMC_STATUS]
94	tst	\rd, #(0x1<<23)	@ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
95	bne	1001b
96.endm
97
98.macro pll_enable, rd, r_car_base, pll_base, pll_misc
99	ldr	\rd, [\r_car_base, #\pll_base]
100	tst	\rd, #(1 << 30)
101	orreq	\rd, \rd, #(1 << 30)
102	streq	\rd, [\r_car_base, #\pll_base]
103	/* Enable lock detector */
104	.if	\pll_misc
105	ldr	\rd, [\r_car_base, #\pll_misc]
106	bic	\rd, \rd, #(1 << 18)
107	str	\rd, [\r_car_base, #\pll_misc]
108	ldr	\rd, [\r_car_base, #\pll_misc]
109	ldr	\rd, [\r_car_base, #\pll_misc]
110	orr	\rd, \rd, #(1 << 18)
111	str	\rd, [\r_car_base, #\pll_misc]
112	.endif
113.endm
114
115.macro pll_locked, rd, r_car_base, pll_base
1161:
117	ldr	\rd, [\r_car_base, #\pll_base]
118	tst	\rd, #(1 << 27)
119	beq	1b
120.endm
121
122.macro pll_iddq_exit, rd, car, iddq, iddq_bit
123	ldr	\rd, [\car, #\iddq]
124	bic	\rd, \rd, #(1<<\iddq_bit)
125	str	\rd, [\car, #\iddq]
126.endm
127
128.macro pll_iddq_entry, rd, car, iddq, iddq_bit
129	ldr	\rd, [\car, #\iddq]
130	orr	\rd, \rd, #(1<<\iddq_bit)
131	str	\rd, [\car, #\iddq]
132.endm
133
134#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
135/*
136 * tegra30_hotplug_shutdown(void)
137 *
138 * Powergates the current CPU.
139 * Should never return.
140 */
141ENTRY(tegra30_hotplug_shutdown)
142	/* Powergate this CPU */
143	mov	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
144	bl	tegra30_cpu_shutdown
145	ret	lr			@ should never get here
146ENDPROC(tegra30_hotplug_shutdown)
147
148/*
149 * tegra30_cpu_shutdown(unsigned long flags)
150 *
151 * Puts the current CPU in wait-for-event mode on the flow controller
152 * and powergates it -- flags (in R0) indicate the request type.
153 *
154 * r10 = SoC ID
155 * corrupts r0-r4, r10-r12
156 */
157ENTRY(tegra30_cpu_shutdown)
158	cpu_id	r3
159	tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
160	cmp	r10, #TEGRA30
161	bne	_no_cpu0_chk	@ It's not Tegra30
162
163	cmp	r3, #0
164	reteq	lr		@ Must never be called for CPU 0
165_no_cpu0_chk:
166
167	ldr	r12, =TEGRA_FLOW_CTRL_VIRT
168	cpu_to_csr_reg r1, r3
169	add	r1, r1, r12	@ virtual CSR address for this CPU
170	cpu_to_halt_reg r2, r3
171	add	r2, r2, r12	@ virtual HALT_EVENTS address for this CPU
172
173	/*
174	 * Clear this CPU's "event" and "interrupt" flags and power gate
175	 * it when halting but not before it is in the "WFE" state.
176	 */
177	movw	r12, \
178		FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
179		FLOW_CTRL_CSR_ENABLE
180	cmp	r10, #TEGRA30
181	moveq	r4, #(1 << 4)			@ wfe bitmap
182	movne	r4, #(1 << 8)			@ wfi bitmap
183 ARM(	orr	r12, r12, r4, lsl r3	)
184 THUMB(	lsl	r4, r4, r3		)
185 THUMB(	orr	r12, r12, r4		)
186	str	r12, [r1]
187
188	/* Halt this CPU. */
189	mov	r3, #0x400
190delay_1:
191	subs	r3, r3, #1			@ delay as a part of wfe war.
192	bge	delay_1;
193	cpsid	a				@ disable imprecise aborts.
194	ldr	r3, [r1]			@ read CSR
195	str	r3, [r1]			@ clear CSR
196
197	tst	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
198	beq	flow_ctrl_setting_for_lp2
199
200	/* flow controller set up for hotplug */
201	mov	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
202	b	flow_ctrl_done
203flow_ctrl_setting_for_lp2:
204	/* flow controller set up for LP2 */
205	cmp	r10, #TEGRA30
206	moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT	@ For LP2
207	movne	r3, #FLOW_CTRL_WAITEVENT
208	orrne	r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
209	orrne	r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
210flow_ctrl_done:
211	cmp	r10, #TEGRA30
212	str	r3, [r2]
213	ldr	r0, [r2]
214	b	wfe_war
215
216__cpu_reset_again:
217	dsb
218	.align 5
219	wfeeq					@ CPU should be power gated here
220	wfine
221wfe_war:
222	b	__cpu_reset_again
223
224	/*
225	 * 38 nop's, which fills rest of wfe cache line and
226	 * 4 more cachelines with nop
227	 */
228	.rept 38
229	nop
230	.endr
231	b	.				@ should never get here
232
233ENDPROC(tegra30_cpu_shutdown)
234#endif
235
236#ifdef CONFIG_PM_SLEEP
237/*
238 * tegra30_sleep_core_finish(unsigned long v2p)
239 *
240 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
241 * tegra30_tear_down_core in IRAM
242 */
243ENTRY(tegra30_sleep_core_finish)
244	mov	r4, r0
245	/* Flush, disable the L1 data cache and exit SMP */
246	mov	r0, #TEGRA_FLUSH_CACHE_ALL
247	bl	tegra_disable_clean_inv_dcache
248	mov	r0, r4
249
250	/*
251	 * Preload all the address literals that are needed for the
252	 * CPU power-gating process, to avoid loading from SDRAM which
253	 * are not supported once SDRAM is put into self-refresh.
254	 * LP0 / LP1 use physical address, since the MMU needs to be
255	 * disabled before putting SDRAM into self-refresh to avoid
256	 * memory access due to page table walks.
257	 */
258	mov32	r4, TEGRA_PMC_BASE
259	mov32	r5, TEGRA_CLK_RESET_BASE
260	mov32	r6, TEGRA_FLOW_CTRL_BASE
261	mov32	r7, TEGRA_TMRUS_BASE
262
263	mov32	r3, tegra_shut_off_mmu
264	add	r3, r3, r0
265
266	mov32	r0, tegra30_tear_down_core
267	mov32	r1, tegra30_iram_start
268	sub	r0, r0, r1
269	mov32	r1, TEGRA_IRAM_LPx_RESUME_AREA
270	add	r0, r0, r1
271
272	ret	r3
273ENDPROC(tegra30_sleep_core_finish)
274
275/*
276 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
277 *
278 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
279 */
280ENTRY(tegra30_sleep_cpu_secondary_finish)
281	mov	r7, lr
282
283	/* Flush and disable the L1 data cache */
284	mov 	r0, #TEGRA_FLUSH_CACHE_LOUIS
285	bl	tegra_disable_clean_inv_dcache
286
287	/* Powergate this CPU. */
288	mov	r0, #0                          @ power mode flags (!hotplug)
289	bl	tegra30_cpu_shutdown
290	mov	r0, #1                          @ never return here
291	ret	r7
292ENDPROC(tegra30_sleep_cpu_secondary_finish)
293
294/*
295 * tegra30_tear_down_cpu
296 *
297 * Switches the CPU to enter sleep.
298 */
299ENTRY(tegra30_tear_down_cpu)
300	mov32	r6, TEGRA_FLOW_CTRL_BASE
301
302	b	tegra30_enter_sleep
303ENDPROC(tegra30_tear_down_cpu)
304
305/* START OF ROUTINES COPIED TO IRAM */
306	.align L1_CACHE_SHIFT
307	.globl tegra30_iram_start
308tegra30_iram_start:
309
310/*
311 * tegra30_lp1_reset
312 *
313 * reset vector for LP1 restore; copied into IRAM during suspend.
314 * Brings the system back up to a safe staring point (SDRAM out of
315 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
316 * system clock running on the same PLL that it suspended at), and
317 * jumps to tegra_resume to restore virtual addressing.
318 * The physical address of tegra_resume expected to be stored in
319 * PMC_SCRATCH41.
320 *
321 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
322 */
323ENTRY(tegra30_lp1_reset)
324	/*
325	 * The CPU and system bus are running at 32KHz and executing from
326	 * IRAM when this code is executed; immediately switch to CLKM and
327	 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
328	 */
329	mov32	r0, TEGRA_CLK_RESET_BASE
330
331	mov	r1, #(1 << 28)
332	str	r1, [r0, #CLK_RESET_SCLK_BURST]
333	str	r1, [r0, #CLK_RESET_CCLK_BURST]
334	mov	r1, #0
335	str	r1, [r0, #CLK_RESET_CCLK_DIVIDER]
336	str	r1, [r0, #CLK_RESET_SCLK_DIVIDER]
337
338	tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
339	cmp	r10, #TEGRA30
340	beq	_no_pll_iddq_exit
341
342	pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
343	pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
344	pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
345
346	mov32	r7, TEGRA_TMRUS_BASE
347	ldr	r1, [r7]
348	add	r1, r1, #2
349	wait_until r1, r7, r3
350
351	/* enable PLLM via PMC */
352	mov32	r2, TEGRA_PMC_BASE
353	ldr	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
354	orr	r1, r1, #(1 << 12)
355	str	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
356
357	pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
358	pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
359	pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
360
361	b	_pll_m_c_x_done
362
363_no_pll_iddq_exit:
364	/* enable PLLM via PMC */
365	mov32	r2, TEGRA_PMC_BASE
366	ldr	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
367	orr	r1, r1, #(1 << 12)
368	str	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
369
370	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
371	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
372	pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
373
374_pll_m_c_x_done:
375	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
376	pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
377
378	pll_locked r1, r0, CLK_RESET_PLLM_BASE
379	pll_locked r1, r0, CLK_RESET_PLLP_BASE
380	pll_locked r1, r0, CLK_RESET_PLLA_BASE
381	pll_locked r1, r0, CLK_RESET_PLLC_BASE
382	pll_locked r1, r0, CLK_RESET_PLLX_BASE
383
384	mov32	r7, TEGRA_TMRUS_BASE
385	ldr	r1, [r7]
386	add	r1, r1, #LOCK_DELAY
387	wait_until r1, r7, r3
388
389	adr	r5, tegra_sdram_pad_save
390
391	ldr	r4, [r5, #0x18]		@ restore CLK_SOURCE_MSELECT
392	str	r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
393
394	ldr	r4, [r5, #0x1C]		@ restore SCLK_BURST
395	str	r4, [r0, #CLK_RESET_SCLK_BURST]
396
397	cmp	r10, #TEGRA30
398	movweq	r4, #:lower16:((1 << 28) | (0x8))	@ burst policy is PLLX
399	movteq	r4, #:upper16:((1 << 28) | (0x8))
400	movwne	r4, #:lower16:((1 << 28) | (0xe))
401	movtne	r4, #:upper16:((1 << 28) | (0xe))
402	str	r4, [r0, #CLK_RESET_CCLK_BURST]
403
404	/* Restore pad power state to normal */
405	ldr	r1, [r5, #0x14]		@ PMC_IO_DPD_STATUS
406	mvn	r1, r1
407	bic	r1, r1, #(1 << 31)
408	orr	r1, r1, #(1 << 30)
409	str	r1, [r2, #PMC_IO_DPD_REQ]	@ DPD_OFF
410
411	cmp	r10, #TEGRA30
412	movweq	r0, #:lower16:TEGRA_EMC_BASE	@ r0 reserved for emc base
413	movteq	r0, #:upper16:TEGRA_EMC_BASE
414	cmp	r10, #TEGRA114
415	movweq	r0, #:lower16:TEGRA_EMC0_BASE
416	movteq	r0, #:upper16:TEGRA_EMC0_BASE
417	cmp	r10, #TEGRA124
418	movweq	r0, #:lower16:TEGRA124_EMC_BASE
419	movteq	r0, #:upper16:TEGRA124_EMC_BASE
420
421exit_self_refresh:
422	ldr	r1, [r5, #0xC]		@ restore EMC_XM2VTTGENPADCTRL
423	str	r1, [r0, #EMC_XM2VTTGENPADCTRL]
424	ldr	r1, [r5, #0x10]		@ restore EMC_XM2VTTGENPADCTRL2
425	str	r1, [r0, #EMC_XM2VTTGENPADCTRL2]
426	ldr	r1, [r5, #0x8]		@ restore EMC_AUTO_CAL_INTERVAL
427	str	r1, [r0, #EMC_AUTO_CAL_INTERVAL]
428
429	/* Relock DLL */
430	ldr	r1, [r0, #EMC_CFG_DIG_DLL]
431	orr	r1, r1, #(1 << 30)	@ set DLL_RESET
432	str	r1, [r0, #EMC_CFG_DIG_DLL]
433
434	emc_timing_update r1, r0
435
436	cmp	r10, #TEGRA114
437	movweq	r1, #:lower16:TEGRA_EMC1_BASE
438	movteq	r1, #:upper16:TEGRA_EMC1_BASE
439	cmpeq	r0, r1
440
441	ldr	r1, [r0, #EMC_AUTO_CAL_CONFIG]
442	orr	r1, r1, #(1 << 31)	@ set AUTO_CAL_ACTIVE
443	orreq	r1, r1, #(1 << 27)	@ set slave mode for channel 1
444	str	r1, [r0, #EMC_AUTO_CAL_CONFIG]
445
446emc_wait_auto_cal_onetime:
447	ldr	r1, [r0, #EMC_AUTO_CAL_STATUS]
448	tst	r1, #(1 << 31)		@ wait until AUTO_CAL_ACTIVE is cleared
449	bne	emc_wait_auto_cal_onetime
450
451	ldr	r1, [r0, #EMC_CFG]
452	bic	r1, r1, #(1 << 31)	@ disable DRAM_CLK_STOP_PD
453	str	r1, [r0, #EMC_CFG]
454
455	mov	r1, #0
456	str	r1, [r0, #EMC_SELF_REF]	@ take DRAM out of self refresh
457	mov	r1, #1
458	cmp	r10, #TEGRA30
459	streq	r1, [r0, #EMC_NOP]
460	streq	r1, [r0, #EMC_NOP]
461
462	emc_device_mask r1, r0
463
464exit_selfrefresh_loop:
465	ldr	r2, [r0, #EMC_EMC_STATUS]
466	ands	r2, r2, r1
467	bne	exit_selfrefresh_loop
468
469	lsr	r1, r1, #8		@ devSel, bit0:dev0, bit1:dev1
470
471	mov32	r7, TEGRA_TMRUS_BASE
472	ldr	r2, [r0, #EMC_FBIO_CFG5]
473
474	and	r2, r2,	#3		@ check DRAM_TYPE
475	cmp	r2, #2
476	beq	emc_lpddr2
477
478	/* Issue a ZQ_CAL for dev0 - DDR3 */
479	mov32	r2, 0x80000011		@ DEV_SELECTION=2, LENGTH=LONG, CMD=1
480	str	r2, [r0, #EMC_ZQ_CAL]
481	ldr	r2, [r7]
482	add	r2, r2, #10
483	wait_until r2, r7, r3
484
485	tst	r1, #2
486	beq	zcal_done
487
488	/* Issue a ZQ_CAL for dev1 - DDR3 */
489	mov32	r2, 0x40000011		@ DEV_SELECTION=1, LENGTH=LONG, CMD=1
490	str	r2, [r0, #EMC_ZQ_CAL]
491	ldr	r2, [r7]
492	add	r2, r2, #10
493	wait_until r2, r7, r3
494	b	zcal_done
495
496emc_lpddr2:
497	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
498	mov32	r2, 0x800A00AB		@ DEV_SELECTION=2, MA=10, OP=0xAB
499	str	r2, [r0, #EMC_MRW]
500	ldr	r2, [r7]
501	add	r2, r2, #1
502	wait_until r2, r7, r3
503
504	tst	r1, #2
505	beq	zcal_done
506
507	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
508	mov32	r2, 0x400A00AB		@ DEV_SELECTION=1, MA=10, OP=0xAB
509	str	r2, [r0, #EMC_MRW]
510	ldr	r2, [r7]
511	add	r2, r2, #1
512	wait_until r2, r7, r3
513
514zcal_done:
515	mov	r1, #0			@ unstall all transactions
516	str	r1, [r0, #EMC_REQ_CTRL]
517	ldr	r1, [r5, #0x4]		@ restore EMC_ZCAL_INTERVAL
518	str	r1, [r0, #EMC_ZCAL_INTERVAL]
519	ldr	r1, [r5, #0x0]		@ restore EMC_CFG
520	str	r1, [r0, #EMC_CFG]
521
522	emc_timing_update r1, r0
523
524	/* Tegra114 had dual EMC channel, now config the other one */
525	cmp	r10, #TEGRA114
526	bne	__no_dual_emc_chanl
527	mov32	r1, TEGRA_EMC1_BASE
528	cmp	r0, r1
529	movne	r0, r1
530	addne	r5, r5, #0x20
531	bne	exit_self_refresh
532__no_dual_emc_chanl:
533
534	mov32	r0, TEGRA_PMC_BASE
535	ldr	r0, [r0, #PMC_SCRATCH41]
536	ret	r0			@ jump to tegra_resume
537ENDPROC(tegra30_lp1_reset)
538
539	.align	L1_CACHE_SHIFT
540tegra30_sdram_pad_address:
541	.word	TEGRA_EMC_BASE + EMC_CFG				@0x0
542	.word	TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL			@0x4
543	.word	TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL			@0x8
544	.word	TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL			@0xc
545	.word	TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2			@0x10
546	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
547	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
548	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
549tegra30_sdram_pad_address_end:
550
551tegra114_sdram_pad_address:
552	.word	TEGRA_EMC0_BASE + EMC_CFG				@0x0
553	.word	TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL			@0x4
554	.word	TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL			@0x8
555	.word	TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL			@0xc
556	.word	TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2			@0x10
557	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
558	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
559	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
560	.word	TEGRA_EMC1_BASE + EMC_CFG				@0x20
561	.word	TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL			@0x24
562	.word	TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL			@0x28
563	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL			@0x2c
564	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30
565tegra114_sdram_pad_adress_end:
566
567tegra124_sdram_pad_address:
568	.word	TEGRA124_EMC_BASE + EMC_CFG				@0x0
569	.word	TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL			@0x4
570	.word	TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL		@0x8
571	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL		@0xc
572	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2		@0x10
573	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
574	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
575	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
576tegra124_sdram_pad_address_end:
577
578tegra30_sdram_pad_size:
579	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
580
581tegra114_sdram_pad_size:
582	.word	tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
583
584	.type	tegra_sdram_pad_save, %object
585tegra_sdram_pad_save:
586	.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
587	.long	0
588	.endr
589
590/*
591 * tegra30_tear_down_core
592 *
593 * copied into and executed from IRAM
594 * puts memory in self-refresh for LP0 and LP1
595 */
596tegra30_tear_down_core:
597	bl	tegra30_sdram_self_refresh
598	bl	tegra30_switch_cpu_to_clk32k
599	b	tegra30_enter_sleep
600
601/*
602 * tegra30_switch_cpu_to_clk32k
603 *
604 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
605 * to the 32KHz clock.
606 * r4 = TEGRA_PMC_BASE
607 * r5 = TEGRA_CLK_RESET_BASE
608 * r6 = TEGRA_FLOW_CTRL_BASE
609 * r7 = TEGRA_TMRUS_BASE
610 * r10= SoC ID
611 */
612tegra30_switch_cpu_to_clk32k:
613	/*
614	 * start by jumping to CLKM to safely disable PLLs, then jump to
615	 * CLKS.
616	 */
617	mov	r0, #(1 << 28)
618	str	r0, [r5, #CLK_RESET_SCLK_BURST]
619	/* 2uS delay delay between changing SCLK and CCLK */
620	ldr	r1, [r7]
621	add	r1, r1, #2
622	wait_until r1, r7, r9
623	str	r0, [r5, #CLK_RESET_CCLK_BURST]
624	mov	r0, #0
625	str	r0, [r5, #CLK_RESET_CCLK_DIVIDER]
626	str	r0, [r5, #CLK_RESET_SCLK_DIVIDER]
627
628	/* switch the clock source of mselect to be CLK_M */
629	ldr	r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
630	orr	r0, r0, #MSELECT_CLKM
631	str	r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
632
633	/* 2uS delay delay between changing SCLK and disabling PLLs */
634	ldr	r1, [r7]
635	add	r1, r1, #2
636	wait_until r1, r7, r9
637
638	/* disable PLLM via PMC in LP1 */
639	ldr	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
640	bic	r0, r0, #(1 << 12)
641	str	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
642
643	/* disable PLLP, PLLA, PLLC and PLLX */
644	ldr	r0, [r5, #CLK_RESET_PLLP_BASE]
645	bic	r0, r0, #(1 << 30)
646	str	r0, [r5, #CLK_RESET_PLLP_BASE]
647	ldr	r0, [r5, #CLK_RESET_PLLA_BASE]
648	bic	r0, r0, #(1 << 30)
649	str	r0, [r5, #CLK_RESET_PLLA_BASE]
650	ldr	r0, [r5, #CLK_RESET_PLLC_BASE]
651	bic	r0, r0, #(1 << 30)
652	str	r0, [r5, #CLK_RESET_PLLC_BASE]
653	ldr	r0, [r5, #CLK_RESET_PLLX_BASE]
654	bic	r0, r0, #(1 << 30)
655	str	r0, [r5, #CLK_RESET_PLLX_BASE]
656
657	cmp	r10, #TEGRA30
658	beq	_no_pll_in_iddq
659	pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
660_no_pll_in_iddq:
661
662	/* switch to CLKS */
663	mov	r0, #0	/* brust policy = 32KHz */
664	str	r0, [r5, #CLK_RESET_SCLK_BURST]
665
666	ret	lr
667
668/*
669 * tegra30_enter_sleep
670 *
671 * uses flow controller to enter sleep state
672 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
673 * executes from SDRAM with target state is LP2
674 * r6 = TEGRA_FLOW_CTRL_BASE
675 */
676tegra30_enter_sleep:
677	cpu_id	r1
678
679	cpu_to_csr_reg	r2, r1
680	ldr	r0, [r6, r2]
681	orr	r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
682	orr	r0, r0, #FLOW_CTRL_CSR_ENABLE
683	str	r0, [r6, r2]
684
685	tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
686	cmp	r10, #TEGRA30
687	mov	r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
688	orreq	r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
689	orrne   r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
690
691	cpu_to_halt_reg r2, r1
692	str	r0, [r6, r2]
693	dsb
694	ldr	r0, [r6, r2] /* memory barrier */
695
696halted:
697	isb
698	dsb
699	wfi	/* CPU should be power gated here */
700
701	/* !!!FIXME!!! Implement halt failure handler */
702	b	halted
703
704/*
705 * tegra30_sdram_self_refresh
706 *
707 * called with MMU off and caches disabled
708 * must be executed from IRAM
709 * r4 = TEGRA_PMC_BASE
710 * r5 = TEGRA_CLK_RESET_BASE
711 * r6 = TEGRA_FLOW_CTRL_BASE
712 * r7 = TEGRA_TMRUS_BASE
713 * r10= SoC ID
714 */
715tegra30_sdram_self_refresh:
716
717	adr	r8, tegra_sdram_pad_save
718	tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
719	cmp	r10, #TEGRA30
720	adreq	r2, tegra30_sdram_pad_address
721	ldreq	r3, tegra30_sdram_pad_size
722	cmp	r10, #TEGRA114
723	adreq	r2, tegra114_sdram_pad_address
724	ldreq	r3, tegra114_sdram_pad_size
725	cmp	r10, #TEGRA124
726	adreq	r2, tegra124_sdram_pad_address
727	ldreq	r3, tegra30_sdram_pad_size
728
729	mov	r9, #0
730
731padsave:
732	ldr	r0, [r2, r9]		@ r0 is the addr in the pad_address
733
734	ldr	r1, [r0]
735	str	r1, [r8, r9]		@ save the content of the addr
736
737	add	r9, r9, #4
738	cmp	r3, r9
739	bne	padsave
740padsave_done:
741
742	dsb
743
744	cmp	r10, #TEGRA30
745	ldreq	r0, =TEGRA_EMC_BASE	@ r0 reserved for emc base addr
746	cmp	r10, #TEGRA114
747	ldreq	r0, =TEGRA_EMC0_BASE
748	cmp	r10, #TEGRA124
749	ldreq	r0, =TEGRA124_EMC_BASE
750
751enter_self_refresh:
752	cmp	r10, #TEGRA30
753	mov	r1, #0
754	str	r1, [r0, #EMC_ZCAL_INTERVAL]
755	str	r1, [r0, #EMC_AUTO_CAL_INTERVAL]
756	ldr	r1, [r0, #EMC_CFG]
757	bic	r1, r1, #(1 << 28)
758	bicne	r1, r1, #(1 << 29)
759	str	r1, [r0, #EMC_CFG]	@ disable DYN_SELF_REF
760
761	emc_timing_update r1, r0
762
763	ldr	r1, [r7]
764	add	r1, r1, #5
765	wait_until r1, r7, r2
766
767emc_wait_auto_cal:
768	ldr	r1, [r0, #EMC_AUTO_CAL_STATUS]
769	tst	r1, #(1 << 31)		@ wait until AUTO_CAL_ACTIVE is cleared
770	bne	emc_wait_auto_cal
771
772	mov	r1, #3
773	str	r1, [r0, #EMC_REQ_CTRL]	@ stall incoming DRAM requests
774
775emcidle:
776	ldr	r1, [r0, #EMC_EMC_STATUS]
777	tst	r1, #4
778	beq	emcidle
779
780	mov	r1, #1
781	str	r1, [r0, #EMC_SELF_REF]
782
783	emc_device_mask r1, r0
784
785emcself:
786	ldr	r2, [r0, #EMC_EMC_STATUS]
787	and	r2, r2, r1
788	cmp	r2, r1
789	bne	emcself			@ loop until DDR in self-refresh
790
791	/* Put VTTGEN in the lowest power mode */
792	ldr	r1, [r0, #EMC_XM2VTTGENPADCTRL]
793	mov32	r2, 0xF8F8FFFF	@ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
794	and	r1, r1, r2
795	str	r1, [r0, #EMC_XM2VTTGENPADCTRL]
796	ldr	r1, [r0, #EMC_XM2VTTGENPADCTRL2]
797	cmp	r10, #TEGRA30
798	orreq	r1, r1, #7		@ set E_NO_VTTGEN
799	orrne	r1, r1, #0x3f
800	str	r1, [r0, #EMC_XM2VTTGENPADCTRL2]
801
802	emc_timing_update r1, r0
803
804	/* Tegra114 had dual EMC channel, now config the other one */
805	cmp	r10, #TEGRA114
806	bne	no_dual_emc_chanl
807	mov32	r1, TEGRA_EMC1_BASE
808	cmp	r0, r1
809	movne	r0, r1
810	bne	enter_self_refresh
811no_dual_emc_chanl:
812
813	ldr	r1, [r4, #PMC_CTRL]
814	tst	r1, #PMC_CTRL_SIDE_EFFECT_LP0
815	bne	pmc_io_dpd_skip
816	/*
817	 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
818	 * and COMP in the lowest power mode when LP1.
819	 */
820	mov32	r1, 0x8EC00000
821	str	r1, [r4, #PMC_IO_DPD_REQ]
822pmc_io_dpd_skip:
823
824	dsb
825
826	ret	lr
827
828	.ltorg
829/* dummy symbol for end of IRAM */
830	.align L1_CACHE_SHIFT
831	.global tegra30_iram_end
832tegra30_iram_end:
833	b	.
834#endif
835