1/*
2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/init.h>
18#include <linux/linkage.h>
19
20#include <soc/tegra/flowctrl.h>
21#include <soc/tegra/fuse.h>
22
23#include <asm/assembler.h>
24#include <asm/asm-offsets.h>
25#include <asm/cache.h>
26
27#include "iomap.h"
28#include "reset.h"
29#include "sleep.h"
30
31#define PMC_SCRATCH41	0x140
32
33#ifdef CONFIG_PM_SLEEP
34/*
35 *	tegra_resume
36 *
37 *	  CPU boot vector when restarting the a CPU following
38 *	  an LP2 transition. Also branched to by LP0 and LP1 resume after
39 *	  re-enabling sdram.
40 *
41 *	r6: SoC ID
42 *	r8: CPU part number
43 */
44ENTRY(tegra_resume)
45	check_cpu_part_num 0xc09, r8, r9
46	bleq	v7_invalidate_l1
47
48	cpu_id	r0
49	cmp	r0, #0				@ CPU0?
50 THUMB(	it	ne )
51	bne	cpu_resume			@ no
52
53	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
54	/* Are we on Tegra20? */
55	cmp	r6, #TEGRA20
56	beq	1f				@ Yes
57	/* Clear the flow controller flags for this CPU. */
58	cpu_to_csr_reg r1, r0
59	mov32	r2, TEGRA_FLOW_CTRL_BASE
60	ldr	r1, [r2, r1]
61	/* Clear event & intr flag */
62	orr	r1, r1, \
63		#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
64	movw	r0, #0x3FFD	@ enable, cluster_switch, immed, bitmaps
65				@ & ext flags for CPU power mgnt
66	bic	r1, r1, r0
67	str	r1, [r2]
681:
69
70	mov32	r9, 0xc09
71	cmp	r8, r9
72	bne	end_ca9_scu_l2_resume
73#ifdef CONFIG_HAVE_ARM_SCU
74	/* enable SCU */
75	mov32	r0, TEGRA_ARM_PERIF_BASE
76	ldr	r1, [r0]
77	orr	r1, r1, #1
78	str	r1, [r0]
79#endif
80	bl	tegra_resume_trusted_foundations
81
82#ifdef CONFIG_CACHE_L2X0
83	/* L2 cache resume & re-enable */
84	bl	l2c310_early_resume
85#endif
86end_ca9_scu_l2_resume:
87	mov32	r9, 0xc0f
88	cmp	r8, r9
89	bleq	tegra_init_l2_for_a15
90
91	b	cpu_resume
92ENDPROC(tegra_resume)
93
94/*
95 *	tegra_resume_trusted_foundations
96 *
97 *	  Trusted Foundations firmware initialization.
98 *
99 *	Doesn't return if firmware presents.
100 *	Corrupted registers: r1, r2
101 */
102ENTRY(tegra_resume_trusted_foundations)
103	/* Check whether Trusted Foundations firmware presents. */
104	mov32	r2, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
105	ldr	r1, =__tegra_cpu_reset_handler_data_offset + \
106							RESET_DATA(TF_PRESENT)
107	ldr	r1, [r2, r1]
108	cmp	r1, #0
109	reteq	lr
110
111 .arch_extension sec
112	/* First call after suspend wakes firmware. No arguments required. */
113	smc	#0
114
115	b	cpu_resume
116ENDPROC(tegra_resume_trusted_foundations)
117#endif
118
119	.align L1_CACHE_SHIFT
120ENTRY(__tegra_cpu_reset_handler_start)
121
122/*
123 * __tegra_cpu_reset_handler:
124 *
125 * Common handler for all CPU reset events.
126 *
127 * Register usage within the reset handler:
128 *
129 *      Others: scratch
130 *      R6  = SoC ID
131 *      R7  = CPU present (to the OS) mask
132 *      R8  = CPU in LP1 state mask
133 *      R9  = CPU in LP2 state mask
134 *      R10 = CPU number
135 *      R11 = CPU mask
136 *      R12 = pointer to reset handler data
137 *
138 * NOTE: This code is copied to IRAM. All code and data accesses
139 *       must be position-independent.
140 */
141
142	.arm
143	.align L1_CACHE_SHIFT
144ENTRY(__tegra_cpu_reset_handler)
145
146	cpsid	aif, 0x13			@ SVC mode, interrupts disabled
147
148	tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
149
150	adr	r12, __tegra_cpu_reset_handler_data
151	ldr	r5, [r12, #RESET_DATA(TF_PRESENT)]
152	cmp	r5, #0
153	bne	after_errata
154
155#ifdef CONFIG_ARCH_TEGRA_2x_SOC
156t20_check:
157	cmp	r6, #TEGRA20
158	bne	after_t20_check
159t20_errata:
160	# Tegra20 is a Cortex-A9 r1p1
161	mrc	p15, 0, r0, c1, c0, 0   @ read system control register
162	orr	r0, r0, #1 << 14        @ erratum 716044
163	mcr	p15, 0, r0, c1, c0, 0   @ write system control register
164	mrc	p15, 0, r0, c15, c0, 1  @ read diagnostic register
165	orr	r0, r0, #1 << 4         @ erratum 742230
166	orr	r0, r0, #1 << 11        @ erratum 751472
167	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
168	b	after_errata
169after_t20_check:
170#endif
171#ifdef CONFIG_ARCH_TEGRA_3x_SOC
172t30_check:
173	cmp	r6, #TEGRA30
174	bne	after_t30_check
175t30_errata:
176	# Tegra30 is a Cortex-A9 r2p9
177	mrc	p15, 0, r0, c15, c0, 1  @ read diagnostic register
178	orr	r0, r0, #1 << 6         @ erratum 743622
179	orr	r0, r0, #1 << 11        @ erratum 751472
180	mcr	p15, 0, r0, c15, c0, 1  @ write diagnostic register
181	b	after_errata
182after_t30_check:
183#endif
184after_errata:
185	mrc	p15, 0, r10, c0, c0, 5		@ MPIDR
186	and	r10, r10, #0x3			@ R10 = CPU number
187	mov	r11, #1
188	mov	r11, r11, lsl r10  		@ R11 = CPU mask
189
190#ifdef CONFIG_SMP
191	/* Does the OS know about this CPU? */
192	ldr	r7, [r12, #RESET_DATA(MASK_PRESENT)]
193	tst	r7, r11 			@ if !present
194	bleq	__die				@ CPU not present (to OS)
195#endif
196
197#ifdef CONFIG_ARCH_TEGRA_2x_SOC
198	/* Are we on Tegra20? */
199	cmp	r6, #TEGRA20
200	bne	1f
201	/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
202	mov	r0, #CPU_NOT_RESETTABLE
203	cmp	r10, #0
204	strbne	r0, [r12, #RESET_DATA(RESETTABLE_STATUS)]
2051:
206#endif
207
208	/* Waking up from LP1? */
209	ldr	r8, [r12, #RESET_DATA(MASK_LP1)]
210	tst	r8, r11				@ if in_lp1
211	beq	__is_not_lp1
212	cmp	r10, #0
213	bne	__die				@ only CPU0 can be here
214	ldr	lr, [r12, #RESET_DATA(STARTUP_LP1)]
215	cmp	lr, #0
216	bleq	__die				@ no LP1 startup handler
217 THUMB(	add	lr, lr, #1 )			@ switch to Thumb mode
218	bx	lr
219__is_not_lp1:
220
221	/* Waking up from LP2? */
222	ldr	r9, [r12, #RESET_DATA(MASK_LP2)]
223	tst	r9, r11				@ if in_lp2
224	beq	__is_not_lp2
225	ldr	lr, [r12, #RESET_DATA(STARTUP_LP2)]
226	cmp	lr, #0
227	bleq	__die				@ no LP2 startup handler
228	bx	lr
229
230__is_not_lp2:
231
232#ifdef CONFIG_SMP
233	/*
234	 * Can only be secondary boot (initial or hotplug)
235	 * CPU0 can't be here for Tegra20/30
236	 */
237	cmp	r6, #TEGRA114
238	beq	__no_cpu0_chk
239	cmp	r10, #0
240	bleq	__die				@ CPU0 cannot be here
241__no_cpu0_chk:
242	ldr	lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
243	cmp	lr, #0
244	bleq	__die				@ no secondary startup handler
245	bx	lr
246#endif
247
248/*
249 * We don't know why the CPU reset. Just kill it.
250 * The LR register will contain the address we died at + 4.
251 */
252
253__die:
254	sub	lr, lr, #4
255	mov32	r7, TEGRA_PMC_BASE
256	str	lr, [r7, #PMC_SCRATCH41]
257
258	mov32	r7, TEGRA_CLK_RESET_BASE
259
260	/* Are we on Tegra20? */
261	cmp	r6, #TEGRA20
262	bne	1f
263
264#ifdef CONFIG_ARCH_TEGRA_2x_SOC
265	mov32	r0, 0x1111
266	mov	r1, r0, lsl r10
267	str	r1, [r7, #0x340]		@ CLK_RST_CPU_CMPLX_SET
268#endif
2691:
270#ifdef CONFIG_ARCH_TEGRA_3x_SOC
271	mov32	r6, TEGRA_FLOW_CTRL_BASE
272
273	cmp	r10, #0
274	moveq	r1, #FLOW_CTRL_HALT_CPU0_EVENTS
275	moveq	r2, #FLOW_CTRL_CPU0_CSR
276	movne	r1, r10, lsl #3
277	addne	r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
278	addne	r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
279
280	/* Clear CPU "event" and "interrupt" flags and power gate
281	   it when halting but not before it is in the "WFI" state. */
282	ldr	r0, [r6, +r2]
283	orr	r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
284	orr	r0, r0, #FLOW_CTRL_CSR_ENABLE
285	str	r0, [r6, +r2]
286
287	/* Unconditionally halt this CPU */
288	mov	r0, #FLOW_CTRL_WAITEVENT
289	str	r0, [r6, +r1]
290	ldr	r0, [r6, +r1]			@ memory barrier
291
292	dsb
293	isb
294	wfi					@ CPU should be power gated here
295
296	/* If the CPU didn't power gate above just kill it's clock. */
297
298	mov	r0, r11, lsl #8
299	str	r0, [r7, #348]			@ CLK_CPU_CMPLX_SET
300#endif
301
302	/* If the CPU still isn't dead, just spin here. */
303	b	.
304ENDPROC(__tegra_cpu_reset_handler)
305
306	.align L1_CACHE_SHIFT
307	.type	__tegra_cpu_reset_handler_data, %object
308	.globl	__tegra_cpu_reset_handler_data
309	.globl	__tegra_cpu_reset_handler_data_offset
310	.equ	__tegra_cpu_reset_handler_data_offset, \
311					. - __tegra_cpu_reset_handler_start
312__tegra_cpu_reset_handler_data:
313	.rept   TEGRA_RESET_DATA_SIZE
314	.long   0
315	.endr
316	.align L1_CACHE_SHIFT
317
318ENTRY(__tegra_cpu_reset_handler_end)
319