1 /* 2 * CPU complex suspend & resume functions for Tegra SoCs 3 * 4 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 #include <linux/cpumask.h> 23 #include <linux/delay.h> 24 #include <linux/cpu_pm.h> 25 #include <linux/suspend.h> 26 #include <linux/err.h> 27 #include <linux/clk/tegra.h> 28 29 #include <asm/smp_plat.h> 30 #include <asm/cacheflush.h> 31 #include <asm/suspend.h> 32 #include <asm/idmap.h> 33 #include <asm/proc-fns.h> 34 #include <asm/tlbflush.h> 35 36 #include "iomap.h" 37 #include "reset.h" 38 #include "flowctrl.h" 39 #include "fuse.h" 40 #include "pmc.h" 41 #include "sleep.h" 42 43 #ifdef CONFIG_PM_SLEEP 44 static DEFINE_SPINLOCK(tegra_lp2_lock); 45 void (*tegra_tear_down_cpu)(void); 46 47 /* 48 * restore_cpu_complex 49 * 50 * restores cpu clock setting, clears flow controller 51 * 52 * Always called on CPU 0. 53 */ 54 static void restore_cpu_complex(void) 55 { 56 int cpu = smp_processor_id(); 57 58 BUG_ON(cpu != 0); 59 60 #ifdef CONFIG_SMP 61 cpu = cpu_logical_map(cpu); 62 #endif 63 64 /* Restore the CPU clock settings */ 65 tegra_cpu_clock_resume(); 66 67 flowctrl_cpu_suspend_exit(cpu); 68 } 69 70 /* 71 * suspend_cpu_complex 72 * 73 * saves pll state for use by restart_plls, prepares flow controller for 74 * transition to suspend state 75 * 76 * Must always be called on cpu 0. 77 */ 78 static void suspend_cpu_complex(void) 79 { 80 int cpu = smp_processor_id(); 81 82 BUG_ON(cpu != 0); 83 84 #ifdef CONFIG_SMP 85 cpu = cpu_logical_map(cpu); 86 #endif 87 88 /* Save the CPU clock settings */ 89 tegra_cpu_clock_suspend(); 90 91 flowctrl_cpu_suspend_enter(cpu); 92 } 93 94 void tegra_clear_cpu_in_lp2(int phy_cpu_id) 95 { 96 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 97 98 spin_lock(&tegra_lp2_lock); 99 100 BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id))); 101 *cpu_in_lp2 &= ~BIT(phy_cpu_id); 102 103 spin_unlock(&tegra_lp2_lock); 104 } 105 106 bool tegra_set_cpu_in_lp2(int phy_cpu_id) 107 { 108 bool last_cpu = false; 109 cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; 110 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 111 112 spin_lock(&tegra_lp2_lock); 113 114 BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); 115 *cpu_in_lp2 |= BIT(phy_cpu_id); 116 117 if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) 118 last_cpu = true; 119 else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1) 120 tegra20_cpu_set_resettable_soon(); 121 122 spin_unlock(&tegra_lp2_lock); 123 return last_cpu; 124 } 125 126 int tegra_cpu_do_idle(void) 127 { 128 return cpu_do_idle(); 129 } 130 131 static int tegra_sleep_cpu(unsigned long v2p) 132 { 133 setup_mm_for_reboot(); 134 tegra_sleep_cpu_finish(v2p); 135 136 /* should never here */ 137 BUG(); 138 139 return 0; 140 } 141 142 void tegra_idle_lp2_last(void) 143 { 144 tegra_pmc_pm_set(TEGRA_SUSPEND_LP2); 145 146 cpu_cluster_pm_enter(); 147 suspend_cpu_complex(); 148 149 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); 150 151 restore_cpu_complex(); 152 cpu_cluster_pm_exit(); 153 } 154 155 enum tegra_suspend_mode tegra_pm_validate_suspend_mode( 156 enum tegra_suspend_mode mode) 157 { 158 /* Tegra114 didn't support any suspending mode yet. */ 159 if (tegra_chip_id == TEGRA114) 160 return TEGRA_SUSPEND_NONE; 161 162 /* 163 * The Tegra devices only support suspending to LP2 currently. 164 */ 165 if (mode > TEGRA_SUSPEND_LP2) 166 return TEGRA_SUSPEND_LP2; 167 168 return mode; 169 } 170 171 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { 172 [TEGRA_SUSPEND_NONE] = "none", 173 [TEGRA_SUSPEND_LP2] = "LP2", 174 [TEGRA_SUSPEND_LP1] = "LP1", 175 [TEGRA_SUSPEND_LP0] = "LP0", 176 }; 177 178 static int __cpuinit tegra_suspend_enter(suspend_state_t state) 179 { 180 enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); 181 182 if (WARN_ON(mode < TEGRA_SUSPEND_NONE || 183 mode >= TEGRA_MAX_SUSPEND_MODE)) 184 return -EINVAL; 185 186 pr_info("Entering suspend state %s\n", lp_state[mode]); 187 188 tegra_pmc_pm_set(mode); 189 190 local_fiq_disable(); 191 192 suspend_cpu_complex(); 193 switch (mode) { 194 case TEGRA_SUSPEND_LP2: 195 tegra_set_cpu_in_lp2(0); 196 break; 197 default: 198 break; 199 } 200 201 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); 202 203 switch (mode) { 204 case TEGRA_SUSPEND_LP2: 205 tegra_clear_cpu_in_lp2(0); 206 break; 207 default: 208 break; 209 } 210 restore_cpu_complex(); 211 212 local_fiq_enable(); 213 214 return 0; 215 } 216 217 static const struct platform_suspend_ops tegra_suspend_ops = { 218 .valid = suspend_valid_only_mem, 219 .enter = tegra_suspend_enter, 220 }; 221 222 void __init tegra_init_suspend(void) 223 { 224 if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE) 225 return; 226 227 tegra_pmc_suspend_init(); 228 229 suspend_set_ops(&tegra_suspend_ops); 230 } 231 #endif 232