1 /* 2 * CPU complex suspend & resume functions for Tegra SoCs 3 * 4 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 #include <linux/cpumask.h> 23 #include <linux/delay.h> 24 #include <linux/cpu_pm.h> 25 #include <linux/clk.h> 26 #include <linux/err.h> 27 #include <linux/clk/tegra.h> 28 29 #include <asm/smp_plat.h> 30 #include <asm/cacheflush.h> 31 #include <asm/suspend.h> 32 #include <asm/idmap.h> 33 #include <asm/proc-fns.h> 34 #include <asm/tlbflush.h> 35 36 #include "iomap.h" 37 #include "reset.h" 38 #include "flowctrl.h" 39 #include "fuse.h" 40 #include "sleep.h" 41 42 #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ 43 44 #define PMC_CTRL 0x0 45 #define PMC_CPUPWRGOOD_TIMER 0xc8 46 #define PMC_CPUPWROFF_TIMER 0xcc 47 48 #ifdef CONFIG_PM_SLEEP 49 static unsigned int g_diag_reg; 50 static DEFINE_SPINLOCK(tegra_lp2_lock); 51 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); 52 static struct clk *tegra_pclk; 53 void (*tegra_tear_down_cpu)(void); 54 55 void save_cpu_arch_register(void) 56 { 57 /* read diagnostic register */ 58 asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc"); 59 return; 60 } 61 62 void restore_cpu_arch_register(void) 63 { 64 /* write diagnostic register */ 65 asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc"); 66 return; 67 } 68 69 static void set_power_timers(unsigned long us_on, unsigned long us_off) 70 { 71 unsigned long long ticks; 72 unsigned long long pclk; 73 unsigned long rate; 74 static unsigned long tegra_last_pclk; 75 76 if (tegra_pclk == NULL) { 77 tegra_pclk = clk_get_sys(NULL, "pclk"); 78 WARN_ON(IS_ERR(tegra_pclk)); 79 } 80 81 rate = clk_get_rate(tegra_pclk); 82 83 if (WARN_ON_ONCE(rate <= 0)) 84 pclk = 100000000; 85 else 86 pclk = rate; 87 88 if ((rate != tegra_last_pclk)) { 89 ticks = (us_on * pclk) + 999999ull; 90 do_div(ticks, 1000000); 91 writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER); 92 93 ticks = (us_off * pclk) + 999999ull; 94 do_div(ticks, 1000000); 95 writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER); 96 wmb(); 97 } 98 tegra_last_pclk = pclk; 99 } 100 101 /* 102 * restore_cpu_complex 103 * 104 * restores cpu clock setting, clears flow controller 105 * 106 * Always called on CPU 0. 107 */ 108 static void restore_cpu_complex(void) 109 { 110 int cpu = smp_processor_id(); 111 112 BUG_ON(cpu != 0); 113 114 #ifdef CONFIG_SMP 115 cpu = cpu_logical_map(cpu); 116 #endif 117 118 /* Restore the CPU clock settings */ 119 tegra_cpu_clock_resume(); 120 121 flowctrl_cpu_suspend_exit(cpu); 122 123 restore_cpu_arch_register(); 124 } 125 126 /* 127 * suspend_cpu_complex 128 * 129 * saves pll state for use by restart_plls, prepares flow controller for 130 * transition to suspend state 131 * 132 * Must always be called on cpu 0. 133 */ 134 static void suspend_cpu_complex(void) 135 { 136 int cpu = smp_processor_id(); 137 138 BUG_ON(cpu != 0); 139 140 #ifdef CONFIG_SMP 141 cpu = cpu_logical_map(cpu); 142 #endif 143 144 /* Save the CPU clock settings */ 145 tegra_cpu_clock_suspend(); 146 147 flowctrl_cpu_suspend_enter(cpu); 148 149 save_cpu_arch_register(); 150 } 151 152 void tegra_clear_cpu_in_lp2(int phy_cpu_id) 153 { 154 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 155 156 spin_lock(&tegra_lp2_lock); 157 158 BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id))); 159 *cpu_in_lp2 &= ~BIT(phy_cpu_id); 160 161 spin_unlock(&tegra_lp2_lock); 162 } 163 164 bool tegra_set_cpu_in_lp2(int phy_cpu_id) 165 { 166 bool last_cpu = false; 167 cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; 168 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 169 170 spin_lock(&tegra_lp2_lock); 171 172 BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); 173 *cpu_in_lp2 |= BIT(phy_cpu_id); 174 175 if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) 176 last_cpu = true; 177 else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1) 178 tegra20_cpu_set_resettable_soon(); 179 180 spin_unlock(&tegra_lp2_lock); 181 return last_cpu; 182 } 183 184 static int tegra_sleep_cpu(unsigned long v2p) 185 { 186 /* Switch to the identity mapping. */ 187 cpu_switch_mm(idmap_pgd, &init_mm); 188 189 /* Flush the TLB. */ 190 local_flush_tlb_all(); 191 192 tegra_sleep_cpu_finish(v2p); 193 194 /* should never here */ 195 BUG(); 196 197 return 0; 198 } 199 200 void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time) 201 { 202 u32 mode; 203 204 /* Only the last cpu down does the final suspend steps */ 205 mode = readl(pmc + PMC_CTRL); 206 mode |= TEGRA_POWER_CPU_PWRREQ_OE; 207 writel(mode, pmc + PMC_CTRL); 208 209 set_power_timers(cpu_on_time, cpu_off_time); 210 211 cpu_cluster_pm_enter(); 212 suspend_cpu_complex(); 213 214 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); 215 216 restore_cpu_complex(); 217 cpu_cluster_pm_exit(); 218 } 219 #endif 220