1 /* 2 * CPU complex suspend & resume functions for Tegra SoCs 3 * 4 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 #include <linux/cpumask.h> 23 #include <linux/delay.h> 24 #include <linux/cpu_pm.h> 25 #include <linux/suspend.h> 26 #include <linux/err.h> 27 #include <linux/clk/tegra.h> 28 29 #include <asm/smp_plat.h> 30 #include <asm/cacheflush.h> 31 #include <asm/suspend.h> 32 #include <asm/idmap.h> 33 #include <asm/proc-fns.h> 34 #include <asm/tlbflush.h> 35 36 #include "iomap.h" 37 #include "reset.h" 38 #include "flowctrl.h" 39 #include "fuse.h" 40 #include "pmc.h" 41 #include "sleep.h" 42 43 #ifdef CONFIG_PM_SLEEP 44 static DEFINE_SPINLOCK(tegra_lp2_lock); 45 void (*tegra_tear_down_cpu)(void); 46 47 static void tegra_tear_down_cpu_init(void) 48 { 49 switch (tegra_chip_id) { 50 case TEGRA20: 51 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 52 tegra_tear_down_cpu = tegra20_tear_down_cpu; 53 break; 54 case TEGRA30: 55 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) 56 tegra_tear_down_cpu = tegra30_tear_down_cpu; 57 break; 58 } 59 } 60 61 /* 62 * restore_cpu_complex 63 * 64 * restores cpu clock setting, clears flow controller 65 * 66 * Always called on CPU 0. 67 */ 68 static void restore_cpu_complex(void) 69 { 70 int cpu = smp_processor_id(); 71 72 BUG_ON(cpu != 0); 73 74 #ifdef CONFIG_SMP 75 cpu = cpu_logical_map(cpu); 76 #endif 77 78 /* Restore the CPU clock settings */ 79 tegra_cpu_clock_resume(); 80 81 flowctrl_cpu_suspend_exit(cpu); 82 } 83 84 /* 85 * suspend_cpu_complex 86 * 87 * saves pll state for use by restart_plls, prepares flow controller for 88 * transition to suspend state 89 * 90 * Must always be called on cpu 0. 91 */ 92 static void suspend_cpu_complex(void) 93 { 94 int cpu = smp_processor_id(); 95 96 BUG_ON(cpu != 0); 97 98 #ifdef CONFIG_SMP 99 cpu = cpu_logical_map(cpu); 100 #endif 101 102 /* Save the CPU clock settings */ 103 tegra_cpu_clock_suspend(); 104 105 flowctrl_cpu_suspend_enter(cpu); 106 } 107 108 void tegra_clear_cpu_in_lp2(void) 109 { 110 int phy_cpu_id = cpu_logical_map(smp_processor_id()); 111 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 112 113 spin_lock(&tegra_lp2_lock); 114 115 BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id))); 116 *cpu_in_lp2 &= ~BIT(phy_cpu_id); 117 118 spin_unlock(&tegra_lp2_lock); 119 } 120 121 bool tegra_set_cpu_in_lp2(void) 122 { 123 int phy_cpu_id = cpu_logical_map(smp_processor_id()); 124 bool last_cpu = false; 125 cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; 126 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 127 128 spin_lock(&tegra_lp2_lock); 129 130 BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); 131 *cpu_in_lp2 |= BIT(phy_cpu_id); 132 133 if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) 134 last_cpu = true; 135 else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1) 136 tegra20_cpu_set_resettable_soon(); 137 138 spin_unlock(&tegra_lp2_lock); 139 return last_cpu; 140 } 141 142 int tegra_cpu_do_idle(void) 143 { 144 return cpu_do_idle(); 145 } 146 147 static int tegra_sleep_cpu(unsigned long v2p) 148 { 149 setup_mm_for_reboot(); 150 tegra_sleep_cpu_finish(v2p); 151 152 /* should never here */ 153 BUG(); 154 155 return 0; 156 } 157 158 void tegra_idle_lp2_last(void) 159 { 160 tegra_pmc_pm_set(TEGRA_SUSPEND_LP2); 161 162 cpu_cluster_pm_enter(); 163 suspend_cpu_complex(); 164 165 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); 166 167 restore_cpu_complex(); 168 cpu_cluster_pm_exit(); 169 } 170 171 enum tegra_suspend_mode tegra_pm_validate_suspend_mode( 172 enum tegra_suspend_mode mode) 173 { 174 /* Tegra114 didn't support any suspending mode yet. */ 175 if (tegra_chip_id == TEGRA114) 176 return TEGRA_SUSPEND_NONE; 177 178 /* 179 * The Tegra devices only support suspending to LP2 currently. 180 */ 181 if (mode > TEGRA_SUSPEND_LP2) 182 return TEGRA_SUSPEND_LP2; 183 184 return mode; 185 } 186 187 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { 188 [TEGRA_SUSPEND_NONE] = "none", 189 [TEGRA_SUSPEND_LP2] = "LP2", 190 [TEGRA_SUSPEND_LP1] = "LP1", 191 [TEGRA_SUSPEND_LP0] = "LP0", 192 }; 193 194 static int tegra_suspend_enter(suspend_state_t state) 195 { 196 enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); 197 198 if (WARN_ON(mode < TEGRA_SUSPEND_NONE || 199 mode >= TEGRA_MAX_SUSPEND_MODE)) 200 return -EINVAL; 201 202 pr_info("Entering suspend state %s\n", lp_state[mode]); 203 204 tegra_pmc_pm_set(mode); 205 206 local_fiq_disable(); 207 208 suspend_cpu_complex(); 209 switch (mode) { 210 case TEGRA_SUSPEND_LP2: 211 tegra_set_cpu_in_lp2(); 212 break; 213 default: 214 break; 215 } 216 217 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); 218 219 switch (mode) { 220 case TEGRA_SUSPEND_LP2: 221 tegra_clear_cpu_in_lp2(); 222 break; 223 default: 224 break; 225 } 226 restore_cpu_complex(); 227 228 local_fiq_enable(); 229 230 return 0; 231 } 232 233 static const struct platform_suspend_ops tegra_suspend_ops = { 234 .valid = suspend_valid_only_mem, 235 .enter = tegra_suspend_enter, 236 }; 237 238 void __init tegra_init_suspend(void) 239 { 240 if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE) 241 return; 242 243 tegra_tear_down_cpu_init(); 244 tegra_pmc_suspend_init(); 245 246 suspend_set_ops(&tegra_suspend_ops); 247 } 248 #endif 249