1 /* 2 * CPU complex suspend & resume functions for Tegra SoCs 3 * 4 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/spinlock.h> 21 #include <linux/io.h> 22 #include <linux/cpumask.h> 23 #include <linux/delay.h> 24 #include <linux/cpu_pm.h> 25 #include <linux/suspend.h> 26 #include <linux/err.h> 27 #include <linux/clk/tegra.h> 28 29 #include <asm/smp_plat.h> 30 #include <asm/cacheflush.h> 31 #include <asm/suspend.h> 32 #include <asm/idmap.h> 33 #include <asm/proc-fns.h> 34 #include <asm/tlbflush.h> 35 36 #include "iomap.h" 37 #include "reset.h" 38 #include "flowctrl.h" 39 #include "fuse.h" 40 #include "pm.h" 41 #include "pmc.h" 42 #include "sleep.h" 43 44 #ifdef CONFIG_PM_SLEEP 45 static DEFINE_SPINLOCK(tegra_lp2_lock); 46 static u32 iram_save_size; 47 static void *iram_save_addr; 48 struct tegra_lp1_iram tegra_lp1_iram; 49 void (*tegra_tear_down_cpu)(void); 50 void (*tegra_sleep_core_finish)(unsigned long v2p); 51 static int (*tegra_sleep_func)(unsigned long v2p); 52 53 static void tegra_tear_down_cpu_init(void) 54 { 55 switch (tegra_chip_id) { 56 case TEGRA20: 57 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 58 tegra_tear_down_cpu = tegra20_tear_down_cpu; 59 break; 60 case TEGRA30: 61 case TEGRA114: 62 case TEGRA124: 63 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 64 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || 65 IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) 66 tegra_tear_down_cpu = tegra30_tear_down_cpu; 67 break; 68 } 69 } 70 71 /* 72 * restore_cpu_complex 73 * 74 * restores cpu clock setting, clears flow controller 75 * 76 * Always called on CPU 0. 77 */ 78 static void restore_cpu_complex(void) 79 { 80 int cpu = smp_processor_id(); 81 82 BUG_ON(cpu != 0); 83 84 #ifdef CONFIG_SMP 85 cpu = cpu_logical_map(cpu); 86 #endif 87 88 /* Restore the CPU clock settings */ 89 tegra_cpu_clock_resume(); 90 91 flowctrl_cpu_suspend_exit(cpu); 92 } 93 94 /* 95 * suspend_cpu_complex 96 * 97 * saves pll state for use by restart_plls, prepares flow controller for 98 * transition to suspend state 99 * 100 * Must always be called on cpu 0. 101 */ 102 static void suspend_cpu_complex(void) 103 { 104 int cpu = smp_processor_id(); 105 106 BUG_ON(cpu != 0); 107 108 #ifdef CONFIG_SMP 109 cpu = cpu_logical_map(cpu); 110 #endif 111 112 /* Save the CPU clock settings */ 113 tegra_cpu_clock_suspend(); 114 115 flowctrl_cpu_suspend_enter(cpu); 116 } 117 118 void tegra_clear_cpu_in_lp2(void) 119 { 120 int phy_cpu_id = cpu_logical_map(smp_processor_id()); 121 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 122 123 spin_lock(&tegra_lp2_lock); 124 125 BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id))); 126 *cpu_in_lp2 &= ~BIT(phy_cpu_id); 127 128 spin_unlock(&tegra_lp2_lock); 129 } 130 131 bool tegra_set_cpu_in_lp2(void) 132 { 133 int phy_cpu_id = cpu_logical_map(smp_processor_id()); 134 bool last_cpu = false; 135 cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; 136 u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; 137 138 spin_lock(&tegra_lp2_lock); 139 140 BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); 141 *cpu_in_lp2 |= BIT(phy_cpu_id); 142 143 if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) 144 last_cpu = true; 145 else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1) 146 tegra20_cpu_set_resettable_soon(); 147 148 spin_unlock(&tegra_lp2_lock); 149 return last_cpu; 150 } 151 152 int tegra_cpu_do_idle(void) 153 { 154 return cpu_do_idle(); 155 } 156 157 static int tegra_sleep_cpu(unsigned long v2p) 158 { 159 setup_mm_for_reboot(); 160 tegra_sleep_cpu_finish(v2p); 161 162 /* should never here */ 163 BUG(); 164 165 return 0; 166 } 167 168 void tegra_idle_lp2_last(void) 169 { 170 tegra_pmc_pm_set(TEGRA_SUSPEND_LP2); 171 172 cpu_cluster_pm_enter(); 173 suspend_cpu_complex(); 174 175 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); 176 177 restore_cpu_complex(); 178 cpu_cluster_pm_exit(); 179 } 180 181 enum tegra_suspend_mode tegra_pm_validate_suspend_mode( 182 enum tegra_suspend_mode mode) 183 { 184 /* 185 * The Tegra devices support suspending to LP1 or lower currently. 186 */ 187 if (mode > TEGRA_SUSPEND_LP1) 188 return TEGRA_SUSPEND_LP1; 189 190 return mode; 191 } 192 193 static int tegra_sleep_core(unsigned long v2p) 194 { 195 setup_mm_for_reboot(); 196 tegra_sleep_core_finish(v2p); 197 198 /* should never here */ 199 BUG(); 200 201 return 0; 202 } 203 204 /* 205 * tegra_lp1_iram_hook 206 * 207 * Hooking the address of LP1 reset vector and SDRAM self-refresh code in 208 * SDRAM. These codes not be copied to IRAM in this fuction. We need to 209 * copy these code to IRAM before LP0/LP1 suspend and restore the content 210 * of IRAM after resume. 211 */ 212 static bool tegra_lp1_iram_hook(void) 213 { 214 switch (tegra_chip_id) { 215 case TEGRA20: 216 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 217 tegra20_lp1_iram_hook(); 218 break; 219 case TEGRA30: 220 case TEGRA114: 221 case TEGRA124: 222 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 223 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || 224 IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) 225 tegra30_lp1_iram_hook(); 226 break; 227 default: 228 break; 229 } 230 231 if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr) 232 return false; 233 234 iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr; 235 iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL); 236 if (!iram_save_addr) 237 return false; 238 239 return true; 240 } 241 242 static bool tegra_sleep_core_init(void) 243 { 244 switch (tegra_chip_id) { 245 case TEGRA20: 246 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 247 tegra20_sleep_core_init(); 248 break; 249 case TEGRA30: 250 case TEGRA114: 251 case TEGRA124: 252 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 253 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || 254 IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) 255 tegra30_sleep_core_init(); 256 break; 257 default: 258 break; 259 } 260 261 if (!tegra_sleep_core_finish) 262 return false; 263 264 return true; 265 } 266 267 static void tegra_suspend_enter_lp1(void) 268 { 269 tegra_pmc_suspend(); 270 271 /* copy the reset vector & SDRAM shutdown code into IRAM */ 272 memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), 273 iram_save_size); 274 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), 275 tegra_lp1_iram.start_addr, iram_save_size); 276 277 *((u32 *)tegra_cpu_lp1_mask) = 1; 278 } 279 280 static void tegra_suspend_exit_lp1(void) 281 { 282 tegra_pmc_resume(); 283 284 /* restore IRAM */ 285 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr, 286 iram_save_size); 287 288 *(u32 *)tegra_cpu_lp1_mask = 0; 289 } 290 291 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { 292 [TEGRA_SUSPEND_NONE] = "none", 293 [TEGRA_SUSPEND_LP2] = "LP2", 294 [TEGRA_SUSPEND_LP1] = "LP1", 295 [TEGRA_SUSPEND_LP0] = "LP0", 296 }; 297 298 static int tegra_suspend_enter(suspend_state_t state) 299 { 300 enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); 301 302 if (WARN_ON(mode < TEGRA_SUSPEND_NONE || 303 mode >= TEGRA_MAX_SUSPEND_MODE)) 304 return -EINVAL; 305 306 pr_info("Entering suspend state %s\n", lp_state[mode]); 307 308 tegra_pmc_pm_set(mode); 309 310 local_fiq_disable(); 311 312 suspend_cpu_complex(); 313 switch (mode) { 314 case TEGRA_SUSPEND_LP1: 315 tegra_suspend_enter_lp1(); 316 break; 317 case TEGRA_SUSPEND_LP2: 318 tegra_set_cpu_in_lp2(); 319 break; 320 default: 321 break; 322 } 323 324 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func); 325 326 switch (mode) { 327 case TEGRA_SUSPEND_LP1: 328 tegra_suspend_exit_lp1(); 329 break; 330 case TEGRA_SUSPEND_LP2: 331 tegra_clear_cpu_in_lp2(); 332 break; 333 default: 334 break; 335 } 336 restore_cpu_complex(); 337 338 local_fiq_enable(); 339 340 return 0; 341 } 342 343 static const struct platform_suspend_ops tegra_suspend_ops = { 344 .valid = suspend_valid_only_mem, 345 .enter = tegra_suspend_enter, 346 }; 347 348 void __init tegra_init_suspend(void) 349 { 350 enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); 351 352 if (mode == TEGRA_SUSPEND_NONE) 353 return; 354 355 tegra_tear_down_cpu_init(); 356 tegra_pmc_suspend_init(); 357 358 if (mode >= TEGRA_SUSPEND_LP1) { 359 if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) { 360 pr_err("%s: unable to allocate memory for SDRAM" 361 "self-refresh -- LP0/LP1 unavailable\n", 362 __func__); 363 tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2); 364 mode = TEGRA_SUSPEND_LP2; 365 } 366 } 367 368 /* set up sleep function for cpu_suspend */ 369 switch (mode) { 370 case TEGRA_SUSPEND_LP1: 371 tegra_sleep_func = tegra_sleep_core; 372 break; 373 case TEGRA_SUSPEND_LP2: 374 tegra_sleep_func = tegra_sleep_cpu; 375 break; 376 default: 377 break; 378 } 379 380 suspend_set_ops(&tegra_suspend_ops); 381 } 382 #endif 383