1 /* 2 * Copyright (C) 2011 Google, Inc. 3 * 4 * Author: 5 * Colin Cross <ccross@android.com> 6 * 7 * Copyright (C) 2010, NVIDIA Corporation 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/of.h> 25 #include <linux/irqchip/arm-gic.h> 26 27 #include "board.h" 28 #include "iomap.h" 29 30 #define ICTLR_CPU_IEP_VFIQ 0x08 31 #define ICTLR_CPU_IEP_FIR 0x14 32 #define ICTLR_CPU_IEP_FIR_SET 0x18 33 #define ICTLR_CPU_IEP_FIR_CLR 0x1c 34 35 #define ICTLR_CPU_IER 0x20 36 #define ICTLR_CPU_IER_SET 0x24 37 #define ICTLR_CPU_IER_CLR 0x28 38 #define ICTLR_CPU_IEP_CLASS 0x2C 39 40 #define ICTLR_COP_IER 0x30 41 #define ICTLR_COP_IER_SET 0x34 42 #define ICTLR_COP_IER_CLR 0x38 43 #define ICTLR_COP_IEP_CLASS 0x3c 44 45 #define FIRST_LEGACY_IRQ 32 46 47 #define SGI_MASK 0xFFFF 48 49 static int num_ictlrs; 50 51 static void __iomem *ictlr_reg_base[] = { 52 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), 53 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), 54 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), 55 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), 56 IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE), 57 }; 58 59 bool tegra_pending_sgi(void) 60 { 61 u32 pending_set; 62 void __iomem *distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); 63 64 pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET); 65 66 if (pending_set & SGI_MASK) 67 return true; 68 69 return false; 70 } 71 72 static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg) 73 { 74 void __iomem *base; 75 u32 mask; 76 77 BUG_ON(irq < FIRST_LEGACY_IRQ || 78 irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32); 79 80 base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32]; 81 mask = BIT((irq - FIRST_LEGACY_IRQ) % 32); 82 83 __raw_writel(mask, base + reg); 84 } 85 86 static void tegra_mask(struct irq_data *d) 87 { 88 if (d->irq < FIRST_LEGACY_IRQ) 89 return; 90 91 tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR); 92 } 93 94 static void tegra_unmask(struct irq_data *d) 95 { 96 if (d->irq < FIRST_LEGACY_IRQ) 97 return; 98 99 tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET); 100 } 101 102 static void tegra_ack(struct irq_data *d) 103 { 104 if (d->irq < FIRST_LEGACY_IRQ) 105 return; 106 107 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); 108 } 109 110 static void tegra_eoi(struct irq_data *d) 111 { 112 if (d->irq < FIRST_LEGACY_IRQ) 113 return; 114 115 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); 116 } 117 118 static int tegra_retrigger(struct irq_data *d) 119 { 120 if (d->irq < FIRST_LEGACY_IRQ) 121 return 0; 122 123 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET); 124 125 return 1; 126 } 127 128 void __init tegra_init_irq(void) 129 { 130 int i; 131 void __iomem *distbase; 132 133 distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); 134 num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f; 135 136 if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) { 137 WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.", 138 num_ictlrs, ARRAY_SIZE(ictlr_reg_base)); 139 num_ictlrs = ARRAY_SIZE(ictlr_reg_base); 140 } 141 142 for (i = 0; i < num_ictlrs; i++) { 143 void __iomem *ictlr = ictlr_reg_base[i]; 144 writel(~0, ictlr + ICTLR_CPU_IER_CLR); 145 writel(0, ictlr + ICTLR_CPU_IEP_CLASS); 146 } 147 148 gic_arch_extn.irq_ack = tegra_ack; 149 gic_arch_extn.irq_eoi = tegra_eoi; 150 gic_arch_extn.irq_mask = tegra_mask; 151 gic_arch_extn.irq_unmask = tegra_unmask; 152 gic_arch_extn.irq_retrigger = tegra_retrigger; 153 154 /* 155 * Check if there is a devicetree present, since the GIC will be 156 * initialized elsewhere under DT. 157 */ 158 if (!of_have_populated_dt()) 159 gic_init(0, 29, distbase, 160 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 161 } 162