15ad36c5fSErik Gilling /* 2938fa349SColin Cross * Copyright (C) 2011 Google, Inc. 35ad36c5fSErik Gilling * 45ad36c5fSErik Gilling * Author: 5938fa349SColin Cross * Colin Cross <ccross@android.com> 65ad36c5fSErik Gilling * 7460907bcSGary King * Copyright (C) 2010, NVIDIA Corporation 8460907bcSGary King * 95ad36c5fSErik Gilling * This software is licensed under the terms of the GNU General Public 105ad36c5fSErik Gilling * License version 2, as published by the Free Software Foundation, and 115ad36c5fSErik Gilling * may be copied, distributed, and modified under those terms. 125ad36c5fSErik Gilling * 135ad36c5fSErik Gilling * This program is distributed in the hope that it will be useful, 145ad36c5fSErik Gilling * but WITHOUT ANY WARRANTY; without even the implied warranty of 155ad36c5fSErik Gilling * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 165ad36c5fSErik Gilling * GNU General Public License for more details. 175ad36c5fSErik Gilling * 185ad36c5fSErik Gilling */ 195ad36c5fSErik Gilling 205ad36c5fSErik Gilling #include <linux/kernel.h> 215ad36c5fSErik Gilling #include <linux/interrupt.h> 225ad36c5fSErik Gilling #include <linux/irq.h> 235ad36c5fSErik Gilling #include <linux/io.h> 240d4f7479Spdeschrijver@nvidia.com #include <linux/of.h> 255ad36c5fSErik Gilling 265ad36c5fSErik Gilling #include <asm/hardware/gic.h> 275ad36c5fSErik Gilling 285ad36c5fSErik Gilling #include <mach/iomap.h> 295ad36c5fSErik Gilling 305ad36c5fSErik Gilling #include "board.h" 315ad36c5fSErik Gilling 32d1d8c666SColin Cross #define ICTLR_CPU_IEP_VFIQ 0x08 33d1d8c666SColin Cross #define ICTLR_CPU_IEP_FIR 0x14 34d1d8c666SColin Cross #define ICTLR_CPU_IEP_FIR_SET 0x18 35d1d8c666SColin Cross #define ICTLR_CPU_IEP_FIR_CLR 0x1c 36d1d8c666SColin Cross 37d1d8c666SColin Cross #define ICTLR_CPU_IER 0x20 38d1d8c666SColin Cross #define ICTLR_CPU_IER_SET 0x24 39d1d8c666SColin Cross #define ICTLR_CPU_IER_CLR 0x28 40d1d8c666SColin Cross #define ICTLR_CPU_IEP_CLASS 0x2C 41d1d8c666SColin Cross 42d1d8c666SColin Cross #define ICTLR_COP_IER 0x30 43d1d8c666SColin Cross #define ICTLR_COP_IER_SET 0x34 44d1d8c666SColin Cross #define ICTLR_COP_IER_CLR 0x38 45d1d8c666SColin Cross #define ICTLR_COP_IEP_CLASS 0x3c 46d1d8c666SColin Cross 47d1d8c666SColin Cross #define FIRST_LEGACY_IRQ 32 48d1d8c666SColin Cross 49caa4868eSPeter De Schrijver static int num_ictlrs; 50caa4868eSPeter De Schrijver 51d1d8c666SColin Cross static void __iomem *ictlr_reg_base[] = { 52d1d8c666SColin Cross IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), 53d1d8c666SColin Cross IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), 54d1d8c666SColin Cross IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), 55d1d8c666SColin Cross IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), 56caa4868eSPeter De Schrijver IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE), 57d1d8c666SColin Cross }; 58d1d8c666SColin Cross 59d1d8c666SColin Cross static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg) 60d1d8c666SColin Cross { 61d1d8c666SColin Cross void __iomem *base; 62d1d8c666SColin Cross u32 mask; 63d1d8c666SColin Cross 64d1d8c666SColin Cross BUG_ON(irq < FIRST_LEGACY_IRQ || 65caa4868eSPeter De Schrijver irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32); 66d1d8c666SColin Cross 67d1d8c666SColin Cross base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32]; 68d1d8c666SColin Cross mask = BIT((irq - FIRST_LEGACY_IRQ) % 32); 69d1d8c666SColin Cross 70d1d8c666SColin Cross __raw_writel(mask, base + reg); 71d1d8c666SColin Cross } 72d1d8c666SColin Cross 7337337a8dSLennert Buytenhek static void tegra_mask(struct irq_data *d) 74460907bcSGary King { 75d1d8c666SColin Cross if (d->irq < FIRST_LEGACY_IRQ) 76d1d8c666SColin Cross return; 77d1d8c666SColin Cross 78d1d8c666SColin Cross tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR); 79460907bcSGary King } 80460907bcSGary King 8137337a8dSLennert Buytenhek static void tegra_unmask(struct irq_data *d) 82460907bcSGary King { 83d1d8c666SColin Cross if (d->irq < FIRST_LEGACY_IRQ) 84d1d8c666SColin Cross return; 85d1d8c666SColin Cross 86d1d8c666SColin Cross tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET); 87460907bcSGary King } 88460907bcSGary King 8926d902c0SColin Cross static void tegra_ack(struct irq_data *d) 9026d902c0SColin Cross { 91d1d8c666SColin Cross if (d->irq < FIRST_LEGACY_IRQ) 92d1d8c666SColin Cross return; 93d1d8c666SColin Cross 94d1d8c666SColin Cross tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); 9526d902c0SColin Cross } 9626d902c0SColin Cross 974bd66cfdSColin Cross static void tegra_eoi(struct irq_data *d) 984bd66cfdSColin Cross { 994bd66cfdSColin Cross if (d->irq < FIRST_LEGACY_IRQ) 1004bd66cfdSColin Cross return; 1014bd66cfdSColin Cross 1024bd66cfdSColin Cross tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR); 1034bd66cfdSColin Cross } 1044bd66cfdSColin Cross 10526d902c0SColin Cross static int tegra_retrigger(struct irq_data *d) 10626d902c0SColin Cross { 107d1d8c666SColin Cross if (d->irq < FIRST_LEGACY_IRQ) 108938fa349SColin Cross return 0; 109938fa349SColin Cross 110d1d8c666SColin Cross tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET); 111d1d8c666SColin Cross 11226d902c0SColin Cross return 1; 11326d902c0SColin Cross } 11426d902c0SColin Cross 1155ad36c5fSErik Gilling void __init tegra_init_irq(void) 1165ad36c5fSErik Gilling { 117d1d8c666SColin Cross int i; 118caa4868eSPeter De Schrijver void __iomem *distbase; 119d1d8c666SColin Cross 120caa4868eSPeter De Schrijver distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); 121caa4868eSPeter De Schrijver num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f; 122caa4868eSPeter De Schrijver 123caa4868eSPeter De Schrijver if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) { 124caa4868eSPeter De Schrijver WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.", 125caa4868eSPeter De Schrijver num_ictlrs, ARRAY_SIZE(ictlr_reg_base)); 126caa4868eSPeter De Schrijver num_ictlrs = ARRAY_SIZE(ictlr_reg_base); 127caa4868eSPeter De Schrijver } 128caa4868eSPeter De Schrijver 129caa4868eSPeter De Schrijver for (i = 0; i < num_ictlrs; i++) { 130d1d8c666SColin Cross void __iomem *ictlr = ictlr_reg_base[i]; 131d1d8c666SColin Cross writel(~0, ictlr + ICTLR_CPU_IER_CLR); 132d1d8c666SColin Cross writel(0, ictlr + ICTLR_CPU_IEP_CLASS); 133d1d8c666SColin Cross } 134460907bcSGary King 135938fa349SColin Cross gic_arch_extn.irq_ack = tegra_ack; 1364bd66cfdSColin Cross gic_arch_extn.irq_eoi = tegra_eoi; 137938fa349SColin Cross gic_arch_extn.irq_mask = tegra_mask; 138938fa349SColin Cross gic_arch_extn.irq_unmask = tegra_unmask; 139938fa349SColin Cross gic_arch_extn.irq_retrigger = tegra_retrigger; 140938fa349SColin Cross 1410d4f7479Spdeschrijver@nvidia.com /* 1420d4f7479Spdeschrijver@nvidia.com * Check if there is a devicetree present, since the GIC will be 1430d4f7479Spdeschrijver@nvidia.com * initialized elsewhere under DT. 1440d4f7479Spdeschrijver@nvidia.com */ 1450d4f7479Spdeschrijver@nvidia.com if (!of_have_populated_dt()) 146caa4868eSPeter De Schrijver gic_init(0, 29, distbase, 147b580b899SRussell King IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 148460907bcSGary King } 149