15ad36c5fSErik Gilling /* 25ad36c5fSErik Gilling * Copyright (C) 2010 Google, Inc. 35ad36c5fSErik Gilling * 45ad36c5fSErik Gilling * Author: 55ad36c5fSErik Gilling * Colin Cross <ccross@google.com> 65ad36c5fSErik Gilling * 7460907bcSGary King * Copyright (C) 2010, NVIDIA Corporation 8460907bcSGary King * 95ad36c5fSErik Gilling * This software is licensed under the terms of the GNU General Public 105ad36c5fSErik Gilling * License version 2, as published by the Free Software Foundation, and 115ad36c5fSErik Gilling * may be copied, distributed, and modified under those terms. 125ad36c5fSErik Gilling * 135ad36c5fSErik Gilling * This program is distributed in the hope that it will be useful, 145ad36c5fSErik Gilling * but WITHOUT ANY WARRANTY; without even the implied warranty of 155ad36c5fSErik Gilling * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 165ad36c5fSErik Gilling * GNU General Public License for more details. 175ad36c5fSErik Gilling * 185ad36c5fSErik Gilling */ 195ad36c5fSErik Gilling 205ad36c5fSErik Gilling #include <linux/kernel.h> 213524b70eSColin Cross #include <linux/delay.h> 225ad36c5fSErik Gilling #include <linux/init.h> 235ad36c5fSErik Gilling #include <linux/interrupt.h> 245ad36c5fSErik Gilling #include <linux/irq.h> 255ad36c5fSErik Gilling #include <linux/io.h> 265ad36c5fSErik Gilling 275ad36c5fSErik Gilling #include <asm/hardware/gic.h> 285ad36c5fSErik Gilling 295ad36c5fSErik Gilling #include <mach/iomap.h> 303524b70eSColin Cross #include <mach/legacy_irq.h> 312ea67fd1SColin Cross #include <mach/suspend.h> 325ad36c5fSErik Gilling 335ad36c5fSErik Gilling #include "board.h" 345ad36c5fSErik Gilling 353524b70eSColin Cross #define PMC_CTRL 0x0 363524b70eSColin Cross #define PMC_CTRL_LATCH_WAKEUPS (1 << 5) 373524b70eSColin Cross #define PMC_WAKE_MASK 0xc 383524b70eSColin Cross #define PMC_WAKE_LEVEL 0x10 393524b70eSColin Cross #define PMC_WAKE_STATUS 0x14 403524b70eSColin Cross #define PMC_SW_WAKE_STATUS 0x18 413524b70eSColin Cross #define PMC_DPD_SAMPLE 0x20 42460907bcSGary King 433524b70eSColin Cross static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); 44460907bcSGary King 453524b70eSColin Cross static u32 tegra_lp0_wake_enb; 463524b70eSColin Cross static u32 tegra_lp0_wake_level; 473524b70eSColin Cross static u32 tegra_lp0_wake_level_any; 48460907bcSGary King 49cc939754SColin Cross static void (*tegra_gic_mask_irq)(struct irq_data *d); 50cc939754SColin Cross static void (*tegra_gic_unmask_irq)(struct irq_data *d); 51460907bcSGary King 523524b70eSColin Cross /* ensures that sufficient time is passed for a register write to 533524b70eSColin Cross * serialize into the 32KHz domain */ 543524b70eSColin Cross static void pmc_32kwritel(u32 val, unsigned long offs) 553524b70eSColin Cross { 563524b70eSColin Cross writel(val, pmc + offs); 573524b70eSColin Cross udelay(130); 583524b70eSColin Cross } 593524b70eSColin Cross 603524b70eSColin Cross int tegra_set_lp1_wake(int irq, int enable) 613524b70eSColin Cross { 623524b70eSColin Cross return tegra_legacy_irq_set_wake(irq, enable); 633524b70eSColin Cross } 643524b70eSColin Cross 653524b70eSColin Cross void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any) 663524b70eSColin Cross { 673524b70eSColin Cross u32 temp; 683524b70eSColin Cross u32 status; 693524b70eSColin Cross u32 lvl; 703524b70eSColin Cross 713524b70eSColin Cross wake_level &= wake_enb; 723524b70eSColin Cross wake_any &= wake_enb; 733524b70eSColin Cross 743524b70eSColin Cross wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb); 753524b70eSColin Cross wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb); 763524b70eSColin Cross 773524b70eSColin Cross wake_enb |= tegra_lp0_wake_enb; 783524b70eSColin Cross 793524b70eSColin Cross pmc_32kwritel(0, PMC_SW_WAKE_STATUS); 803524b70eSColin Cross temp = readl(pmc + PMC_CTRL); 813524b70eSColin Cross temp |= PMC_CTRL_LATCH_WAKEUPS; 823524b70eSColin Cross pmc_32kwritel(temp, PMC_CTRL); 833524b70eSColin Cross temp &= ~PMC_CTRL_LATCH_WAKEUPS; 843524b70eSColin Cross pmc_32kwritel(temp, PMC_CTRL); 853524b70eSColin Cross status = readl(pmc + PMC_SW_WAKE_STATUS); 863524b70eSColin Cross lvl = readl(pmc + PMC_WAKE_LEVEL); 873524b70eSColin Cross 883524b70eSColin Cross /* flip the wakeup trigger for any-edge triggered pads 893524b70eSColin Cross * which are currently asserting as wakeups */ 903524b70eSColin Cross lvl ^= status; 913524b70eSColin Cross lvl &= wake_any; 923524b70eSColin Cross 933524b70eSColin Cross wake_level |= lvl; 943524b70eSColin Cross 953524b70eSColin Cross writel(wake_level, pmc + PMC_WAKE_LEVEL); 963524b70eSColin Cross /* Enable DPD sample to trigger sampling pads data and direction 973524b70eSColin Cross * in which pad will be driven during lp0 mode*/ 983524b70eSColin Cross writel(0x1, pmc + PMC_DPD_SAMPLE); 993524b70eSColin Cross 1003524b70eSColin Cross writel(wake_enb, pmc + PMC_WAKE_MASK); 1013524b70eSColin Cross } 102460907bcSGary King 10337337a8dSLennert Buytenhek static void tegra_mask(struct irq_data *d) 104460907bcSGary King { 105cc939754SColin Cross tegra_gic_mask_irq(d); 1063524b70eSColin Cross tegra_legacy_mask_irq(d->irq); 107460907bcSGary King } 108460907bcSGary King 10937337a8dSLennert Buytenhek static void tegra_unmask(struct irq_data *d) 110460907bcSGary King { 111cc939754SColin Cross tegra_gic_unmask_irq(d); 1123524b70eSColin Cross tegra_legacy_unmask_irq(d->irq); 113460907bcSGary King } 114460907bcSGary King 115460907bcSGary King static struct irq_chip tegra_irq = { 116460907bcSGary King .name = "PPI", 11737337a8dSLennert Buytenhek .irq_mask = tegra_mask, 11837337a8dSLennert Buytenhek .irq_unmask = tegra_unmask, 119460907bcSGary King }; 120460907bcSGary King 1215ad36c5fSErik Gilling void __init tegra_init_irq(void) 1225ad36c5fSErik Gilling { 123460907bcSGary King struct irq_chip *gic; 124460907bcSGary King unsigned int i; 1253524b70eSColin Cross int irq; 126460907bcSGary King 1273524b70eSColin Cross tegra_init_legacy_irq(); 128460907bcSGary King 129b580b899SRussell King gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 130b580b899SRussell King IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 131460907bcSGary King 132460907bcSGary King gic = get_irq_chip(29); 133cc939754SColin Cross tegra_gic_unmask_irq = gic->irq_unmask; 134cc939754SColin Cross tegra_gic_mask_irq = gic->irq_mask; 13537337a8dSLennert Buytenhek tegra_irq.irq_ack = gic->irq_ack; 136460907bcSGary King #ifdef CONFIG_SMP 13737337a8dSLennert Buytenhek tegra_irq.irq_set_affinity = gic->irq_set_affinity; 138460907bcSGary King #endif 139460907bcSGary King 1403524b70eSColin Cross for (i = 0; i < INT_MAIN_NR; i++) { 1413524b70eSColin Cross irq = INT_PRI_BASE + i; 1423524b70eSColin Cross set_irq_chip(irq, &tegra_irq); 1433524b70eSColin Cross set_irq_handler(irq, handle_level_irq); 1443524b70eSColin Cross set_irq_flags(irq, IRQF_VALID); 1455ad36c5fSErik Gilling } 146460907bcSGary King } 147