1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * Author: 5 * Colin Cross <ccross@google.com> 6 * Erik Gilling <konkers@google.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef __MACH_TEGRA_IOMAP_H 20 #define __MACH_TEGRA_IOMAP_H 21 22 #include <asm/sizes.h> 23 24 #define TEGRA_IRAM_BASE 0x40000000 25 #define TEGRA_IRAM_SIZE SZ_256K 26 27 #define TEGRA_HOST1X_BASE 0x50000000 28 #define TEGRA_HOST1X_SIZE 0x24000 29 30 #define TEGRA_ARM_PERIF_BASE 0x50040000 31 #define TEGRA_ARM_PERIF_SIZE SZ_8K 32 33 #define TEGRA_ARM_PL310_BASE 0x50043000 34 #define TEGRA_ARM_PL310_SIZE SZ_4K 35 36 #define TEGRA_ARM_INT_DIST_BASE 0x50041000 37 #define TEGRA_ARM_INT_DIST_SIZE SZ_4K 38 39 #define TEGRA_MPE_BASE 0x54040000 40 #define TEGRA_MPE_SIZE SZ_256K 41 42 #define TEGRA_VI_BASE 0x54080000 43 #define TEGRA_VI_SIZE SZ_256K 44 45 #define TEGRA_ISP_BASE 0x54100000 46 #define TEGRA_ISP_SIZE SZ_256K 47 48 #define TEGRA_DISPLAY_BASE 0x54200000 49 #define TEGRA_DISPLAY_SIZE SZ_256K 50 51 #define TEGRA_DISPLAY2_BASE 0x54240000 52 #define TEGRA_DISPLAY2_SIZE SZ_256K 53 54 #define TEGRA_HDMI_BASE 0x54280000 55 #define TEGRA_HDMI_SIZE SZ_256K 56 57 #define TEGRA_GART_BASE 0x58000000 58 #define TEGRA_GART_SIZE SZ_32M 59 60 #define TEGRA_RES_SEMA_BASE 0x60001000 61 #define TEGRA_RES_SEMA_SIZE SZ_4K 62 63 #define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 64 #define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 65 66 #define TEGRA_SECONDARY_ICTLR_BASE 0x60004100 67 #define TEGRA_SECONDARY_ICTLR_SIZE SZ_64 68 69 #define TEGRA_TERTIARY_ICTLR_BASE 0x60004200 70 #define TEGRA_TERTIARY_ICTLR_SIZE SZ_64 71 72 #define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300 73 #define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64 74 75 #define TEGRA_QUINARY_ICTLR_BASE 0x60004400 76 #define TEGRA_QUINARY_ICTLR_SIZE SZ_64 77 78 #define TEGRA_TMR1_BASE 0x60005000 79 #define TEGRA_TMR1_SIZE SZ_8 80 81 #define TEGRA_TMR2_BASE 0x60005008 82 #define TEGRA_TMR2_SIZE SZ_8 83 84 #define TEGRA_TMRUS_BASE 0x60005010 85 #define TEGRA_TMRUS_SIZE SZ_64 86 87 #define TEGRA_TMR3_BASE 0x60005050 88 #define TEGRA_TMR3_SIZE SZ_8 89 90 #define TEGRA_TMR4_BASE 0x60005058 91 #define TEGRA_TMR4_SIZE SZ_8 92 93 #define TEGRA_CLK_RESET_BASE 0x60006000 94 #define TEGRA_CLK_RESET_SIZE SZ_4K 95 96 #define TEGRA_FLOW_CTRL_BASE 0x60007000 97 #define TEGRA_FLOW_CTRL_SIZE 20 98 99 #define TEGRA_AHB_DMA_BASE 0x60008000 100 #define TEGRA_AHB_DMA_SIZE SZ_4K 101 102 #define TEGRA_AHB_DMA_CH0_BASE 0x60009000 103 #define TEGRA_AHB_DMA_CH0_SIZE 32 104 105 #define TEGRA_APB_DMA_BASE 0x6000A000 106 #define TEGRA_APB_DMA_SIZE SZ_4K 107 108 #define TEGRA_APB_DMA_CH0_BASE 0x6000B000 109 #define TEGRA_APB_DMA_CH0_SIZE 32 110 111 #define TEGRA_AHB_GIZMO_BASE 0x6000C004 112 #define TEGRA_AHB_GIZMO_SIZE 0x10C 113 114 #define TEGRA_SB_BASE 0x6000C200 115 #define TEGRA_SB_SIZE 256 116 117 #define TEGRA_STATMON_BASE 0x6000C400 118 #define TEGRA_STATMON_SIZE SZ_1K 119 120 #define TEGRA_GPIO_BASE 0x6000D000 121 #define TEGRA_GPIO_SIZE SZ_4K 122 123 #define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 124 #define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K 125 126 #define TEGRA_APB_MISC_BASE 0x70000000 127 #define TEGRA_APB_MISC_SIZE SZ_4K 128 129 #define TEGRA_APB_MISC_DAS_BASE 0x70000c00 130 #define TEGRA_APB_MISC_DAS_SIZE SZ_128 131 132 #define TEGRA_AC97_BASE 0x70002000 133 #define TEGRA_AC97_SIZE SZ_512 134 135 #define TEGRA_SPDIF_BASE 0x70002400 136 #define TEGRA_SPDIF_SIZE SZ_512 137 138 #define TEGRA_I2S1_BASE 0x70002800 139 #define TEGRA_I2S1_SIZE SZ_256 140 141 #define TEGRA_I2S2_BASE 0x70002A00 142 #define TEGRA_I2S2_SIZE SZ_256 143 144 #define TEGRA_UARTA_BASE 0x70006000 145 #define TEGRA_UARTA_SIZE SZ_64 146 147 #define TEGRA_UARTB_BASE 0x70006040 148 #define TEGRA_UARTB_SIZE SZ_64 149 150 #define TEGRA_UARTC_BASE 0x70006200 151 #define TEGRA_UARTC_SIZE SZ_256 152 153 #define TEGRA_UARTD_BASE 0x70006300 154 #define TEGRA_UARTD_SIZE SZ_256 155 156 #define TEGRA_UARTE_BASE 0x70006400 157 #define TEGRA_UARTE_SIZE SZ_256 158 159 #define TEGRA_NAND_BASE 0x70008000 160 #define TEGRA_NAND_SIZE SZ_256 161 162 #define TEGRA_HSMMC_BASE 0x70008500 163 #define TEGRA_HSMMC_SIZE SZ_256 164 165 #define TEGRA_SNOR_BASE 0x70009000 166 #define TEGRA_SNOR_SIZE SZ_4K 167 168 #define TEGRA_PWFM_BASE 0x7000A000 169 #define TEGRA_PWFM_SIZE SZ_256 170 171 #define TEGRA_PWFM0_BASE 0x7000A000 172 #define TEGRA_PWFM0_SIZE 4 173 174 #define TEGRA_PWFM1_BASE 0x7000A010 175 #define TEGRA_PWFM1_SIZE 4 176 177 #define TEGRA_PWFM2_BASE 0x7000A020 178 #define TEGRA_PWFM2_SIZE 4 179 180 #define TEGRA_PWFM3_BASE 0x7000A030 181 #define TEGRA_PWFM3_SIZE 4 182 183 #define TEGRA_MIPI_BASE 0x7000B000 184 #define TEGRA_MIPI_SIZE SZ_256 185 186 #define TEGRA_I2C_BASE 0x7000C000 187 #define TEGRA_I2C_SIZE SZ_256 188 189 #define TEGRA_TWC_BASE 0x7000C100 190 #define TEGRA_TWC_SIZE SZ_256 191 192 #define TEGRA_SPI_BASE 0x7000C380 193 #define TEGRA_SPI_SIZE 48 194 195 #define TEGRA_I2C2_BASE 0x7000C400 196 #define TEGRA_I2C2_SIZE SZ_256 197 198 #define TEGRA_I2C3_BASE 0x7000C500 199 #define TEGRA_I2C3_SIZE SZ_256 200 201 #define TEGRA_OWR_BASE 0x7000C600 202 #define TEGRA_OWR_SIZE 80 203 204 #define TEGRA_DVC_BASE 0x7000D000 205 #define TEGRA_DVC_SIZE SZ_512 206 207 #define TEGRA_SPI1_BASE 0x7000D400 208 #define TEGRA_SPI1_SIZE SZ_512 209 210 #define TEGRA_SPI2_BASE 0x7000D600 211 #define TEGRA_SPI2_SIZE SZ_512 212 213 #define TEGRA_SPI3_BASE 0x7000D800 214 #define TEGRA_SPI3_SIZE SZ_512 215 216 #define TEGRA_SPI4_BASE 0x7000DA00 217 #define TEGRA_SPI4_SIZE SZ_512 218 219 #define TEGRA_RTC_BASE 0x7000E000 220 #define TEGRA_RTC_SIZE SZ_256 221 222 #define TEGRA_KBC_BASE 0x7000E200 223 #define TEGRA_KBC_SIZE SZ_256 224 225 #define TEGRA_PMC_BASE 0x7000E400 226 #define TEGRA_PMC_SIZE SZ_256 227 228 #define TEGRA_MC_BASE 0x7000F000 229 #define TEGRA_MC_SIZE SZ_1K 230 231 #define TEGRA_EMC_BASE 0x7000F400 232 #define TEGRA_EMC_SIZE SZ_1K 233 234 #define TEGRA_FUSE_BASE 0x7000F800 235 #define TEGRA_FUSE_SIZE SZ_1K 236 237 #define TEGRA_KFUSE_BASE 0x7000FC00 238 #define TEGRA_KFUSE_SIZE SZ_1K 239 240 #define TEGRA_CSITE_BASE 0x70040000 241 #define TEGRA_CSITE_SIZE SZ_256K 242 243 #define TEGRA_USB_BASE 0xC5000000 244 #define TEGRA_USB_SIZE SZ_16K 245 246 #define TEGRA_USB2_BASE 0xC5004000 247 #define TEGRA_USB2_SIZE SZ_16K 248 249 #define TEGRA_USB3_BASE 0xC5008000 250 #define TEGRA_USB3_SIZE SZ_16K 251 252 #define TEGRA_SDMMC1_BASE 0xC8000000 253 #define TEGRA_SDMMC1_SIZE SZ_512 254 255 #define TEGRA_SDMMC2_BASE 0xC8000200 256 #define TEGRA_SDMMC2_SIZE SZ_512 257 258 #define TEGRA_SDMMC3_BASE 0xC8000400 259 #define TEGRA_SDMMC3_SIZE SZ_512 260 261 #define TEGRA_SDMMC4_BASE 0xC8000600 262 #define TEGRA_SDMMC4_SIZE SZ_512 263 264 /* On TEGRA, many peripherals are very closely packed in 265 * two 256MB io windows (that actually only use about 64KB 266 * at the start of each). 267 * 268 * We will just map the first 1MB of each window (to minimize 269 * pt entries needed) and provide a macro to transform physical 270 * io addresses to an appropriate void __iomem *. 271 * 272 */ 273 274 #define IO_IRAM_PHYS 0x40000000 275 #define IO_IRAM_VIRT IOMEM(0xFE400000) 276 #define IO_IRAM_SIZE SZ_256K 277 278 #define IO_CPU_PHYS 0x50040000 279 #define IO_CPU_VIRT IOMEM(0xFE000000) 280 #define IO_CPU_SIZE SZ_16K 281 282 #define IO_PPSB_PHYS 0x60000000 283 #define IO_PPSB_VIRT IOMEM(0xFE200000) 284 #define IO_PPSB_SIZE SZ_1M 285 286 #define IO_APB_PHYS 0x70000000 287 #define IO_APB_VIRT IOMEM(0xFE300000) 288 #define IO_APB_SIZE SZ_1M 289 290 #define TEGRA_PCIE_BASE 0x80000000 291 #define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M) 292 293 #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 294 #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) 295 296 #define IO_TO_VIRT(n) ( \ 297 IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \ 298 IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \ 299 IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \ 300 IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \ 301 IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \ 302 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \ 303 IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \ 304 IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \ 305 NULL) 306 307 #define IO_ADDRESS(n) (IO_TO_VIRT(n)) 308 309 #endif 310