1c5f80065SErik Gillingif ARCH_TEGRA 2c5f80065SErik Gilling 3c5f80065SErik Gillingcomment "NVIDIA Tegra options" 4c5f80065SErik Gilling 5c5f80065SErik Gillingconfig ARCH_TEGRA_2x_SOC 644107d8bSPeter De Schrijver bool "Enable support for Tegra20 family" 73c92db9aSErik Gilling select ARCH_REQUIRE_GPIOLIB 8f35b431dSStephen Warren select ARM_ERRATA_720789 9f35b431dSStephen Warren select ARM_ERRATA_742230 10f35b431dSStephen Warren select ARM_ERRATA_751472 11f35b431dSStephen Warren select ARM_ERRATA_754327 128f90cce5SArnd Bergmann select ARM_ERRATA_764369 if SMP 13b1b3f49cSRussell King select ARM_GIC 14b1b3f49cSRussell King select CPU_FREQ_TABLE if CPU_FREQ 15b1b3f49cSRussell King select CPU_V7 16b1b3f49cSRussell King select PINCTRL 17b1b3f49cSRussell King select PINCTRL_TEGRA20 18f35b431dSStephen Warren select PL310_ERRATA_727915 if CACHE_L2X0 19f35b431dSStephen Warren select PL310_ERRATA_769419 if CACHE_L2X0 20b1b3f49cSRussell King select USB_ARCH_HAS_EHCI if USB_SUPPORT 21b1b3f49cSRussell King select USB_ULPI if USB 22b1b3f49cSRussell King select USB_ULPI_VIEWPORT if USB_SUPPORT 23c5f80065SErik Gilling help 24c5f80065SErik Gilling Support for NVIDIA Tegra AP20 and T20 processors, based on the 25c5f80065SErik Gilling ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 26c5f80065SErik Gilling 2744107d8bSPeter De Schrijverconfig ARCH_TEGRA_3x_SOC 2844107d8bSPeter De Schrijver bool "Enable support for Tegra30 family" 2944107d8bSPeter De Schrijver select ARCH_REQUIRE_GPIOLIB 30f35b431dSStephen Warren select ARM_ERRATA_743622 31f35b431dSStephen Warren select ARM_ERRATA_751472 32f35b431dSStephen Warren select ARM_ERRATA_754322 338f90cce5SArnd Bergmann select ARM_ERRATA_764369 if SMP 34b1b3f49cSRussell King select ARM_GIC 35013df388SArnd Bergmann select CPU_FREQ_TABLE if CPU_FREQ 36b1b3f49cSRussell King select CPU_V7 37b1b3f49cSRussell King select PINCTRL 38b1b3f49cSRussell King select PINCTRL_TEGRA30 39b1b3f49cSRussell King select PL310_ERRATA_769419 if CACHE_L2X0 40b1b3f49cSRussell King select USB_ARCH_HAS_EHCI if USB_SUPPORT 41b1b3f49cSRussell King select USB_ULPI if USB 42b1b3f49cSRussell King select USB_ULPI_VIEWPORT if USB_SUPPORT 4344107d8bSPeter De Schrijver help 4444107d8bSPeter De Schrijver Support for NVIDIA Tegra T30 processor family, based on the 4544107d8bSPeter De Schrijver ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 46c5f80065SErik Gilling 4777ffc146SMike Rapoportconfig TEGRA_PCI 4877ffc146SMike Rapoport bool "PCI Express support" 49b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 5077ffc146SMike Rapoport select PCI 5177ffc146SMike Rapoport 5287d0bab2SHiroshi DOYUconfig TEGRA_AHB 5387d0bab2SHiroshi DOYU bool "Enable AHB driver for NVIDIA Tegra SoCs" 5487d0bab2SHiroshi DOYU default y 5587d0bab2SHiroshi DOYU help 5687d0bab2SHiroshi DOYU Adds AHB configuration functionality for NVIDIA Tegra SoCs, 5787d0bab2SHiroshi DOYU which controls AHB bus master arbitration and some 58e41e85ccSMasanari Iida performance parameters(priority, prefech size). 5987d0bab2SHiroshi DOYU 60c5f80065SErik Gillingchoice 6180881daeSStephen Warren prompt "Default low-level debug console UART" 62c5f80065SErik Gilling default TEGRA_DEBUG_UART_NONE 63c5f80065SErik Gilling 64c5f80065SErik Gillingconfig TEGRA_DEBUG_UART_NONE 65c5f80065SErik Gilling bool "None" 66c5f80065SErik Gilling 67c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTA 68c5f80065SErik Gilling bool "UART-A" 69c5f80065SErik Gilling 70c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTB 71c5f80065SErik Gilling bool "UART-B" 72c5f80065SErik Gilling 73c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTC 74c5f80065SErik Gilling bool "UART-C" 75c5f80065SErik Gilling 76c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTD 77c5f80065SErik Gilling bool "UART-D" 78c5f80065SErik Gilling 79c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTE 80c5f80065SErik Gilling bool "UART-E" 81c5f80065SErik Gilling 82c5f80065SErik Gillingendchoice 83c5f80065SErik Gilling 8480881daeSStephen Warrenchoice 8580881daeSStephen Warren prompt "Automatic low-level debug console UART" 8680881daeSStephen Warren default TEGRA_DEBUG_UART_AUTO_NONE 8780881daeSStephen Warren 8880881daeSStephen Warrenconfig TEGRA_DEBUG_UART_AUTO_NONE 8980881daeSStephen Warren bool "None" 9080881daeSStephen Warren 9180881daeSStephen Warrenconfig TEGRA_DEBUG_UART_AUTO_ODMDATA 9280881daeSStephen Warren bool "Via ODMDATA" 9380881daeSStephen Warren help 9480881daeSStephen Warren Automatically determines which UART to use for low-level debug based 9580881daeSStephen Warren on the ODMDATA value. This value is part of the BCT, and is written 9680881daeSStephen Warren to the boot memory device using nvflash, or other flashing tool. 9780881daeSStephen Warren When bits 19:18 are 3, then bits 17:15 indicate which UART to use; 9880881daeSStephen Warren 0/1/2/3/4 are UART A/B/C/D/E. 9980881daeSStephen Warren 10080881daeSStephen Warrenconfig TEGRA_DEBUG_UART_AUTO_SCRATCH 10180881daeSStephen Warren bool "Via UART scratch register" 10280881daeSStephen Warren help 10380881daeSStephen Warren Automatically determines which UART to use for low-level debug based 10480881daeSStephen Warren on the UART scratch register value. Some bootloaders put ASCII 'D' 10580881daeSStephen Warren in this register when they initialize their own console UART output. 10680881daeSStephen Warren Using this option allows the kernel to automatically pick the same 10780881daeSStephen Warren UART. 10880881daeSStephen Warren 10980881daeSStephen Warrenendchoice 11080881daeSStephen Warren 111efdf72adSColin Crossconfig TEGRA_EMC_SCALING_ENABLE 112efdf72adSColin Cross bool "Enable scaling the memory frequency" 11338376866SMark Brown 11438376866SMark Brownendif 115