1c5f80065SErik Gillingif ARCH_TEGRA 2c5f80065SErik Gilling 3c5f80065SErik Gillingcomment "NVIDIA Tegra options" 4c5f80065SErik Gilling 5c5f80065SErik Gillingconfig ARCH_TEGRA_2x_SOC 644107d8bSPeter De Schrijver bool "Enable support for Tegra20 family" 7c5f80065SErik Gilling select CPU_V7 8c5f80065SErik Gilling select ARM_GIC 93c92db9aSErik Gilling select ARCH_REQUIRE_GPIOLIB 10f1f1ffa0SStephen Warren select PINCTRL 11f1f1ffa0SStephen Warren select PINCTRL_TEGRA20 1291525d08SBenoit Goby select USB_ARCH_HAS_EHCI if USB_SUPPORT 13279b6585SArnd Bergmann select USB_ULPI if USB 1491525d08SBenoit Goby select USB_ULPI_VIEWPORT if USB_SUPPORT 15f35b431dSStephen Warren select ARM_ERRATA_720789 16f35b431dSStephen Warren select ARM_ERRATA_742230 17f35b431dSStephen Warren select ARM_ERRATA_751472 18f35b431dSStephen Warren select ARM_ERRATA_754327 198f90cce5SArnd Bergmann select ARM_ERRATA_764369 if SMP 20f35b431dSStephen Warren select PL310_ERRATA_727915 if CACHE_L2X0 21f35b431dSStephen Warren select PL310_ERRATA_769419 if CACHE_L2X0 22013df388SArnd Bergmann select CPU_FREQ_TABLE if CPU_FREQ 23c5f80065SErik Gilling help 24c5f80065SErik Gilling Support for NVIDIA Tegra AP20 and T20 processors, based on the 25c5f80065SErik Gilling ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 26c5f80065SErik Gilling 2744107d8bSPeter De Schrijverconfig ARCH_TEGRA_3x_SOC 2844107d8bSPeter De Schrijver bool "Enable support for Tegra30 family" 2944107d8bSPeter De Schrijver select CPU_V7 3044107d8bSPeter De Schrijver select ARM_GIC 3144107d8bSPeter De Schrijver select ARCH_REQUIRE_GPIOLIB 32f1f1ffa0SStephen Warren select PINCTRL 33f1f1ffa0SStephen Warren select PINCTRL_TEGRA30 3444107d8bSPeter De Schrijver select USB_ARCH_HAS_EHCI if USB_SUPPORT 35279b6585SArnd Bergmann select USB_ULPI if USB 3644107d8bSPeter De Schrijver select USB_ULPI_VIEWPORT if USB_SUPPORT 3744107d8bSPeter De Schrijver select USE_OF 38f35b431dSStephen Warren select ARM_ERRATA_743622 39f35b431dSStephen Warren select ARM_ERRATA_751472 40f35b431dSStephen Warren select ARM_ERRATA_754322 418f90cce5SArnd Bergmann select ARM_ERRATA_764369 if SMP 42f35b431dSStephen Warren select PL310_ERRATA_769419 if CACHE_L2X0 43013df388SArnd Bergmann select CPU_FREQ_TABLE if CPU_FREQ 4444107d8bSPeter De Schrijver help 4544107d8bSPeter De Schrijver Support for NVIDIA Tegra T30 processor family, based on the 4644107d8bSPeter De Schrijver ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 47c5f80065SErik Gilling 4877ffc146SMike Rapoportconfig TEGRA_PCI 4977ffc146SMike Rapoport bool "PCI Express support" 50b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 5177ffc146SMike Rapoport select PCI 5277ffc146SMike Rapoport 5387d0bab2SHiroshi DOYUconfig TEGRA_AHB 5487d0bab2SHiroshi DOYU bool "Enable AHB driver for NVIDIA Tegra SoCs" 5587d0bab2SHiroshi DOYU default y 5687d0bab2SHiroshi DOYU help 5787d0bab2SHiroshi DOYU Adds AHB configuration functionality for NVIDIA Tegra SoCs, 5887d0bab2SHiroshi DOYU which controls AHB bus master arbitration and some 5987d0bab2SHiroshi DOYU perfomance parameters(priority, prefech size). 6087d0bab2SHiroshi DOYU 61c5f80065SErik Gillingcomment "Tegra board type" 62c5f80065SErik Gilling 63c5f80065SErik Gillingconfig MACH_HARMONY 64c5f80065SErik Gilling bool "Harmony board" 65b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 66c5f80065SErik Gilling help 67c5f80065SErik Gilling Support for nVidia Harmony development platform 68c5f80065SErik Gilling 6965b935aaSMarc Dietrichconfig MACH_PAZ00 7065b935aaSMarc Dietrich bool "Paz00 board" 71b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 7265b935aaSMarc Dietrich help 7365b935aaSMarc Dietrich Support for the Toshiba AC100/Dynabook AZ netbook 7465b935aaSMarc Dietrich 75cca414b2SMike Rapoportconfig MACH_TRIMSLICE 76cca414b2SMike Rapoport bool "TrimSlice board" 77b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 78cca414b2SMike Rapoport select TEGRA_PCI 79cca414b2SMike Rapoport help 80cca414b2SMike Rapoport Support for CompuLab TrimSlice platform 81cca414b2SMike Rapoport 82c5f80065SErik Gillingchoice 8380881daeSStephen Warren prompt "Default low-level debug console UART" 84c5f80065SErik Gilling default TEGRA_DEBUG_UART_NONE 85c5f80065SErik Gilling 86c5f80065SErik Gillingconfig TEGRA_DEBUG_UART_NONE 87c5f80065SErik Gilling bool "None" 88c5f80065SErik Gilling 89c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTA 90c5f80065SErik Gilling bool "UART-A" 91c5f80065SErik Gilling 92c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTB 93c5f80065SErik Gilling bool "UART-B" 94c5f80065SErik Gilling 95c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTC 96c5f80065SErik Gilling bool "UART-C" 97c5f80065SErik Gilling 98c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTD 99c5f80065SErik Gilling bool "UART-D" 100c5f80065SErik Gilling 101c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTE 102c5f80065SErik Gilling bool "UART-E" 103c5f80065SErik Gilling 104c5f80065SErik Gillingendchoice 105c5f80065SErik Gilling 10680881daeSStephen Warrenchoice 10780881daeSStephen Warren prompt "Automatic low-level debug console UART" 10880881daeSStephen Warren default TEGRA_DEBUG_UART_AUTO_NONE 10980881daeSStephen Warren 11080881daeSStephen Warrenconfig TEGRA_DEBUG_UART_AUTO_NONE 11180881daeSStephen Warren bool "None" 11280881daeSStephen Warren 11380881daeSStephen Warrenconfig TEGRA_DEBUG_UART_AUTO_ODMDATA 11480881daeSStephen Warren bool "Via ODMDATA" 11580881daeSStephen Warren help 11680881daeSStephen Warren Automatically determines which UART to use for low-level debug based 11780881daeSStephen Warren on the ODMDATA value. This value is part of the BCT, and is written 11880881daeSStephen Warren to the boot memory device using nvflash, or other flashing tool. 11980881daeSStephen Warren When bits 19:18 are 3, then bits 17:15 indicate which UART to use; 12080881daeSStephen Warren 0/1/2/3/4 are UART A/B/C/D/E. 12180881daeSStephen Warren 12280881daeSStephen Warrenconfig TEGRA_DEBUG_UART_AUTO_SCRATCH 12380881daeSStephen Warren bool "Via UART scratch register" 12480881daeSStephen Warren help 12580881daeSStephen Warren Automatically determines which UART to use for low-level debug based 12680881daeSStephen Warren on the UART scratch register value. Some bootloaders put ASCII 'D' 12780881daeSStephen Warren in this register when they initialize their own console UART output. 12880881daeSStephen Warren Using this option allows the kernel to automatically pick the same 12980881daeSStephen Warren UART. 13080881daeSStephen Warren 13180881daeSStephen Warrenendchoice 13280881daeSStephen Warren 1334de3a8faSColin Crossconfig TEGRA_SYSTEM_DMA 1344de3a8faSColin Cross bool "Enable system DMA driver for NVIDIA Tegra SoCs" 1354de3a8faSColin Cross default y 1364de3a8faSColin Cross help 1374de3a8faSColin Cross Adds system DMA functionality for NVIDIA Tegra SoCs, used by 1384de3a8faSColin Cross several Tegra device drivers 1394de3a8faSColin Cross 140efdf72adSColin Crossconfig TEGRA_EMC_SCALING_ENABLE 141efdf72adSColin Cross bool "Enable scaling the memory frequency" 14238376866SMark Brown 14338376866SMark Brownendif 144