1c5f80065SErik Gillingif ARCH_TEGRA 2c5f80065SErik Gilling 3c5f80065SErik Gillingcomment "NVIDIA Tegra options" 4c5f80065SErik Gilling 5c5f80065SErik Gillingconfig ARCH_TEGRA_2x_SOC 644107d8bSPeter De Schrijver bool "Enable support for Tegra20 family" 7c5f80065SErik Gilling select CPU_V7 8c5f80065SErik Gilling select ARM_GIC 93c92db9aSErik Gilling select ARCH_REQUIRE_GPIOLIB 10f1f1ffa0SStephen Warren select PINCTRL 11f1f1ffa0SStephen Warren select PINCTRL_TEGRA20 1291525d08SBenoit Goby select USB_ARCH_HAS_EHCI if USB_SUPPORT 13279b6585SArnd Bergmann select USB_ULPI if USB 1491525d08SBenoit Goby select USB_ULPI_VIEWPORT if USB_SUPPORT 15f35b431dSStephen Warren select ARM_ERRATA_720789 16f35b431dSStephen Warren select ARM_ERRATA_742230 17f35b431dSStephen Warren select ARM_ERRATA_751472 18f35b431dSStephen Warren select ARM_ERRATA_754327 19f35b431dSStephen Warren select ARM_ERRATA_764369 20f35b431dSStephen Warren select PL310_ERRATA_727915 if CACHE_L2X0 21f35b431dSStephen Warren select PL310_ERRATA_769419 if CACHE_L2X0 22013df388SArnd Bergmann select CPU_FREQ_TABLE if CPU_FREQ 23c5f80065SErik Gilling help 24c5f80065SErik Gilling Support for NVIDIA Tegra AP20 and T20 processors, based on the 25c5f80065SErik Gilling ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 26c5f80065SErik Gilling 2744107d8bSPeter De Schrijverconfig ARCH_TEGRA_3x_SOC 2844107d8bSPeter De Schrijver bool "Enable support for Tegra30 family" 2944107d8bSPeter De Schrijver select CPU_V7 3044107d8bSPeter De Schrijver select ARM_GIC 3144107d8bSPeter De Schrijver select ARCH_REQUIRE_GPIOLIB 32f1f1ffa0SStephen Warren select PINCTRL 33f1f1ffa0SStephen Warren select PINCTRL_TEGRA30 3444107d8bSPeter De Schrijver select USB_ARCH_HAS_EHCI if USB_SUPPORT 35279b6585SArnd Bergmann select USB_ULPI if USB 3644107d8bSPeter De Schrijver select USB_ULPI_VIEWPORT if USB_SUPPORT 3744107d8bSPeter De Schrijver select USE_OF 38f35b431dSStephen Warren select ARM_ERRATA_743622 39f35b431dSStephen Warren select ARM_ERRATA_751472 40f35b431dSStephen Warren select ARM_ERRATA_754322 41f35b431dSStephen Warren select ARM_ERRATA_764369 42f35b431dSStephen Warren select PL310_ERRATA_769419 if CACHE_L2X0 43013df388SArnd Bergmann select CPU_FREQ_TABLE if CPU_FREQ 4444107d8bSPeter De Schrijver help 4544107d8bSPeter De Schrijver Support for NVIDIA Tegra T30 processor family, based on the 4644107d8bSPeter De Schrijver ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 47c5f80065SErik Gilling 4877ffc146SMike Rapoportconfig TEGRA_PCI 4977ffc146SMike Rapoport bool "PCI Express support" 50b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 5177ffc146SMike Rapoport select PCI 5277ffc146SMike Rapoport 53c5f80065SErik Gillingcomment "Tegra board type" 54c5f80065SErik Gilling 55c5f80065SErik Gillingconfig MACH_HARMONY 56c5f80065SErik Gilling bool "Harmony board" 57b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 58885f24e1SUwe Kleine-König select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC 59c5f80065SErik Gilling help 60c5f80065SErik Gilling Support for nVidia Harmony development platform 61c5f80065SErik Gilling 62d9a51fe7SOlof Johanssonconfig MACH_KAEN 63d9a51fe7SOlof Johansson bool "Kaen board" 64b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 65d9a51fe7SOlof Johansson select MACH_SEABOARD 66885f24e1SUwe Kleine-König select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC 67d9a51fe7SOlof Johansson help 68d9a51fe7SOlof Johansson Support for the Kaen version of Seaboard 69d9a51fe7SOlof Johansson 7065b935aaSMarc Dietrichconfig MACH_PAZ00 7165b935aaSMarc Dietrich bool "Paz00 board" 72b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 7365b935aaSMarc Dietrich help 7465b935aaSMarc Dietrich Support for the Toshiba AC100/Dynabook AZ netbook 7565b935aaSMarc Dietrich 76d9a51fe7SOlof Johanssonconfig MACH_SEABOARD 77d9a51fe7SOlof Johansson bool "Seaboard board" 78b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 79885f24e1SUwe Kleine-König select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC 80d9a51fe7SOlof Johansson help 81d9a51fe7SOlof Johansson Support for nVidia Seaboard development platform. It will 82d9a51fe7SOlof Johansson also be included for some of the derivative boards that 83d9a51fe7SOlof Johansson have large similarities with the seaboard design. 84d9a51fe7SOlof Johansson 858e267f3dSGrant Likelyconfig MACH_TEGRA_DT 86a2385dc5SPeter De Schrijver bool "Generic Tegra20 board (FDT support)" 8724692c0fSStephen Warren depends on ARCH_TEGRA_2x_SOC 888e267f3dSGrant Likely select USE_OF 898e267f3dSGrant Likely help 90a2385dc5SPeter De Schrijver Support for generic NVIDIA Tegra20 boards using Flattened Device Tree 918e267f3dSGrant Likely 92cca414b2SMike Rapoportconfig MACH_TRIMSLICE 93cca414b2SMike Rapoport bool "TrimSlice board" 94b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 95cca414b2SMike Rapoport select TEGRA_PCI 96cca414b2SMike Rapoport help 97cca414b2SMike Rapoport Support for CompuLab TrimSlice platform 98cca414b2SMike Rapoport 99d9a51fe7SOlof Johanssonconfig MACH_WARIO 100d9a51fe7SOlof Johansson bool "Wario board" 101b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 102d9a51fe7SOlof Johansson select MACH_SEABOARD 103d9a51fe7SOlof Johansson help 104d9a51fe7SOlof Johansson Support for the Wario version of Seaboard 105d9a51fe7SOlof Johansson 106add29e61SPeter De Schrijverconfig MACH_VENTANA 107add29e61SPeter De Schrijver bool "Ventana board" 108b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 109add29e61SPeter De Schrijver select MACH_TEGRA_DT 110add29e61SPeter De Schrijver help 111add29e61SPeter De Schrijver Support for the nVidia Ventana development platform 112add29e61SPeter De Schrijver 113c5f80065SErik Gillingchoice 11480881daeSStephen Warren prompt "Default low-level debug console UART" 115c5f80065SErik Gilling default TEGRA_DEBUG_UART_NONE 116c5f80065SErik Gilling 117c5f80065SErik Gillingconfig TEGRA_DEBUG_UART_NONE 118c5f80065SErik Gilling bool "None" 119c5f80065SErik Gilling 120c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTA 121c5f80065SErik Gilling bool "UART-A" 122c5f80065SErik Gilling 123c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTB 124c5f80065SErik Gilling bool "UART-B" 125c5f80065SErik Gilling 126c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTC 127c5f80065SErik Gilling bool "UART-C" 128c5f80065SErik Gilling 129c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTD 130c5f80065SErik Gilling bool "UART-D" 131c5f80065SErik Gilling 132c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTE 133c5f80065SErik Gilling bool "UART-E" 134c5f80065SErik Gilling 135c5f80065SErik Gillingendchoice 136c5f80065SErik Gilling 13780881daeSStephen Warrenchoice 13880881daeSStephen Warren prompt "Automatic low-level debug console UART" 13980881daeSStephen Warren default TEGRA_DEBUG_UART_AUTO_NONE 14080881daeSStephen Warren 14180881daeSStephen Warrenconfig TEGRA_DEBUG_UART_AUTO_NONE 14280881daeSStephen Warren bool "None" 14380881daeSStephen Warren 14480881daeSStephen Warrenconfig TEGRA_DEBUG_UART_AUTO_ODMDATA 14580881daeSStephen Warren bool "Via ODMDATA" 14680881daeSStephen Warren help 14780881daeSStephen Warren Automatically determines which UART to use for low-level debug based 14880881daeSStephen Warren on the ODMDATA value. This value is part of the BCT, and is written 14980881daeSStephen Warren to the boot memory device using nvflash, or other flashing tool. 15080881daeSStephen Warren When bits 19:18 are 3, then bits 17:15 indicate which UART to use; 15180881daeSStephen Warren 0/1/2/3/4 are UART A/B/C/D/E. 15280881daeSStephen Warren 15380881daeSStephen Warrenconfig TEGRA_DEBUG_UART_AUTO_SCRATCH 15480881daeSStephen Warren bool "Via UART scratch register" 15580881daeSStephen Warren help 15680881daeSStephen Warren Automatically determines which UART to use for low-level debug based 15780881daeSStephen Warren on the UART scratch register value. Some bootloaders put ASCII 'D' 15880881daeSStephen Warren in this register when they initialize their own console UART output. 15980881daeSStephen Warren Using this option allows the kernel to automatically pick the same 16080881daeSStephen Warren UART. 16180881daeSStephen Warren 16280881daeSStephen Warrenendchoice 16380881daeSStephen Warren 1644de3a8faSColin Crossconfig TEGRA_SYSTEM_DMA 1654de3a8faSColin Cross bool "Enable system DMA driver for NVIDIA Tegra SoCs" 1664de3a8faSColin Cross default y 1674de3a8faSColin Cross help 1684de3a8faSColin Cross Adds system DMA functionality for NVIDIA Tegra SoCs, used by 1694de3a8faSColin Cross several Tegra device drivers 1704de3a8faSColin Cross 171efdf72adSColin Crossconfig TEGRA_EMC_SCALING_ENABLE 172efdf72adSColin Cross bool "Enable scaling the memory frequency" 17338376866SMark Brown 17438376866SMark Brownendif 175