121278aeaSRob Herringmenuconfig ARCH_TEGRA 290027225SStephen Warren bool "NVIDIA Tegra" if ARCH_MULTI_V7 390027225SStephen Warren select ARCH_REQUIRE_GPIOLIB 41a5de3aeSAlexandre Courbot select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS 520984c44SStephen Warren select ARM_GIC 690027225SStephen Warren select CLKSRC_MMIO 74c3ffffdSStephen Boyd select HAVE_ARM_SCU if SMP 8a894fcc2SStephen Boyd select HAVE_ARM_TWD if SMP 920984c44SStephen Warren select PINCTRL 10e0421468SStephen Warren select ARCH_HAS_RESET_CONTROLLER 11e0421468SStephen Warren select RESET_CONTROLLER 1290027225SStephen Warren select SOC_BUS 1320984c44SStephen Warren select USB_ULPI if USB_PHY 1420984c44SStephen Warren select USB_ULPI_VIEWPORT if USB_PHY 1590027225SStephen Warren help 1690027225SStephen Warren This enables support for NVIDIA Tegra based systems. 17c5f80065SErik Gilling 1821278aeaSRob Herringif ARCH_TEGRA 19c5f80065SErik Gilling 20c5f80065SErik Gillingconfig ARCH_TEGRA_2x_SOC 2144107d8bSPeter De Schrijver bool "Enable support for Tegra20 family" 221d328606SJoseph Lo select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP 23f35b431dSStephen Warren select ARM_ERRATA_720789 2445c9e592SStephen Warren select ARM_ERRATA_754327 if SMP 258f90cce5SArnd Bergmann select ARM_ERRATA_764369 if SMP 26b1b3f49cSRussell King select PINCTRL_TEGRA20 27f35b431dSStephen Warren select PL310_ERRATA_727915 if CACHE_L2X0 28f35b431dSStephen Warren select PL310_ERRATA_769419 if CACHE_L2X0 29c5f80065SErik Gilling help 30c5f80065SErik Gilling Support for NVIDIA Tegra AP20 and T20 processors, based on the 31c5f80065SErik Gilling ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 32c5f80065SErik Gilling 3344107d8bSPeter De Schrijverconfig ARCH_TEGRA_3x_SOC 3444107d8bSPeter De Schrijver bool "Enable support for Tegra30 family" 35f35b431dSStephen Warren select ARM_ERRATA_754322 368f90cce5SArnd Bergmann select ARM_ERRATA_764369 if SMP 37b1b3f49cSRussell King select PINCTRL_TEGRA30 38b1b3f49cSRussell King select PL310_ERRATA_769419 if CACHE_L2X0 3944107d8bSPeter De Schrijver help 4044107d8bSPeter De Schrijver Support for NVIDIA Tegra T30 processor family, based on the 4144107d8bSPeter De Schrijver ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 42c5f80065SErik Gilling 435c541b88SHiroshi Doyuconfig ARCH_TEGRA_114_SOC 445c541b88SHiroshi Doyu bool "Enable support for Tegra114 family" 4559fd3033SRussell King select ARM_ERRATA_798181 if SMP 461d7e5c2cSStephen Warren select ARM_L1_CACHE_SHIFT_6 47b6bda4e0SStephen Warren select HAVE_ARM_ARCH_TIMER 4820fd4806SLaxman Dewangan select PINCTRL_TEGRA114 495c541b88SHiroshi Doyu help 505c541b88SHiroshi Doyu Support for NVIDIA Tegra T114 processor family, based on the 515c541b88SHiroshi Doyu ARM CortexA15MP CPU 525c541b88SHiroshi Doyu 5373944475SJoseph Loconfig ARCH_TEGRA_124_SOC 5473944475SJoseph Lo bool "Enable support for Tegra124 family" 5573944475SJoseph Lo select ARM_L1_CACHE_SHIFT_6 5673944475SJoseph Lo select HAVE_ARM_ARCH_TIMER 577e1161f8SLaxman Dewangan select PINCTRL_TEGRA124 5873944475SJoseph Lo help 5973944475SJoseph Lo Support for NVIDIA Tegra T124 processor family, based on the 6073944475SJoseph Lo ARM CortexA15MP CPU 6173944475SJoseph Lo 6287d0bab2SHiroshi DOYUconfig TEGRA_AHB 6387d0bab2SHiroshi DOYU bool "Enable AHB driver for NVIDIA Tegra SoCs" 6487d0bab2SHiroshi DOYU default y 6587d0bab2SHiroshi DOYU help 6687d0bab2SHiroshi DOYU Adds AHB configuration functionality for NVIDIA Tegra SoCs, 6787d0bab2SHiroshi DOYU which controls AHB bus master arbitration and some 68e41e85ccSMasanari Iida performance parameters(priority, prefech size). 6987d0bab2SHiroshi DOYU 7021278aeaSRob Herringendif 71