1c5f80065SErik Gillingif ARCH_TEGRA 2c5f80065SErik Gilling 3c5f80065SErik Gillingcomment "NVIDIA Tegra options" 4c5f80065SErik Gilling 5c5f80065SErik Gillingconfig ARCH_TEGRA_2x_SOC 644107d8bSPeter De Schrijver bool "Enable support for Tegra20 family" 7c5f80065SErik Gilling select CPU_V7 8c5f80065SErik Gilling select ARM_GIC 93c92db9aSErik Gilling select ARCH_REQUIRE_GPIOLIB 1091525d08SBenoit Goby select USB_ARCH_HAS_EHCI if USB_SUPPORT 1191525d08SBenoit Goby select USB_ULPI if USB_SUPPORT 1291525d08SBenoit Goby select USB_ULPI_VIEWPORT if USB_SUPPORT 13f35b431dSStephen Warren select ARM_ERRATA_720789 14f35b431dSStephen Warren select ARM_ERRATA_742230 15f35b431dSStephen Warren select ARM_ERRATA_751472 16f35b431dSStephen Warren select ARM_ERRATA_754327 17f35b431dSStephen Warren select ARM_ERRATA_764369 18f35b431dSStephen Warren select PL310_ERRATA_727915 if CACHE_L2X0 19f35b431dSStephen Warren select PL310_ERRATA_769419 if CACHE_L2X0 20013df388SArnd Bergmann select CPU_FREQ_TABLE if CPU_FREQ 21c5f80065SErik Gilling help 22c5f80065SErik Gilling Support for NVIDIA Tegra AP20 and T20 processors, based on the 23c5f80065SErik Gilling ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 24c5f80065SErik Gilling 2544107d8bSPeter De Schrijverconfig ARCH_TEGRA_3x_SOC 2644107d8bSPeter De Schrijver bool "Enable support for Tegra30 family" 2744107d8bSPeter De Schrijver select CPU_V7 2844107d8bSPeter De Schrijver select ARM_GIC 2944107d8bSPeter De Schrijver select ARCH_REQUIRE_GPIOLIB 3044107d8bSPeter De Schrijver select USB_ARCH_HAS_EHCI if USB_SUPPORT 3144107d8bSPeter De Schrijver select USB_ULPI if USB_SUPPORT 3244107d8bSPeter De Schrijver select USB_ULPI_VIEWPORT if USB_SUPPORT 3344107d8bSPeter De Schrijver select USE_OF 34f35b431dSStephen Warren select ARM_ERRATA_743622 35f35b431dSStephen Warren select ARM_ERRATA_751472 36f35b431dSStephen Warren select ARM_ERRATA_754322 37f35b431dSStephen Warren select ARM_ERRATA_764369 38f35b431dSStephen Warren select PL310_ERRATA_769419 if CACHE_L2X0 39013df388SArnd Bergmann select CPU_FREQ_TABLE if CPU_FREQ 4044107d8bSPeter De Schrijver help 4144107d8bSPeter De Schrijver Support for NVIDIA Tegra T30 processor family, based on the 4244107d8bSPeter De Schrijver ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 43c5f80065SErik Gilling 4477ffc146SMike Rapoportconfig TEGRA_PCI 4577ffc146SMike Rapoport bool "PCI Express support" 46b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 4777ffc146SMike Rapoport select PCI 4877ffc146SMike Rapoport 49c5f80065SErik Gillingcomment "Tegra board type" 50c5f80065SErik Gilling 51c5f80065SErik Gillingconfig MACH_HARMONY 52c5f80065SErik Gilling bool "Harmony board" 53b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 54885f24e1SUwe Kleine-König select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC 55c5f80065SErik Gilling help 56c5f80065SErik Gilling Support for nVidia Harmony development platform 57c5f80065SErik Gilling 58d9a51fe7SOlof Johanssonconfig MACH_KAEN 59d9a51fe7SOlof Johansson bool "Kaen board" 60b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 61d9a51fe7SOlof Johansson select MACH_SEABOARD 62885f24e1SUwe Kleine-König select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC 63d9a51fe7SOlof Johansson help 64d9a51fe7SOlof Johansson Support for the Kaen version of Seaboard 65d9a51fe7SOlof Johansson 6665b935aaSMarc Dietrichconfig MACH_PAZ00 6765b935aaSMarc Dietrich bool "Paz00 board" 68b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 6965b935aaSMarc Dietrich help 7065b935aaSMarc Dietrich Support for the Toshiba AC100/Dynabook AZ netbook 7165b935aaSMarc Dietrich 72d9a51fe7SOlof Johanssonconfig MACH_SEABOARD 73d9a51fe7SOlof Johansson bool "Seaboard board" 74b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 75885f24e1SUwe Kleine-König select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC 76d9a51fe7SOlof Johansson help 77d9a51fe7SOlof Johansson Support for nVidia Seaboard development platform. It will 78d9a51fe7SOlof Johansson also be included for some of the derivative boards that 79d9a51fe7SOlof Johansson have large similarities with the seaboard design. 80d9a51fe7SOlof Johansson 818e267f3dSGrant Likelyconfig MACH_TEGRA_DT 82a2385dc5SPeter De Schrijver bool "Generic Tegra20 board (FDT support)" 8324692c0fSStephen Warren depends on ARCH_TEGRA_2x_SOC 848e267f3dSGrant Likely select USE_OF 858e267f3dSGrant Likely help 86a2385dc5SPeter De Schrijver Support for generic NVIDIA Tegra20 boards using Flattened Device Tree 878e267f3dSGrant Likely 88cca414b2SMike Rapoportconfig MACH_TRIMSLICE 89cca414b2SMike Rapoport bool "TrimSlice board" 90b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 91cca414b2SMike Rapoport select TEGRA_PCI 92cca414b2SMike Rapoport help 93cca414b2SMike Rapoport Support for CompuLab TrimSlice platform 94cca414b2SMike Rapoport 95d9a51fe7SOlof Johanssonconfig MACH_WARIO 96d9a51fe7SOlof Johansson bool "Wario board" 97b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 98d9a51fe7SOlof Johansson select MACH_SEABOARD 99d9a51fe7SOlof Johansson help 100d9a51fe7SOlof Johansson Support for the Wario version of Seaboard 101d9a51fe7SOlof Johansson 102add29e61SPeter De Schrijverconfig MACH_VENTANA 103add29e61SPeter De Schrijver bool "Ventana board" 104b2bbbc4dSPeter De Schrijver depends on ARCH_TEGRA_2x_SOC 105add29e61SPeter De Schrijver select MACH_TEGRA_DT 106add29e61SPeter De Schrijver help 107add29e61SPeter De Schrijver Support for the nVidia Ventana development platform 108add29e61SPeter De Schrijver 109c5f80065SErik Gillingchoice 110c5f80065SErik Gilling prompt "Low-level debug console UART" 111c5f80065SErik Gilling default TEGRA_DEBUG_UART_NONE 112c5f80065SErik Gilling 113c5f80065SErik Gillingconfig TEGRA_DEBUG_UART_NONE 114c5f80065SErik Gilling bool "None" 115c5f80065SErik Gilling 116c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTA 117c5f80065SErik Gilling bool "UART-A" 118c5f80065SErik Gilling 119c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTB 120c5f80065SErik Gilling bool "UART-B" 121c5f80065SErik Gilling 122c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTC 123c5f80065SErik Gilling bool "UART-C" 124c5f80065SErik Gilling 125c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTD 126c5f80065SErik Gilling bool "UART-D" 127c5f80065SErik Gilling 128c5f80065SErik Gillingconfig TEGRA_DEBUG_UARTE 129c5f80065SErik Gilling bool "UART-E" 130c5f80065SErik Gilling 131c5f80065SErik Gillingendchoice 132c5f80065SErik Gilling 1334de3a8faSColin Crossconfig TEGRA_SYSTEM_DMA 1344de3a8faSColin Cross bool "Enable system DMA driver for NVIDIA Tegra SoCs" 1354de3a8faSColin Cross default y 1364de3a8faSColin Cross help 1374de3a8faSColin Cross Adds system DMA functionality for NVIDIA Tegra SoCs, used by 1384de3a8faSColin Cross several Tegra device drivers 1394de3a8faSColin Cross 140efdf72adSColin Crossconfig TEGRA_EMC_SCALING_ENABLE 141efdf72adSColin Cross bool "Enable scaling the memory frequency" 14238376866SMark Brown 14338376866SMark Brownendif 144