1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Chen-Yu Tsai 4 * 5 * Chen-Yu Tsai <wens@csie.org> 6 * 7 * arch/arm/mach-sunxi/mc_smp.c 8 * 9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and 10 * arch/arm/mach-hisi/platmcpm.c 11 * Cluster cache enable trampoline code adapted from MCPM framework 12 */ 13 14 #include <linux/arm-cci.h> 15 #include <linux/cpu_pm.h> 16 #include <linux/delay.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/irqchip/arm-gic.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/smp.h> 24 25 #include <asm/cacheflush.h> 26 #include <asm/cp15.h> 27 #include <asm/cputype.h> 28 #include <asm/idmap.h> 29 #include <asm/smp_plat.h> 30 #include <asm/suspend.h> 31 32 #define SUNXI_CPUS_PER_CLUSTER 4 33 #define SUNXI_NR_CLUSTERS 2 34 35 #define POLL_USEC 100 36 #define TIMEOUT_USEC 100000 37 38 #define CPUCFG_CX_CTRL_REG0(c) (0x10 * (c)) 39 #define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(n) BIT(n) 40 #define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL 0xf 41 #define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7 BIT(4) 42 #define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15 BIT(0) 43 #define CPUCFG_CX_CTRL_REG1(c) (0x10 * (c) + 0x4) 44 #define CPUCFG_CX_CTRL_REG1_ACINACTM BIT(0) 45 #define CPUCFG_CX_STATUS(c) (0x30 + 0x4 * (c)) 46 #define CPUCFG_CX_STATUS_STANDBYWFI(n) BIT(16 + (n)) 47 #define CPUCFG_CX_STATUS_STANDBYWFIL2 BIT(0) 48 #define CPUCFG_CX_RST_CTRL(c) (0x80 + 0x4 * (c)) 49 #define CPUCFG_CX_RST_CTRL_DBG_SOC_RST BIT(24) 50 #define CPUCFG_CX_RST_CTRL_ETM_RST(n) BIT(20 + (n)) 51 #define CPUCFG_CX_RST_CTRL_ETM_RST_ALL (0xf << 20) 52 #define CPUCFG_CX_RST_CTRL_DBG_RST(n) BIT(16 + (n)) 53 #define CPUCFG_CX_RST_CTRL_DBG_RST_ALL (0xf << 16) 54 #define CPUCFG_CX_RST_CTRL_H_RST BIT(12) 55 #define CPUCFG_CX_RST_CTRL_L2_RST BIT(8) 56 #define CPUCFG_CX_RST_CTRL_CX_RST(n) BIT(4 + (n)) 57 #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n) 58 #define CPUCFG_CX_RST_CTRL_CORE_RST_ALL (0xf << 0) 59 60 #define PRCM_CPU_PO_RST_CTRL(c) (0x4 + 0x4 * (c)) 61 #define PRCM_CPU_PO_RST_CTRL_CORE(n) BIT(n) 62 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL 0xf 63 #define PRCM_PWROFF_GATING_REG(c) (0x100 + 0x4 * (c)) 64 /* The power off register for clusters are different from a80 and a83t */ 65 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I BIT(0) 66 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I BIT(4) 67 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n) 68 #define PRCM_PWR_SWITCH_REG(c, cpu) (0x140 + 0x10 * (c) + 0x4 * (cpu)) 69 #define PRCM_CPU_SOFT_ENTRY_REG 0x164 70 71 /* R_CPUCFG registers, specific to sun8i-a83t */ 72 #define R_CPUCFG_CLUSTER_PO_RST_CTRL(c) (0x30 + (c) * 0x4) 73 #define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n) BIT(n) 74 #define R_CPUCFG_CPU_SOFT_ENTRY_REG 0x01a4 75 76 #define CPU0_SUPPORT_HOTPLUG_MAGIC0 0xFA50392F 77 #define CPU0_SUPPORT_HOTPLUG_MAGIC1 0x790DCA3A 78 79 static void __iomem *cpucfg_base; 80 static void __iomem *prcm_base; 81 static void __iomem *sram_b_smp_base; 82 static void __iomem *r_cpucfg_base; 83 84 extern void sunxi_mc_smp_secondary_startup(void); 85 extern void sunxi_mc_smp_resume(void); 86 static bool is_a83t; 87 88 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster) 89 { 90 struct device_node *node; 91 int cpu = cluster * SUNXI_CPUS_PER_CLUSTER + core; 92 93 node = of_cpu_device_node_get(cpu); 94 95 /* In case of_cpu_device_node_get fails */ 96 if (!node) 97 node = of_get_cpu_node(cpu, NULL); 98 99 if (!node) { 100 /* 101 * There's no point in returning an error, since we 102 * would be mid way in a core or cluster power sequence. 103 */ 104 pr_err("%s: Couldn't get CPU cluster %u core %u device node\n", 105 __func__, cluster, core); 106 107 return false; 108 } 109 110 return of_device_is_compatible(node, "arm,cortex-a15"); 111 } 112 113 static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster, 114 bool enable) 115 { 116 u32 reg; 117 118 /* control sequence from Allwinner A80 user manual v1.2 PRCM section */ 119 reg = readl(prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); 120 if (enable) { 121 if (reg == 0x00) { 122 pr_debug("power clamp for cluster %u cpu %u already open\n", 123 cluster, cpu); 124 return 0; 125 } 126 127 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); 128 udelay(10); 129 writel(0xfe, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); 130 udelay(10); 131 writel(0xf8, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); 132 udelay(10); 133 writel(0xf0, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); 134 udelay(10); 135 writel(0x00, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); 136 udelay(10); 137 } else { 138 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); 139 udelay(10); 140 } 141 142 return 0; 143 } 144 145 static void sunxi_cpu0_hotplug_support_set(bool enable) 146 { 147 if (enable) { 148 writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base); 149 writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4); 150 } else { 151 writel(0x0, sram_b_smp_base); 152 writel(0x0, sram_b_smp_base + 0x4); 153 } 154 } 155 156 static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster) 157 { 158 u32 reg; 159 160 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu); 161 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS) 162 return -EINVAL; 163 164 /* Set hotplug support magic flags for cpu0 */ 165 if (cluster == 0 && cpu == 0) 166 sunxi_cpu0_hotplug_support_set(true); 167 168 /* assert processor power-on reset */ 169 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); 170 reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu); 171 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); 172 173 if (is_a83t) { 174 /* assert cpu power-on reset */ 175 reg = readl(r_cpucfg_base + 176 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); 177 reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu)); 178 writel(reg, r_cpucfg_base + 179 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); 180 udelay(10); 181 } 182 183 /* Cortex-A7: hold L1 reset disable signal low */ 184 if (!sunxi_core_is_cortex_a15(cpu, cluster)) { 185 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); 186 reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(cpu); 187 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); 188 } 189 190 /* assert processor related resets */ 191 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 192 reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST(cpu); 193 194 /* 195 * Allwinner code also asserts resets for NEON on A15. According 196 * to ARM manuals, asserting power-on reset is sufficient. 197 */ 198 if (!sunxi_core_is_cortex_a15(cpu, cluster)) 199 reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST(cpu); 200 201 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 202 203 /* open power switch */ 204 sunxi_cpu_power_switch_set(cpu, cluster, true); 205 206 /* Handle A83T bit swap */ 207 if (is_a83t) { 208 if (cpu == 0) 209 cpu = 4; 210 } 211 212 /* clear processor power gate */ 213 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); 214 reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu); 215 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); 216 udelay(20); 217 218 /* Handle A83T bit swap */ 219 if (is_a83t) { 220 if (cpu == 4) 221 cpu = 0; 222 } 223 224 /* de-assert processor power-on reset */ 225 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); 226 reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu); 227 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); 228 229 if (is_a83t) { 230 reg = readl(r_cpucfg_base + 231 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); 232 reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu); 233 writel(reg, r_cpucfg_base + 234 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); 235 udelay(10); 236 } 237 238 /* de-assert all processor resets */ 239 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 240 reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu); 241 reg |= CPUCFG_CX_RST_CTRL_CORE_RST(cpu); 242 if (!sunxi_core_is_cortex_a15(cpu, cluster)) 243 reg |= CPUCFG_CX_RST_CTRL_ETM_RST(cpu); 244 else 245 reg |= CPUCFG_CX_RST_CTRL_CX_RST(cpu); /* NEON */ 246 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 247 248 return 0; 249 } 250 251 static int sunxi_cluster_powerup(unsigned int cluster) 252 { 253 u32 reg; 254 255 pr_debug("%s: cluster %u\n", __func__, cluster); 256 if (cluster >= SUNXI_NR_CLUSTERS) 257 return -EINVAL; 258 259 /* For A83T, assert cluster cores resets */ 260 if (is_a83t) { 261 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 262 reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL; /* Core Reset */ 263 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 264 udelay(10); 265 } 266 267 /* assert ACINACTM */ 268 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); 269 reg |= CPUCFG_CX_CTRL_REG1_ACINACTM; 270 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); 271 272 /* assert cluster processor power-on resets */ 273 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); 274 reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL; 275 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); 276 277 /* assert cluster cores resets */ 278 if (is_a83t) { 279 reg = readl(r_cpucfg_base + 280 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); 281 reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL; 282 writel(reg, r_cpucfg_base + 283 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); 284 udelay(10); 285 } 286 287 /* assert cluster resets */ 288 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 289 reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST; 290 reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST_ALL; 291 reg &= ~CPUCFG_CX_RST_CTRL_H_RST; 292 reg &= ~CPUCFG_CX_RST_CTRL_L2_RST; 293 294 /* 295 * Allwinner code also asserts resets for NEON on A15. According 296 * to ARM manuals, asserting power-on reset is sufficient. 297 */ 298 if (!sunxi_core_is_cortex_a15(0, cluster)) 299 reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST_ALL; 300 301 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 302 303 /* hold L1/L2 reset disable signals low */ 304 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); 305 if (sunxi_core_is_cortex_a15(0, cluster)) { 306 /* Cortex-A15: hold L2RSTDISABLE low */ 307 reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15; 308 } else { 309 /* Cortex-A7: hold L1RSTDISABLE and L2RSTDISABLE low */ 310 reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL; 311 reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7; 312 } 313 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); 314 315 /* clear cluster power gate */ 316 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); 317 if (is_a83t) 318 reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I; 319 else 320 reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I; 321 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); 322 udelay(20); 323 324 /* de-assert cluster resets */ 325 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 326 reg |= CPUCFG_CX_RST_CTRL_DBG_SOC_RST; 327 reg |= CPUCFG_CX_RST_CTRL_H_RST; 328 reg |= CPUCFG_CX_RST_CTRL_L2_RST; 329 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 330 331 /* de-assert ACINACTM */ 332 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); 333 reg &= ~CPUCFG_CX_CTRL_REG1_ACINACTM; 334 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); 335 336 return 0; 337 } 338 339 /* 340 * This bit is shared between the initial nocache_trampoline call to 341 * enable CCI-400 and proper cluster cache disable before power down. 342 */ 343 static void sunxi_cluster_cache_disable_without_axi(void) 344 { 345 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { 346 /* 347 * On the Cortex-A15 we need to disable 348 * L2 prefetching before flushing the cache. 349 */ 350 asm volatile( 351 "mcr p15, 1, %0, c15, c0, 3\n" 352 "isb\n" 353 "dsb" 354 : : "r" (0x400)); 355 } 356 357 /* Flush all cache levels for this cluster. */ 358 v7_exit_coherency_flush(all); 359 360 /* 361 * Disable cluster-level coherency by masking 362 * incoming snoops and DVM messages: 363 */ 364 cci_disable_port_by_cpu(read_cpuid_mpidr()); 365 } 366 367 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER]; 368 int sunxi_mc_smp_first_comer; 369 370 static DEFINE_SPINLOCK(boot_lock); 371 372 static bool sunxi_mc_smp_cluster_is_down(unsigned int cluster) 373 { 374 int i; 375 376 for (i = 0; i < SUNXI_CPUS_PER_CLUSTER; i++) 377 if (sunxi_mc_smp_cpu_table[cluster][i]) 378 return false; 379 return true; 380 } 381 382 static void sunxi_mc_smp_secondary_init(unsigned int cpu) 383 { 384 /* Clear hotplug support magic flags for cpu0 */ 385 if (cpu == 0) 386 sunxi_cpu0_hotplug_support_set(false); 387 } 388 389 static int sunxi_mc_smp_boot_secondary(unsigned int l_cpu, struct task_struct *idle) 390 { 391 unsigned int mpidr, cpu, cluster; 392 393 mpidr = cpu_logical_map(l_cpu); 394 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 395 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 396 397 if (!cpucfg_base) 398 return -ENODEV; 399 if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER) 400 return -EINVAL; 401 402 spin_lock_irq(&boot_lock); 403 404 if (sunxi_mc_smp_cpu_table[cluster][cpu]) 405 goto out; 406 407 if (sunxi_mc_smp_cluster_is_down(cluster)) { 408 sunxi_mc_smp_first_comer = true; 409 sunxi_cluster_powerup(cluster); 410 } else { 411 sunxi_mc_smp_first_comer = false; 412 } 413 414 /* This is read by incoming CPUs with their cache and MMU disabled */ 415 sync_cache_w(&sunxi_mc_smp_first_comer); 416 sunxi_cpu_powerup(cpu, cluster); 417 418 out: 419 sunxi_mc_smp_cpu_table[cluster][cpu]++; 420 spin_unlock_irq(&boot_lock); 421 422 return 0; 423 } 424 425 #ifdef CONFIG_HOTPLUG_CPU 426 static void sunxi_cluster_cache_disable(void) 427 { 428 unsigned int cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); 429 u32 reg; 430 431 pr_debug("%s: cluster %u\n", __func__, cluster); 432 433 sunxi_cluster_cache_disable_without_axi(); 434 435 /* last man standing, assert ACINACTM */ 436 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); 437 reg |= CPUCFG_CX_CTRL_REG1_ACINACTM; 438 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); 439 } 440 441 static void sunxi_mc_smp_cpu_die(unsigned int l_cpu) 442 { 443 unsigned int mpidr, cpu, cluster; 444 bool last_man; 445 446 mpidr = cpu_logical_map(l_cpu); 447 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 448 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 449 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu); 450 451 spin_lock(&boot_lock); 452 sunxi_mc_smp_cpu_table[cluster][cpu]--; 453 if (sunxi_mc_smp_cpu_table[cluster][cpu] == 1) { 454 /* A power_up request went ahead of us. */ 455 pr_debug("%s: aborting due to a power up request\n", 456 __func__); 457 spin_unlock(&boot_lock); 458 return; 459 } else if (sunxi_mc_smp_cpu_table[cluster][cpu] > 1) { 460 pr_err("Cluster %d CPU%d boots multiple times\n", 461 cluster, cpu); 462 BUG(); 463 } 464 465 last_man = sunxi_mc_smp_cluster_is_down(cluster); 466 spin_unlock(&boot_lock); 467 468 gic_cpu_if_down(0); 469 if (last_man) 470 sunxi_cluster_cache_disable(); 471 else 472 v7_exit_coherency_flush(louis); 473 474 for (;;) 475 wfi(); 476 } 477 478 static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster) 479 { 480 u32 reg; 481 482 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu); 483 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS) 484 return -EINVAL; 485 486 /* gate processor power */ 487 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); 488 reg |= PRCM_PWROFF_GATING_REG_CORE(cpu); 489 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); 490 udelay(20); 491 492 /* close power switch */ 493 sunxi_cpu_power_switch_set(cpu, cluster, false); 494 495 return 0; 496 } 497 498 static int sunxi_cluster_powerdown(unsigned int cluster) 499 { 500 u32 reg; 501 502 pr_debug("%s: cluster %u\n", __func__, cluster); 503 if (cluster >= SUNXI_NR_CLUSTERS) 504 return -EINVAL; 505 506 /* assert cluster resets or system will hang */ 507 pr_debug("%s: assert cluster reset\n", __func__); 508 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 509 reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST; 510 reg &= ~CPUCFG_CX_RST_CTRL_H_RST; 511 reg &= ~CPUCFG_CX_RST_CTRL_L2_RST; 512 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); 513 514 /* gate cluster power */ 515 pr_debug("%s: gate cluster power\n", __func__); 516 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); 517 if (is_a83t) 518 reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I; 519 else 520 reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I; 521 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); 522 udelay(20); 523 524 return 0; 525 } 526 527 static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu) 528 { 529 unsigned int mpidr, cpu, cluster; 530 unsigned int tries, count; 531 int ret = 0; 532 u32 reg; 533 534 mpidr = cpu_logical_map(l_cpu); 535 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 536 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 537 538 /* This should never happen */ 539 if (WARN_ON(cluster >= SUNXI_NR_CLUSTERS || 540 cpu >= SUNXI_CPUS_PER_CLUSTER)) 541 return 0; 542 543 /* wait for CPU core to die and enter WFI */ 544 count = TIMEOUT_USEC / POLL_USEC; 545 spin_lock_irq(&boot_lock); 546 for (tries = 0; tries < count; tries++) { 547 spin_unlock_irq(&boot_lock); 548 usleep_range(POLL_USEC / 2, POLL_USEC); 549 spin_lock_irq(&boot_lock); 550 551 /* 552 * If the user turns off a bunch of cores at the same 553 * time, the kernel might call cpu_kill before some of 554 * them are ready. This is because boot_lock serializes 555 * both cpu_die and cpu_kill callbacks. Either one could 556 * run first. We should wait for cpu_die to complete. 557 */ 558 if (sunxi_mc_smp_cpu_table[cluster][cpu]) 559 continue; 560 561 reg = readl(cpucfg_base + CPUCFG_CX_STATUS(cluster)); 562 if (reg & CPUCFG_CX_STATUS_STANDBYWFI(cpu)) 563 break; 564 } 565 566 if (tries >= count) { 567 ret = ETIMEDOUT; 568 goto out; 569 } 570 571 /* power down CPU core */ 572 sunxi_cpu_powerdown(cpu, cluster); 573 574 if (!sunxi_mc_smp_cluster_is_down(cluster)) 575 goto out; 576 577 /* wait for cluster L2 WFI */ 578 ret = readl_poll_timeout(cpucfg_base + CPUCFG_CX_STATUS(cluster), reg, 579 reg & CPUCFG_CX_STATUS_STANDBYWFIL2, 580 POLL_USEC, TIMEOUT_USEC); 581 if (ret) { 582 /* 583 * Ignore timeout on the cluster. Leaving the cluster on 584 * will not affect system execution, just use a bit more 585 * power. But returning an error here will only confuse 586 * the user as the CPU has already been shutdown. 587 */ 588 ret = 0; 589 goto out; 590 } 591 592 /* Power down cluster */ 593 sunxi_cluster_powerdown(cluster); 594 595 out: 596 spin_unlock_irq(&boot_lock); 597 pr_debug("%s: cluster %u cpu %u powerdown: %d\n", 598 __func__, cluster, cpu, ret); 599 return !ret; 600 } 601 602 static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu) 603 { 604 /* CPU0 hotplug not handled for sun8i-a83t */ 605 if (is_a83t) 606 if (cpu == 0) 607 return false; 608 return true; 609 } 610 #endif 611 612 static const struct smp_operations sunxi_mc_smp_smp_ops __initconst = { 613 .smp_secondary_init = sunxi_mc_smp_secondary_init, 614 .smp_boot_secondary = sunxi_mc_smp_boot_secondary, 615 #ifdef CONFIG_HOTPLUG_CPU 616 .cpu_die = sunxi_mc_smp_cpu_die, 617 .cpu_kill = sunxi_mc_smp_cpu_kill, 618 .cpu_can_disable = sunxi_mc_smp_cpu_can_disable, 619 #endif 620 }; 621 622 static bool __init sunxi_mc_smp_cpu_table_init(void) 623 { 624 unsigned int mpidr, cpu, cluster; 625 626 mpidr = read_cpuid_mpidr(); 627 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); 628 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); 629 630 if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER) { 631 pr_err("%s: boot CPU is out of bounds!\n", __func__); 632 return false; 633 } 634 sunxi_mc_smp_cpu_table[cluster][cpu] = 1; 635 return true; 636 } 637 638 /* 639 * Adapted from arch/arm/common/mc_smp_entry.c 640 * 641 * We need the trampoline code to enable CCI-400 on the first cluster 642 */ 643 typedef typeof(cpu_reset) phys_reset_t; 644 645 static int __init nocache_trampoline(unsigned long __unused) 646 { 647 phys_reset_t phys_reset; 648 649 setup_mm_for_reboot(); 650 sunxi_cluster_cache_disable_without_axi(); 651 652 phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset); 653 phys_reset(__pa_symbol(sunxi_mc_smp_resume), false); 654 BUG(); 655 } 656 657 static int __init sunxi_mc_smp_loopback(void) 658 { 659 int ret; 660 661 /* 662 * We're going to soft-restart the current CPU through the 663 * low-level MCPM code by leveraging the suspend/resume 664 * infrastructure. Let's play it safe by using cpu_pm_enter() 665 * in case the CPU init code path resets the VFP or similar. 666 */ 667 sunxi_mc_smp_first_comer = true; 668 local_irq_disable(); 669 local_fiq_disable(); 670 ret = cpu_pm_enter(); 671 if (!ret) { 672 ret = cpu_suspend(0, nocache_trampoline); 673 cpu_pm_exit(); 674 } 675 local_fiq_enable(); 676 local_irq_enable(); 677 sunxi_mc_smp_first_comer = false; 678 679 return ret; 680 } 681 682 /* 683 * This holds any device nodes that we requested resources for, 684 * so that we may easily release resources in the error path. 685 */ 686 struct sunxi_mc_smp_nodes { 687 struct device_node *prcm_node; 688 struct device_node *cpucfg_node; 689 struct device_node *sram_node; 690 struct device_node *r_cpucfg_node; 691 }; 692 693 /* This structure holds SoC-specific bits tied to an enable-method string. */ 694 struct sunxi_mc_smp_data { 695 const char *enable_method; 696 int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes); 697 bool is_a83t; 698 }; 699 700 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes) 701 { 702 of_node_put(nodes->prcm_node); 703 of_node_put(nodes->cpucfg_node); 704 of_node_put(nodes->sram_node); 705 of_node_put(nodes->r_cpucfg_node); 706 memset(nodes, 0, sizeof(*nodes)); 707 } 708 709 static int __init sun9i_a80_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes) 710 { 711 nodes->prcm_node = of_find_compatible_node(NULL, NULL, 712 "allwinner,sun9i-a80-prcm"); 713 if (!nodes->prcm_node) { 714 pr_err("%s: PRCM not available\n", __func__); 715 return -ENODEV; 716 } 717 718 nodes->cpucfg_node = of_find_compatible_node(NULL, NULL, 719 "allwinner,sun9i-a80-cpucfg"); 720 if (!nodes->cpucfg_node) { 721 pr_err("%s: CPUCFG not available\n", __func__); 722 return -ENODEV; 723 } 724 725 nodes->sram_node = of_find_compatible_node(NULL, NULL, 726 "allwinner,sun9i-a80-smp-sram"); 727 if (!nodes->sram_node) { 728 pr_err("%s: Secure SRAM not available\n", __func__); 729 return -ENODEV; 730 } 731 732 return 0; 733 } 734 735 static int __init sun8i_a83t_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes) 736 { 737 nodes->prcm_node = of_find_compatible_node(NULL, NULL, 738 "allwinner,sun8i-a83t-r-ccu"); 739 if (!nodes->prcm_node) { 740 pr_err("%s: PRCM not available\n", __func__); 741 return -ENODEV; 742 } 743 744 nodes->cpucfg_node = of_find_compatible_node(NULL, NULL, 745 "allwinner,sun8i-a83t-cpucfg"); 746 if (!nodes->cpucfg_node) { 747 pr_err("%s: CPUCFG not available\n", __func__); 748 return -ENODEV; 749 } 750 751 nodes->r_cpucfg_node = of_find_compatible_node(NULL, NULL, 752 "allwinner,sun8i-a83t-r-cpucfg"); 753 if (!nodes->r_cpucfg_node) { 754 pr_err("%s: RCPUCFG not available\n", __func__); 755 return -ENODEV; 756 } 757 758 return 0; 759 } 760 761 static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = { 762 { 763 .enable_method = "allwinner,sun9i-a80-smp", 764 .get_smp_nodes = sun9i_a80_get_smp_nodes, 765 }, 766 { 767 .enable_method = "allwinner,sun8i-a83t-smp", 768 .get_smp_nodes = sun8i_a83t_get_smp_nodes, 769 .is_a83t = true, 770 }, 771 }; 772 773 static int __init sunxi_mc_smp_init(void) 774 { 775 struct sunxi_mc_smp_nodes nodes = { 0 }; 776 struct device_node *node; 777 struct resource res; 778 void __iomem *addr; 779 int i, ret; 780 781 /* 782 * Don't bother checking the "cpus" node, as an enable-method 783 * property in that node is undocumented. 784 */ 785 node = of_cpu_device_node_get(0); 786 if (!node) 787 return -ENODEV; 788 789 /* 790 * We can't actually use the enable-method magic in the kernel. 791 * Our loopback / trampoline code uses the CPU suspend framework, 792 * which requires the identity mapping be available. It would not 793 * yet be available if we used the .init_cpus or .prepare_cpus 794 * callbacks in smp_operations, which we would use if we were to 795 * use CPU_METHOD_OF_DECLARE 796 */ 797 for (i = 0; i < ARRAY_SIZE(sunxi_mc_smp_data); i++) { 798 ret = of_property_match_string(node, "enable-method", 799 sunxi_mc_smp_data[i].enable_method); 800 if (!ret) 801 break; 802 } 803 804 is_a83t = sunxi_mc_smp_data[i].is_a83t; 805 806 of_node_put(node); 807 if (ret) 808 return -ENODEV; 809 810 if (!sunxi_mc_smp_cpu_table_init()) 811 return -EINVAL; 812 813 if (!cci_probed()) { 814 pr_err("%s: CCI-400 not available\n", __func__); 815 return -ENODEV; 816 } 817 818 /* Get needed device tree nodes */ 819 ret = sunxi_mc_smp_data[i].get_smp_nodes(&nodes); 820 if (ret) 821 goto err_put_nodes; 822 823 /* 824 * Unfortunately we can not request the I/O region for the PRCM. 825 * It is shared with the PRCM clock. 826 */ 827 prcm_base = of_iomap(nodes.prcm_node, 0); 828 if (!prcm_base) { 829 pr_err("%s: failed to map PRCM registers\n", __func__); 830 ret = -ENOMEM; 831 goto err_put_nodes; 832 } 833 834 cpucfg_base = of_io_request_and_map(nodes.cpucfg_node, 0, 835 "sunxi-mc-smp"); 836 if (IS_ERR(cpucfg_base)) { 837 ret = PTR_ERR(cpucfg_base); 838 pr_err("%s: failed to map CPUCFG registers: %d\n", 839 __func__, ret); 840 goto err_unmap_prcm; 841 } 842 843 if (is_a83t) { 844 r_cpucfg_base = of_io_request_and_map(nodes.r_cpucfg_node, 845 0, "sunxi-mc-smp"); 846 if (IS_ERR(r_cpucfg_base)) { 847 ret = PTR_ERR(r_cpucfg_base); 848 pr_err("%s: failed to map R-CPUCFG registers\n", 849 __func__); 850 goto err_unmap_release_cpucfg; 851 } 852 } else { 853 sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0, 854 "sunxi-mc-smp"); 855 if (IS_ERR(sram_b_smp_base)) { 856 ret = PTR_ERR(sram_b_smp_base); 857 pr_err("%s: failed to map secure SRAM\n", __func__); 858 goto err_unmap_release_cpucfg; 859 } 860 } 861 862 /* Configure CCI-400 for boot cluster */ 863 ret = sunxi_mc_smp_loopback(); 864 if (ret) { 865 pr_err("%s: failed to configure boot cluster: %d\n", 866 __func__, ret); 867 goto err_unmap_release_sram_rcpucfg; 868 } 869 870 /* We don't need the device nodes anymore */ 871 sunxi_mc_smp_put_nodes(&nodes); 872 873 /* Set the hardware entry point address */ 874 if (is_a83t) 875 addr = r_cpucfg_base + R_CPUCFG_CPU_SOFT_ENTRY_REG; 876 else 877 addr = prcm_base + PRCM_CPU_SOFT_ENTRY_REG; 878 writel(__pa_symbol(sunxi_mc_smp_secondary_startup), addr); 879 880 /* Actually enable multi cluster SMP */ 881 smp_set_ops(&sunxi_mc_smp_smp_ops); 882 883 pr_info("sunxi multi cluster SMP support installed\n"); 884 885 return 0; 886 887 err_unmap_release_sram_rcpucfg: 888 if (is_a83t) { 889 iounmap(r_cpucfg_base); 890 of_address_to_resource(nodes.r_cpucfg_node, 0, &res); 891 } else { 892 iounmap(sram_b_smp_base); 893 of_address_to_resource(nodes.sram_node, 0, &res); 894 } 895 release_mem_region(res.start, resource_size(&res)); 896 err_unmap_release_cpucfg: 897 iounmap(cpucfg_base); 898 of_address_to_resource(nodes.cpucfg_node, 0, &res); 899 release_mem_region(res.start, resource_size(&res)); 900 err_unmap_prcm: 901 iounmap(prcm_base); 902 err_put_nodes: 903 sunxi_mc_smp_put_nodes(&nodes); 904 return ret; 905 } 906 907 early_initcall(sunxi_mc_smp_init); 908