1a7ed099fSArnd Bergmann /* 2a7ed099fSArnd Bergmann * arch/arm/plat-spear/time.c 3a7ed099fSArnd Bergmann * 4a7ed099fSArnd Bergmann * Copyright (C) 2010 ST Microelectronics 59cc23682SViresh Kumar * Shiraz Hashim<shiraz.linux.kernel@gmail.com> 6a7ed099fSArnd Bergmann * 7a7ed099fSArnd Bergmann * This file is licensed under the terms of the GNU General Public 8a7ed099fSArnd Bergmann * License version 2. This program is licensed "as is" without any 9a7ed099fSArnd Bergmann * warranty of any kind, whether express or implied. 10a7ed099fSArnd Bergmann */ 11a7ed099fSArnd Bergmann 12a7ed099fSArnd Bergmann #include <linux/clk.h> 13a7ed099fSArnd Bergmann #include <linux/clockchips.h> 14a7ed099fSArnd Bergmann #include <linux/clocksource.h> 15a7ed099fSArnd Bergmann #include <linux/err.h> 16a7ed099fSArnd Bergmann #include <linux/init.h> 17a7ed099fSArnd Bergmann #include <linux/interrupt.h> 18a7ed099fSArnd Bergmann #include <linux/ioport.h> 19a7ed099fSArnd Bergmann #include <linux/io.h> 20a7ed099fSArnd Bergmann #include <linux/kernel.h> 21a7ed099fSArnd Bergmann #include <linux/of_irq.h> 22a7ed099fSArnd Bergmann #include <linux/of_address.h> 23a7ed099fSArnd Bergmann #include <linux/time.h> 24a7ed099fSArnd Bergmann #include <linux/irq.h> 25a7ed099fSArnd Bergmann #include <asm/mach/time.h> 262b9c613cSArnd Bergmann #include "generic.h" 27a7ed099fSArnd Bergmann 28a7ed099fSArnd Bergmann /* 29a7ed099fSArnd Bergmann * We would use TIMER0 and TIMER1 as clockevent and clocksource. 30a7ed099fSArnd Bergmann * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further 31a7ed099fSArnd Bergmann * they share same functional clock. Any change in one's functional clock will 32a7ed099fSArnd Bergmann * also affect other timer. 33a7ed099fSArnd Bergmann */ 34a7ed099fSArnd Bergmann 35a7ed099fSArnd Bergmann #define CLKEVT 0 /* gpt0, channel0 as clockevent */ 36a7ed099fSArnd Bergmann #define CLKSRC 1 /* gpt0, channel1 as clocksource */ 37a7ed099fSArnd Bergmann 38a7ed099fSArnd Bergmann /* Register offsets, x is channel number */ 39a7ed099fSArnd Bergmann #define CR(x) ((x) * 0x80 + 0x80) 40a7ed099fSArnd Bergmann #define IR(x) ((x) * 0x80 + 0x84) 41a7ed099fSArnd Bergmann #define LOAD(x) ((x) * 0x80 + 0x88) 42a7ed099fSArnd Bergmann #define COUNT(x) ((x) * 0x80 + 0x8C) 43a7ed099fSArnd Bergmann 44a7ed099fSArnd Bergmann /* Reg bit definitions */ 45a7ed099fSArnd Bergmann #define CTRL_INT_ENABLE 0x0100 46a7ed099fSArnd Bergmann #define CTRL_ENABLE 0x0020 47a7ed099fSArnd Bergmann #define CTRL_ONE_SHOT 0x0010 48a7ed099fSArnd Bergmann 49a7ed099fSArnd Bergmann #define CTRL_PRESCALER1 0x0 50a7ed099fSArnd Bergmann #define CTRL_PRESCALER2 0x1 51a7ed099fSArnd Bergmann #define CTRL_PRESCALER4 0x2 52a7ed099fSArnd Bergmann #define CTRL_PRESCALER8 0x3 53a7ed099fSArnd Bergmann #define CTRL_PRESCALER16 0x4 54a7ed099fSArnd Bergmann #define CTRL_PRESCALER32 0x5 55a7ed099fSArnd Bergmann #define CTRL_PRESCALER64 0x6 56a7ed099fSArnd Bergmann #define CTRL_PRESCALER128 0x7 57a7ed099fSArnd Bergmann #define CTRL_PRESCALER256 0x8 58a7ed099fSArnd Bergmann 59a7ed099fSArnd Bergmann #define INT_STATUS 0x1 60a7ed099fSArnd Bergmann 61a7ed099fSArnd Bergmann /* 62a7ed099fSArnd Bergmann * Minimum clocksource/clockevent timer range in seconds 63a7ed099fSArnd Bergmann */ 64a7ed099fSArnd Bergmann #define SPEAR_MIN_RANGE 4 65a7ed099fSArnd Bergmann 66a7ed099fSArnd Bergmann static __iomem void *gpt_base; 67a7ed099fSArnd Bergmann static struct clk *gpt_clk; 68a7ed099fSArnd Bergmann 69a7ed099fSArnd Bergmann static int clockevent_next_event(unsigned long evt, 70a7ed099fSArnd Bergmann struct clock_event_device *clk_event_dev); 71a7ed099fSArnd Bergmann 721be5f692SAlex Elder static void __init spear_clocksource_init(void) 73a7ed099fSArnd Bergmann { 74a7ed099fSArnd Bergmann u32 tick_rate; 75a7ed099fSArnd Bergmann u16 val; 76a7ed099fSArnd Bergmann 77a7ed099fSArnd Bergmann /* program the prescaler (/256)*/ 78a7ed099fSArnd Bergmann writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC)); 79a7ed099fSArnd Bergmann 80a7ed099fSArnd Bergmann /* find out actual clock driving Timer */ 81a7ed099fSArnd Bergmann tick_rate = clk_get_rate(gpt_clk); 82a7ed099fSArnd Bergmann tick_rate >>= CTRL_PRESCALER256; 83a7ed099fSArnd Bergmann 84a7ed099fSArnd Bergmann writew(0xFFFF, gpt_base + LOAD(CLKSRC)); 85a7ed099fSArnd Bergmann 86a7ed099fSArnd Bergmann val = readw(gpt_base + CR(CLKSRC)); 87a7ed099fSArnd Bergmann val &= ~CTRL_ONE_SHOT; /* autoreload mode */ 88a7ed099fSArnd Bergmann val |= CTRL_ENABLE ; 89a7ed099fSArnd Bergmann writew(val, gpt_base + CR(CLKSRC)); 90a7ed099fSArnd Bergmann 91a7ed099fSArnd Bergmann /* register the clocksource */ 92a7ed099fSArnd Bergmann clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate, 93a7ed099fSArnd Bergmann 200, 16, clocksource_mmio_readw_up); 94a7ed099fSArnd Bergmann } 95a7ed099fSArnd Bergmann 967639c0b8SViresh Kumar static inline void timer_shutdown(struct clock_event_device *evt) 977639c0b8SViresh Kumar { 987639c0b8SViresh Kumar u16 val = readw(gpt_base + CR(CLKEVT)); 99a7ed099fSArnd Bergmann 1007639c0b8SViresh Kumar /* stop the timer */ 1017639c0b8SViresh Kumar val &= ~CTRL_ENABLE; 1027639c0b8SViresh Kumar writew(val, gpt_base + CR(CLKEVT)); 1037639c0b8SViresh Kumar } 1047639c0b8SViresh Kumar 1057639c0b8SViresh Kumar static int spear_shutdown(struct clock_event_device *evt) 1067639c0b8SViresh Kumar { 1077639c0b8SViresh Kumar timer_shutdown(evt); 1087639c0b8SViresh Kumar 1097639c0b8SViresh Kumar return 0; 1107639c0b8SViresh Kumar } 1117639c0b8SViresh Kumar 1127639c0b8SViresh Kumar static int spear_set_oneshot(struct clock_event_device *evt) 1137639c0b8SViresh Kumar { 1147639c0b8SViresh Kumar u16 val; 1157639c0b8SViresh Kumar 1167639c0b8SViresh Kumar /* stop the timer */ 1177639c0b8SViresh Kumar timer_shutdown(evt); 1187639c0b8SViresh Kumar 1197639c0b8SViresh Kumar val = readw(gpt_base + CR(CLKEVT)); 1207639c0b8SViresh Kumar val |= CTRL_ONE_SHOT; 1217639c0b8SViresh Kumar writew(val, gpt_base + CR(CLKEVT)); 1227639c0b8SViresh Kumar 1237639c0b8SViresh Kumar return 0; 1247639c0b8SViresh Kumar } 1257639c0b8SViresh Kumar 1267639c0b8SViresh Kumar static int spear_set_periodic(struct clock_event_device *evt) 127a7ed099fSArnd Bergmann { 128a7ed099fSArnd Bergmann u32 period; 129a7ed099fSArnd Bergmann u16 val; 130a7ed099fSArnd Bergmann 131a7ed099fSArnd Bergmann /* stop the timer */ 1327639c0b8SViresh Kumar timer_shutdown(evt); 133a7ed099fSArnd Bergmann 134a7ed099fSArnd Bergmann period = clk_get_rate(gpt_clk) / HZ; 135a7ed099fSArnd Bergmann period >>= CTRL_PRESCALER16; 136a7ed099fSArnd Bergmann writew(period, gpt_base + LOAD(CLKEVT)); 137a7ed099fSArnd Bergmann 138a7ed099fSArnd Bergmann val = readw(gpt_base + CR(CLKEVT)); 139a7ed099fSArnd Bergmann val &= ~CTRL_ONE_SHOT; 140a7ed099fSArnd Bergmann val |= CTRL_ENABLE | CTRL_INT_ENABLE; 141a7ed099fSArnd Bergmann writew(val, gpt_base + CR(CLKEVT)); 142a7ed099fSArnd Bergmann 1437639c0b8SViresh Kumar return 0; 144a7ed099fSArnd Bergmann } 1457639c0b8SViresh Kumar 1467639c0b8SViresh Kumar static struct clock_event_device clkevt = { 1477639c0b8SViresh Kumar .name = "tmr0", 1487639c0b8SViresh Kumar .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 1497639c0b8SViresh Kumar .set_state_shutdown = spear_shutdown, 1507639c0b8SViresh Kumar .set_state_periodic = spear_set_periodic, 1517639c0b8SViresh Kumar .set_state_oneshot = spear_set_oneshot, 1527639c0b8SViresh Kumar .tick_resume = spear_shutdown, 1537639c0b8SViresh Kumar .set_next_event = clockevent_next_event, 1547639c0b8SViresh Kumar .shift = 0, /* to be computed */ 1557639c0b8SViresh Kumar }; 156a7ed099fSArnd Bergmann 157a7ed099fSArnd Bergmann static int clockevent_next_event(unsigned long cycles, 158a7ed099fSArnd Bergmann struct clock_event_device *clk_event_dev) 159a7ed099fSArnd Bergmann { 160a7ed099fSArnd Bergmann u16 val = readw(gpt_base + CR(CLKEVT)); 161a7ed099fSArnd Bergmann 162a7ed099fSArnd Bergmann if (val & CTRL_ENABLE) 163a7ed099fSArnd Bergmann writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT)); 164a7ed099fSArnd Bergmann 165a7ed099fSArnd Bergmann writew(cycles, gpt_base + LOAD(CLKEVT)); 166a7ed099fSArnd Bergmann 167a7ed099fSArnd Bergmann val |= CTRL_ENABLE | CTRL_INT_ENABLE; 168a7ed099fSArnd Bergmann writew(val, gpt_base + CR(CLKEVT)); 169a7ed099fSArnd Bergmann 170a7ed099fSArnd Bergmann return 0; 171a7ed099fSArnd Bergmann } 172a7ed099fSArnd Bergmann 173a7ed099fSArnd Bergmann static irqreturn_t spear_timer_interrupt(int irq, void *dev_id) 174a7ed099fSArnd Bergmann { 175a7ed099fSArnd Bergmann struct clock_event_device *evt = &clkevt; 176a7ed099fSArnd Bergmann 177a7ed099fSArnd Bergmann writew(INT_STATUS, gpt_base + IR(CLKEVT)); 178a7ed099fSArnd Bergmann 179a7ed099fSArnd Bergmann evt->event_handler(evt); 180a7ed099fSArnd Bergmann 181a7ed099fSArnd Bergmann return IRQ_HANDLED; 182a7ed099fSArnd Bergmann } 183a7ed099fSArnd Bergmann 184a7ed099fSArnd Bergmann static void __init spear_clockevent_init(int irq) 185a7ed099fSArnd Bergmann { 186a7ed099fSArnd Bergmann u32 tick_rate; 187a7ed099fSArnd Bergmann 188a7ed099fSArnd Bergmann /* program the prescaler */ 189a7ed099fSArnd Bergmann writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT)); 190a7ed099fSArnd Bergmann 191a7ed099fSArnd Bergmann tick_rate = clk_get_rate(gpt_clk); 192a7ed099fSArnd Bergmann tick_rate >>= CTRL_PRESCALER16; 193a7ed099fSArnd Bergmann 194a7ed099fSArnd Bergmann clkevt.cpumask = cpumask_of(0); 195a7ed099fSArnd Bergmann 196a7ed099fSArnd Bergmann clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0); 197a7ed099fSArnd Bergmann 198c84e4899Safzal mohammed if (request_irq(irq, spear_timer_interrupt, IRQF_TIMER, "timer", NULL)) 199c84e4899Safzal mohammed pr_err("Failed to request irq %d (timer)\n", irq); 200a7ed099fSArnd Bergmann } 201a7ed099fSArnd Bergmann 2020527873bSArnd Bergmann static const struct of_device_id timer_of_match[] __initconst = { 203a7ed099fSArnd Bergmann { .compatible = "st,spear-timer", }, 204a7ed099fSArnd Bergmann { }, 205a7ed099fSArnd Bergmann }; 206a7ed099fSArnd Bergmann 207a7ed099fSArnd Bergmann void __init spear_setup_of_timer(void) 208a7ed099fSArnd Bergmann { 209a7ed099fSArnd Bergmann struct device_node *np; 210a7ed099fSArnd Bergmann int irq, ret; 211a7ed099fSArnd Bergmann 212a7ed099fSArnd Bergmann np = of_find_matching_node(NULL, timer_of_match); 213a7ed099fSArnd Bergmann if (!np) { 214a7ed099fSArnd Bergmann pr_err("%s: No timer passed via DT\n", __func__); 215a7ed099fSArnd Bergmann return; 216a7ed099fSArnd Bergmann } 217a7ed099fSArnd Bergmann 218a7ed099fSArnd Bergmann irq = irq_of_parse_and_map(np, 0); 219a7ed099fSArnd Bergmann if (!irq) { 220a7ed099fSArnd Bergmann pr_err("%s: No irq passed for timer via DT\n", __func__); 221*2c629dd2SLiang He goto err_put_np; 222a7ed099fSArnd Bergmann } 223a7ed099fSArnd Bergmann 224a7ed099fSArnd Bergmann gpt_base = of_iomap(np, 0); 225a7ed099fSArnd Bergmann if (!gpt_base) { 226a7ed099fSArnd Bergmann pr_err("%s: of iomap failed\n", __func__); 227*2c629dd2SLiang He goto err_put_np; 228a7ed099fSArnd Bergmann } 229a7ed099fSArnd Bergmann 230a7ed099fSArnd Bergmann gpt_clk = clk_get_sys("gpt0", NULL); 231ce340961SChristophe JAILLET if (IS_ERR(gpt_clk)) { 232a7ed099fSArnd Bergmann pr_err("%s:couldn't get clk for gpt\n", __func__); 233a7ed099fSArnd Bergmann goto err_iomap; 234a7ed099fSArnd Bergmann } 235a7ed099fSArnd Bergmann 236a7ed099fSArnd Bergmann ret = clk_prepare_enable(gpt_clk); 237a7ed099fSArnd Bergmann if (ret < 0) { 238a7ed099fSArnd Bergmann pr_err("%s:couldn't prepare-enable gpt clock\n", __func__); 239a7ed099fSArnd Bergmann goto err_prepare_enable_clk; 240a7ed099fSArnd Bergmann } 241a7ed099fSArnd Bergmann 242*2c629dd2SLiang He of_node_put(np); 243*2c629dd2SLiang He 244a7ed099fSArnd Bergmann spear_clockevent_init(irq); 245a7ed099fSArnd Bergmann spear_clocksource_init(); 246a7ed099fSArnd Bergmann 247a7ed099fSArnd Bergmann return; 248a7ed099fSArnd Bergmann 249a7ed099fSArnd Bergmann err_prepare_enable_clk: 250a7ed099fSArnd Bergmann clk_put(gpt_clk); 251a7ed099fSArnd Bergmann err_iomap: 252a7ed099fSArnd Bergmann iounmap(gpt_base); 253*2c629dd2SLiang He err_put_np: 254*2c629dd2SLiang He of_node_put(np); 255a7ed099fSArnd Bergmann } 256