1 /* 2 * arch/arm/mach-spear13xx/spear13xx.c 3 * 4 * SPEAr13XX machines common source file 5 * 6 * Copyright (C) 2012 ST Microelectronics 7 * Viresh Kumar <vireshk@kernel.org> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #define pr_fmt(fmt) "SPEAr13xx: " fmt 15 16 #include <linux/amba/pl022.h> 17 #include <linux/clk.h> 18 #include <linux/clk/spear.h> 19 #include <linux/clocksource.h> 20 #include <linux/err.h> 21 #include <linux/of.h> 22 #include <asm/hardware/cache-l2x0.h> 23 #include <asm/mach/map.h> 24 #include "spear.h" 25 #include "generic.h" 26 27 void __init spear13xx_l2x0_init(void) 28 { 29 /* 30 * 512KB (64KB/way), 8-way associativity, parity supported 31 * 32 * FIXME: 9th bit, of Auxiliary Controller register must be set 33 * for some spear13xx devices for stable L2 operation. 34 * 35 * Enable Early BRESP, L2 prefetch for Instruction and Data, 36 * write alloc and 'Full line of zero' options 37 * 38 */ 39 if (!IS_ENABLED(CONFIG_CACHE_L2X0)) 40 return; 41 42 writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL); 43 44 /* 45 * Program following latencies in order to make 46 * SPEAr1340 work at 600 MHz 47 */ 48 writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL); 49 writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL); 50 l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff); 51 } 52 53 /* 54 * Following will create 16MB static virtual/physical mappings 55 * PHYSICAL VIRTUAL 56 * 0xB3000000 0xF9000000 57 * 0xE0000000 0xFD000000 58 * 0xEC000000 0xFC000000 59 * 0xED000000 0xFB000000 60 */ 61 static struct map_desc spear13xx_io_desc[] __initdata = { 62 { 63 .virtual = (unsigned long)VA_PERIP_GRP2_BASE, 64 .pfn = __phys_to_pfn(PERIP_GRP2_BASE), 65 .length = SZ_16M, 66 .type = MT_DEVICE 67 }, { 68 .virtual = (unsigned long)VA_PERIP_GRP1_BASE, 69 .pfn = __phys_to_pfn(PERIP_GRP1_BASE), 70 .length = SZ_16M, 71 .type = MT_DEVICE 72 }, { 73 .virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE, 74 .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE), 75 .length = SZ_16M, 76 .type = MT_DEVICE 77 }, { 78 .virtual = (unsigned long)VA_L2CC_BASE, 79 .pfn = __phys_to_pfn(L2CC_BASE), 80 .length = SZ_4K, 81 .type = MT_DEVICE 82 }, 83 }; 84 85 /* This will create static memory mapping for selected devices */ 86 void __init spear13xx_map_io(void) 87 { 88 iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc)); 89 } 90 91 static void __init spear13xx_clk_init(void) 92 { 93 if (of_machine_is_compatible("st,spear1310")) 94 spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE); 95 else if (of_machine_is_compatible("st,spear1340")) 96 spear1340_clk_init(VA_MISC_BASE); 97 else 98 pr_err("%s: Unknown machine\n", __func__); 99 } 100 101 void __init spear13xx_timer_init(void) 102 { 103 char pclk_name[] = "osc_24m_clk"; 104 struct clk *gpt_clk, *pclk; 105 106 spear13xx_clk_init(); 107 108 /* get the system timer clock */ 109 gpt_clk = clk_get_sys("gpt0", NULL); 110 if (IS_ERR(gpt_clk)) { 111 pr_err("%s:couldn't get clk for gpt\n", __func__); 112 BUG(); 113 } 114 115 /* get the suitable parent clock for timer*/ 116 pclk = clk_get(NULL, pclk_name); 117 if (IS_ERR(pclk)) { 118 pr_err("%s:couldn't get %s as parent for gpt\n", __func__, 119 pclk_name); 120 BUG(); 121 } 122 123 clk_set_parent(gpt_clk, pclk); 124 clk_put(gpt_clk); 125 clk_put(pclk); 126 127 spear_setup_of_timer(); 128 timer_probe(); 129 } 130