1 /* 2 * arch/arm/mach-spear13xx/platsmp.c 3 * 4 * based upon linux/arch/arm/mach-realview/platsmp.c 5 * 6 * Copyright (C) 2012 ST Microelectronics Ltd. 7 * Shiraz Hashim <shiraz.linux.kernel@gmail.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/delay.h> 15 #include <linux/jiffies.h> 16 #include <linux/io.h> 17 #include <linux/smp.h> 18 #include <asm/cacheflush.h> 19 #include <asm/smp_scu.h> 20 #include <mach/spear.h> 21 #include "generic.h" 22 23 /* 24 * Write pen_release in a way that is guaranteed to be visible to all 25 * observers, irrespective of whether they're taking part in coherency 26 * or not. This is necessary for the hotplug code to work reliably. 27 */ 28 static void write_pen_release(int val) 29 { 30 pen_release = val; 31 smp_wmb(); 32 sync_cache_w(&pen_release); 33 } 34 35 static DEFINE_SPINLOCK(boot_lock); 36 37 static void __iomem *scu_base = IOMEM(VA_SCU_BASE); 38 39 static void spear13xx_secondary_init(unsigned int cpu) 40 { 41 /* 42 * let the primary processor know we're out of the 43 * pen, then head off into the C entry point 44 */ 45 write_pen_release(-1); 46 47 /* 48 * Synchronise with the boot thread. 49 */ 50 spin_lock(&boot_lock); 51 spin_unlock(&boot_lock); 52 } 53 54 static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle) 55 { 56 unsigned long timeout; 57 58 /* 59 * set synchronisation state between this boot processor 60 * and the secondary one 61 */ 62 spin_lock(&boot_lock); 63 64 /* 65 * The secondary processor is waiting to be released from 66 * the holding pen - release it, then wait for it to flag 67 * that it has been released by resetting pen_release. 68 * 69 * Note that "pen_release" is the hardware CPU ID, whereas 70 * "cpu" is Linux's internal ID. 71 */ 72 write_pen_release(cpu); 73 74 timeout = jiffies + (1 * HZ); 75 while (time_before(jiffies, timeout)) { 76 smp_rmb(); 77 if (pen_release == -1) 78 break; 79 80 udelay(10); 81 } 82 83 /* 84 * now the secondary core is starting up let it run its 85 * calibrations, then wait for it to finish 86 */ 87 spin_unlock(&boot_lock); 88 89 return pen_release != -1 ? -ENOSYS : 0; 90 } 91 92 /* 93 * Initialise the CPU possible map early - this describes the CPUs 94 * which may be present or become present in the system. 95 */ 96 static void __init spear13xx_smp_init_cpus(void) 97 { 98 unsigned int i, ncores = scu_get_core_count(scu_base); 99 100 if (ncores > nr_cpu_ids) { 101 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", 102 ncores, nr_cpu_ids); 103 ncores = nr_cpu_ids; 104 } 105 106 for (i = 0; i < ncores; i++) 107 set_cpu_possible(i, true); 108 } 109 110 static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus) 111 { 112 113 scu_enable(scu_base); 114 115 /* 116 * Write the address of secondary startup into the system-wide location 117 * (presently it is in SRAM). The BootMonitor waits until it receives a 118 * soft interrupt, and then the secondary CPU branches to this address. 119 */ 120 __raw_writel(virt_to_phys(spear13xx_secondary_startup), SYS_LOCATION); 121 } 122 123 const struct smp_operations spear13xx_smp_ops __initconst = { 124 .smp_init_cpus = spear13xx_smp_init_cpus, 125 .smp_prepare_cpus = spear13xx_smp_prepare_cpus, 126 .smp_secondary_init = spear13xx_secondary_init, 127 .smp_boot_secondary = spear13xx_boot_secondary, 128 #ifdef CONFIG_HOTPLUG_CPU 129 .cpu_die = spear13xx_cpu_die, 130 #endif 131 }; 132