1 /* 2 * SMP support for R-Mobile / SH-Mobile - sh73a0 portion 3 * 4 * Copyright (C) 2010 Magnus Damm 5 * Copyright (C) 2010 Takashi Yoshii 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/smp.h> 23 #include <linux/spinlock.h> 24 #include <linux/io.h> 25 #include <mach/common.h> 26 #include <asm/smp_plat.h> 27 #include <asm/smp_scu.h> 28 #include <asm/smp_twd.h> 29 #include <asm/hardware/gic.h> 30 31 #define WUPCR IOMEM(0xe6151010) 32 #define SRESCR IOMEM(0xe6151018) 33 #define PSTR IOMEM(0xe6151040) 34 #define SBAR IOMEM(0xe6180020) 35 #define APARMBAREA IOMEM(0xe6f10020) 36 37 static void __iomem *scu_base_addr(void) 38 { 39 return (void __iomem *)0xf0000000; 40 } 41 42 static DEFINE_SPINLOCK(scu_lock); 43 static unsigned long tmp; 44 45 #ifdef CONFIG_HAVE_ARM_TWD 46 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); 47 void __init sh73a0_register_twd(void) 48 { 49 twd_local_timer_register(&twd_local_timer); 50 } 51 #endif 52 53 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) 54 { 55 void __iomem *scu_base = scu_base_addr(); 56 57 spin_lock(&scu_lock); 58 tmp = __raw_readl(scu_base + 8); 59 tmp &= ~clr; 60 tmp |= set; 61 spin_unlock(&scu_lock); 62 63 /* disable cache coherency after releasing the lock */ 64 __raw_writel(tmp, scu_base + 8); 65 } 66 67 unsigned int __init sh73a0_get_core_count(void) 68 { 69 void __iomem *scu_base = scu_base_addr(); 70 71 return scu_get_core_count(scu_base); 72 } 73 74 void __cpuinit sh73a0_secondary_init(unsigned int cpu) 75 { 76 gic_secondary_init(0); 77 } 78 79 int __cpuinit sh73a0_boot_secondary(unsigned int cpu) 80 { 81 cpu = cpu_logical_map(cpu); 82 83 /* enable cache coherency */ 84 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 85 86 if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3) 87 __raw_writel(1 << cpu, WUPCR); /* wake up */ 88 else 89 __raw_writel(1 << cpu, SRESCR); /* reset */ 90 91 return 0; 92 } 93 94 void __init sh73a0_smp_prepare_cpus(void) 95 { 96 int cpu = cpu_logical_map(0); 97 98 scu_enable(scu_base_addr()); 99 100 /* Map the reset vector (in headsmp.S) */ 101 __raw_writel(0, APARMBAREA); /* 4k */ 102 __raw_writel(__pa(shmobile_secondary_vector), SBAR); 103 104 /* enable cache coherency on CPU0 */ 105 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 106 } 107