1 /* 2 * SMP support for R-Mobile / SH-Mobile - r8a7779 portion 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * Copyright (C) 2011 Magnus Damm 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/smp.h> 23 #include <linux/spinlock.h> 24 #include <linux/io.h> 25 #include <linux/delay.h> 26 #include <linux/irqchip/arm-gic.h> 27 #include <mach/common.h> 28 #include <mach/r8a7779.h> 29 #include <asm/smp_plat.h> 30 #include <asm/smp_scu.h> 31 #include <asm/smp_twd.h> 32 33 #define AVECR IOMEM(0xfe700040) 34 35 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { 36 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ 37 .chan_bit = 1, /* ARM1 */ 38 .isr_bit = 1, /* ARM1 */ 39 }; 40 41 static struct r8a7779_pm_ch r8a7779_ch_cpu2 = { 42 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ 43 .chan_bit = 2, /* ARM2 */ 44 .isr_bit = 2, /* ARM2 */ 45 }; 46 47 static struct r8a7779_pm_ch r8a7779_ch_cpu3 = { 48 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ 49 .chan_bit = 3, /* ARM3 */ 50 .isr_bit = 3, /* ARM3 */ 51 }; 52 53 static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = { 54 [1] = &r8a7779_ch_cpu1, 55 [2] = &r8a7779_ch_cpu2, 56 [3] = &r8a7779_ch_cpu3, 57 }; 58 59 static void __iomem *scu_base_addr(void) 60 { 61 return (void __iomem *)0xf0000000; 62 } 63 64 static DEFINE_SPINLOCK(scu_lock); 65 static unsigned long tmp; 66 67 #ifdef CONFIG_HAVE_ARM_TWD 68 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); 69 70 void __init r8a7779_register_twd(void) 71 { 72 twd_local_timer_register(&twd_local_timer); 73 } 74 #endif 75 76 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) 77 { 78 void __iomem *scu_base = scu_base_addr(); 79 80 spin_lock(&scu_lock); 81 tmp = __raw_readl(scu_base + 8); 82 tmp &= ~clr; 83 tmp |= set; 84 spin_unlock(&scu_lock); 85 86 /* disable cache coherency after releasing the lock */ 87 __raw_writel(tmp, scu_base + 8); 88 } 89 90 static unsigned int __init r8a7779_get_core_count(void) 91 { 92 void __iomem *scu_base = scu_base_addr(); 93 94 return scu_get_core_count(scu_base); 95 } 96 97 static int r8a7779_platform_cpu_kill(unsigned int cpu) 98 { 99 struct r8a7779_pm_ch *ch = NULL; 100 int ret = -EIO; 101 102 cpu = cpu_logical_map(cpu); 103 104 /* disable cache coherency */ 105 modify_scu_cpu_psr(3 << (cpu * 8), 0); 106 107 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) 108 ch = r8a7779_ch_cpu[cpu]; 109 110 if (ch) 111 ret = r8a7779_sysc_power_down(ch); 112 113 return ret ? ret : 1; 114 } 115 116 static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu) 117 { 118 int k; 119 120 /* this function is running on another CPU than the offline target, 121 * here we need wait for shutdown code in platform_cpu_die() to 122 * finish before asking SoC-specific code to power off the CPU core. 123 */ 124 for (k = 0; k < 1000; k++) { 125 if (shmobile_cpu_is_dead(cpu)) 126 return r8a7779_platform_cpu_kill(cpu); 127 128 mdelay(1); 129 } 130 131 return 0; 132 } 133 134 135 static void __cpuinit r8a7779_secondary_init(unsigned int cpu) 136 { 137 gic_secondary_init(0); 138 } 139 140 static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) 141 { 142 struct r8a7779_pm_ch *ch = NULL; 143 int ret = -EIO; 144 145 cpu = cpu_logical_map(cpu); 146 147 /* enable cache coherency */ 148 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 149 150 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) 151 ch = r8a7779_ch_cpu[cpu]; 152 153 if (ch) 154 ret = r8a7779_sysc_power_up(ch); 155 156 return ret; 157 } 158 159 static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) 160 { 161 int cpu = cpu_logical_map(0); 162 163 scu_enable(scu_base_addr()); 164 165 /* Map the reset vector (in headsmp.S) */ 166 __raw_writel(__pa(shmobile_secondary_vector), AVECR); 167 168 /* enable cache coherency on CPU0 */ 169 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 170 171 r8a7779_pm_init(); 172 173 /* power off secondary CPUs */ 174 r8a7779_platform_cpu_kill(1); 175 r8a7779_platform_cpu_kill(2); 176 r8a7779_platform_cpu_kill(3); 177 } 178 179 static void __init r8a7779_smp_init_cpus(void) 180 { 181 unsigned int ncores = r8a7779_get_core_count(); 182 183 shmobile_smp_init_cpus(ncores); 184 } 185 186 struct smp_operations r8a7779_smp_ops __initdata = { 187 .smp_init_cpus = r8a7779_smp_init_cpus, 188 .smp_prepare_cpus = r8a7779_smp_prepare_cpus, 189 .smp_secondary_init = r8a7779_secondary_init, 190 .smp_boot_secondary = r8a7779_boot_secondary, 191 #ifdef CONFIG_HOTPLUG_CPU 192 .cpu_kill = r8a7779_cpu_kill, 193 .cpu_die = shmobile_cpu_die, 194 .cpu_disable = shmobile_cpu_disable, 195 #endif 196 }; 197