1 /* 2 * sh73a0 processor support 3 * 4 * Copyright (C) 2010 Takashi Yoshii 5 * Copyright (C) 2010 Magnus Damm 6 * Copyright (C) 2008 Yoshihiro Shimoda 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/irqchip.h> 26 #include <linux/platform_device.h> 27 #include <linux/of_platform.h> 28 #include <linux/delay.h> 29 #include <linux/input.h> 30 #include <linux/io.h> 31 #include <linux/serial_sci.h> 32 #include <linux/sh_dma.h> 33 #include <linux/sh_intc.h> 34 #include <linux/sh_timer.h> 35 #include <linux/platform_data/sh_ipmmu.h> 36 #include <mach/dma-register.h> 37 #include <mach/hardware.h> 38 #include <mach/irqs.h> 39 #include <mach/sh73a0.h> 40 #include <mach/common.h> 41 #include <asm/mach-types.h> 42 #include <asm/mach/map.h> 43 #include <asm/mach/arch.h> 44 #include <asm/mach/time.h> 45 46 static struct map_desc sh73a0_io_desc[] __initdata = { 47 /* create a 1:1 entity map for 0xe6xxxxxx 48 * used by CPGA, INTC and PFC. 49 */ 50 { 51 .virtual = 0xe6000000, 52 .pfn = __phys_to_pfn(0xe6000000), 53 .length = 256 << 20, 54 .type = MT_DEVICE_NONSHARED 55 }, 56 }; 57 58 void __init sh73a0_map_io(void) 59 { 60 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); 61 } 62 63 static struct resource sh73a0_pfc_resources[] = { 64 [0] = { 65 .start = 0xe6050000, 66 .end = 0xe6057fff, 67 .flags = IORESOURCE_MEM, 68 }, 69 [1] = { 70 .start = 0xe605801c, 71 .end = 0xe6058027, 72 .flags = IORESOURCE_MEM, 73 } 74 }; 75 76 static struct platform_device sh73a0_pfc_device = { 77 .name = "pfc-sh73a0", 78 .id = -1, 79 .resource = sh73a0_pfc_resources, 80 .num_resources = ARRAY_SIZE(sh73a0_pfc_resources), 81 }; 82 83 void __init sh73a0_pinmux_init(void) 84 { 85 platform_device_register(&sh73a0_pfc_device); 86 } 87 88 static struct plat_sci_port scif0_platform_data = { 89 .mapbase = 0xe6c40000, 90 .flags = UPF_BOOT_AUTOCONF, 91 .scscr = SCSCR_RE | SCSCR_TE, 92 .scbrr_algo_id = SCBRR_ALGO_4, 93 .type = PORT_SCIFA, 94 .irqs = { gic_spi(72), gic_spi(72), 95 gic_spi(72), gic_spi(72) }, 96 }; 97 98 static struct platform_device scif0_device = { 99 .name = "sh-sci", 100 .id = 0, 101 .dev = { 102 .platform_data = &scif0_platform_data, 103 }, 104 }; 105 106 static struct plat_sci_port scif1_platform_data = { 107 .mapbase = 0xe6c50000, 108 .flags = UPF_BOOT_AUTOCONF, 109 .scscr = SCSCR_RE | SCSCR_TE, 110 .scbrr_algo_id = SCBRR_ALGO_4, 111 .type = PORT_SCIFA, 112 .irqs = { gic_spi(73), gic_spi(73), 113 gic_spi(73), gic_spi(73) }, 114 }; 115 116 static struct platform_device scif1_device = { 117 .name = "sh-sci", 118 .id = 1, 119 .dev = { 120 .platform_data = &scif1_platform_data, 121 }, 122 }; 123 124 static struct plat_sci_port scif2_platform_data = { 125 .mapbase = 0xe6c60000, 126 .flags = UPF_BOOT_AUTOCONF, 127 .scscr = SCSCR_RE | SCSCR_TE, 128 .scbrr_algo_id = SCBRR_ALGO_4, 129 .type = PORT_SCIFA, 130 .irqs = { gic_spi(74), gic_spi(74), 131 gic_spi(74), gic_spi(74) }, 132 }; 133 134 static struct platform_device scif2_device = { 135 .name = "sh-sci", 136 .id = 2, 137 .dev = { 138 .platform_data = &scif2_platform_data, 139 }, 140 }; 141 142 static struct plat_sci_port scif3_platform_data = { 143 .mapbase = 0xe6c70000, 144 .flags = UPF_BOOT_AUTOCONF, 145 .scscr = SCSCR_RE | SCSCR_TE, 146 .scbrr_algo_id = SCBRR_ALGO_4, 147 .type = PORT_SCIFA, 148 .irqs = { gic_spi(75), gic_spi(75), 149 gic_spi(75), gic_spi(75) }, 150 }; 151 152 static struct platform_device scif3_device = { 153 .name = "sh-sci", 154 .id = 3, 155 .dev = { 156 .platform_data = &scif3_platform_data, 157 }, 158 }; 159 160 static struct plat_sci_port scif4_platform_data = { 161 .mapbase = 0xe6c80000, 162 .flags = UPF_BOOT_AUTOCONF, 163 .scscr = SCSCR_RE | SCSCR_TE, 164 .scbrr_algo_id = SCBRR_ALGO_4, 165 .type = PORT_SCIFA, 166 .irqs = { gic_spi(78), gic_spi(78), 167 gic_spi(78), gic_spi(78) }, 168 }; 169 170 static struct platform_device scif4_device = { 171 .name = "sh-sci", 172 .id = 4, 173 .dev = { 174 .platform_data = &scif4_platform_data, 175 }, 176 }; 177 178 static struct plat_sci_port scif5_platform_data = { 179 .mapbase = 0xe6cb0000, 180 .flags = UPF_BOOT_AUTOCONF, 181 .scscr = SCSCR_RE | SCSCR_TE, 182 .scbrr_algo_id = SCBRR_ALGO_4, 183 .type = PORT_SCIFA, 184 .irqs = { gic_spi(79), gic_spi(79), 185 gic_spi(79), gic_spi(79) }, 186 }; 187 188 static struct platform_device scif5_device = { 189 .name = "sh-sci", 190 .id = 5, 191 .dev = { 192 .platform_data = &scif5_platform_data, 193 }, 194 }; 195 196 static struct plat_sci_port scif6_platform_data = { 197 .mapbase = 0xe6cc0000, 198 .flags = UPF_BOOT_AUTOCONF, 199 .scscr = SCSCR_RE | SCSCR_TE, 200 .scbrr_algo_id = SCBRR_ALGO_4, 201 .type = PORT_SCIFA, 202 .irqs = { gic_spi(156), gic_spi(156), 203 gic_spi(156), gic_spi(156) }, 204 }; 205 206 static struct platform_device scif6_device = { 207 .name = "sh-sci", 208 .id = 6, 209 .dev = { 210 .platform_data = &scif6_platform_data, 211 }, 212 }; 213 214 static struct plat_sci_port scif7_platform_data = { 215 .mapbase = 0xe6cd0000, 216 .flags = UPF_BOOT_AUTOCONF, 217 .scscr = SCSCR_RE | SCSCR_TE, 218 .scbrr_algo_id = SCBRR_ALGO_4, 219 .type = PORT_SCIFA, 220 .irqs = { gic_spi(143), gic_spi(143), 221 gic_spi(143), gic_spi(143) }, 222 }; 223 224 static struct platform_device scif7_device = { 225 .name = "sh-sci", 226 .id = 7, 227 .dev = { 228 .platform_data = &scif7_platform_data, 229 }, 230 }; 231 232 static struct plat_sci_port scif8_platform_data = { 233 .mapbase = 0xe6c30000, 234 .flags = UPF_BOOT_AUTOCONF, 235 .scscr = SCSCR_RE | SCSCR_TE, 236 .scbrr_algo_id = SCBRR_ALGO_4, 237 .type = PORT_SCIFB, 238 .irqs = { gic_spi(80), gic_spi(80), 239 gic_spi(80), gic_spi(80) }, 240 }; 241 242 static struct platform_device scif8_device = { 243 .name = "sh-sci", 244 .id = 8, 245 .dev = { 246 .platform_data = &scif8_platform_data, 247 }, 248 }; 249 250 static struct sh_timer_config cmt10_platform_data = { 251 .name = "CMT10", 252 .channel_offset = 0x10, 253 .timer_bit = 0, 254 .clockevent_rating = 125, 255 .clocksource_rating = 125, 256 }; 257 258 static struct resource cmt10_resources[] = { 259 [0] = { 260 .name = "CMT10", 261 .start = 0xe6138010, 262 .end = 0xe613801b, 263 .flags = IORESOURCE_MEM, 264 }, 265 [1] = { 266 .start = gic_spi(65), 267 .flags = IORESOURCE_IRQ, 268 }, 269 }; 270 271 static struct platform_device cmt10_device = { 272 .name = "sh_cmt", 273 .id = 10, 274 .dev = { 275 .platform_data = &cmt10_platform_data, 276 }, 277 .resource = cmt10_resources, 278 .num_resources = ARRAY_SIZE(cmt10_resources), 279 }; 280 281 /* TMU */ 282 static struct sh_timer_config tmu00_platform_data = { 283 .name = "TMU00", 284 .channel_offset = 0x4, 285 .timer_bit = 0, 286 .clockevent_rating = 200, 287 }; 288 289 static struct resource tmu00_resources[] = { 290 [0] = { 291 .name = "TMU00", 292 .start = 0xfff60008, 293 .end = 0xfff60013, 294 .flags = IORESOURCE_MEM, 295 }, 296 [1] = { 297 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ 298 .flags = IORESOURCE_IRQ, 299 }, 300 }; 301 302 static struct platform_device tmu00_device = { 303 .name = "sh_tmu", 304 .id = 0, 305 .dev = { 306 .platform_data = &tmu00_platform_data, 307 }, 308 .resource = tmu00_resources, 309 .num_resources = ARRAY_SIZE(tmu00_resources), 310 }; 311 312 static struct sh_timer_config tmu01_platform_data = { 313 .name = "TMU01", 314 .channel_offset = 0x10, 315 .timer_bit = 1, 316 .clocksource_rating = 200, 317 }; 318 319 static struct resource tmu01_resources[] = { 320 [0] = { 321 .name = "TMU01", 322 .start = 0xfff60014, 323 .end = 0xfff6001f, 324 .flags = IORESOURCE_MEM, 325 }, 326 [1] = { 327 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ 328 .flags = IORESOURCE_IRQ, 329 }, 330 }; 331 332 static struct platform_device tmu01_device = { 333 .name = "sh_tmu", 334 .id = 1, 335 .dev = { 336 .platform_data = &tmu01_platform_data, 337 }, 338 .resource = tmu01_resources, 339 .num_resources = ARRAY_SIZE(tmu01_resources), 340 }; 341 342 static struct resource i2c0_resources[] = { 343 [0] = { 344 .name = "IIC0", 345 .start = 0xe6820000, 346 .end = 0xe6820425 - 1, 347 .flags = IORESOURCE_MEM, 348 }, 349 [1] = { 350 .start = gic_spi(167), 351 .end = gic_spi(170), 352 .flags = IORESOURCE_IRQ, 353 }, 354 }; 355 356 static struct resource i2c1_resources[] = { 357 [0] = { 358 .name = "IIC1", 359 .start = 0xe6822000, 360 .end = 0xe6822425 - 1, 361 .flags = IORESOURCE_MEM, 362 }, 363 [1] = { 364 .start = gic_spi(51), 365 .end = gic_spi(54), 366 .flags = IORESOURCE_IRQ, 367 }, 368 }; 369 370 static struct resource i2c2_resources[] = { 371 [0] = { 372 .name = "IIC2", 373 .start = 0xe6824000, 374 .end = 0xe6824425 - 1, 375 .flags = IORESOURCE_MEM, 376 }, 377 [1] = { 378 .start = gic_spi(171), 379 .end = gic_spi(174), 380 .flags = IORESOURCE_IRQ, 381 }, 382 }; 383 384 static struct resource i2c3_resources[] = { 385 [0] = { 386 .name = "IIC3", 387 .start = 0xe6826000, 388 .end = 0xe6826425 - 1, 389 .flags = IORESOURCE_MEM, 390 }, 391 [1] = { 392 .start = gic_spi(183), 393 .end = gic_spi(186), 394 .flags = IORESOURCE_IRQ, 395 }, 396 }; 397 398 static struct resource i2c4_resources[] = { 399 [0] = { 400 .name = "IIC4", 401 .start = 0xe6828000, 402 .end = 0xe6828425 - 1, 403 .flags = IORESOURCE_MEM, 404 }, 405 [1] = { 406 .start = gic_spi(187), 407 .end = gic_spi(190), 408 .flags = IORESOURCE_IRQ, 409 }, 410 }; 411 412 static struct platform_device i2c0_device = { 413 .name = "i2c-sh_mobile", 414 .id = 0, 415 .resource = i2c0_resources, 416 .num_resources = ARRAY_SIZE(i2c0_resources), 417 }; 418 419 static struct platform_device i2c1_device = { 420 .name = "i2c-sh_mobile", 421 .id = 1, 422 .resource = i2c1_resources, 423 .num_resources = ARRAY_SIZE(i2c1_resources), 424 }; 425 426 static struct platform_device i2c2_device = { 427 .name = "i2c-sh_mobile", 428 .id = 2, 429 .resource = i2c2_resources, 430 .num_resources = ARRAY_SIZE(i2c2_resources), 431 }; 432 433 static struct platform_device i2c3_device = { 434 .name = "i2c-sh_mobile", 435 .id = 3, 436 .resource = i2c3_resources, 437 .num_resources = ARRAY_SIZE(i2c3_resources), 438 }; 439 440 static struct platform_device i2c4_device = { 441 .name = "i2c-sh_mobile", 442 .id = 4, 443 .resource = i2c4_resources, 444 .num_resources = ARRAY_SIZE(i2c4_resources), 445 }; 446 447 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { 448 { 449 .slave_id = SHDMA_SLAVE_SCIF0_TX, 450 .addr = 0xe6c40020, 451 .chcr = CHCR_TX(XMIT_SZ_8BIT), 452 .mid_rid = 0x21, 453 }, { 454 .slave_id = SHDMA_SLAVE_SCIF0_RX, 455 .addr = 0xe6c40024, 456 .chcr = CHCR_RX(XMIT_SZ_8BIT), 457 .mid_rid = 0x22, 458 }, { 459 .slave_id = SHDMA_SLAVE_SCIF1_TX, 460 .addr = 0xe6c50020, 461 .chcr = CHCR_TX(XMIT_SZ_8BIT), 462 .mid_rid = 0x25, 463 }, { 464 .slave_id = SHDMA_SLAVE_SCIF1_RX, 465 .addr = 0xe6c50024, 466 .chcr = CHCR_RX(XMIT_SZ_8BIT), 467 .mid_rid = 0x26, 468 }, { 469 .slave_id = SHDMA_SLAVE_SCIF2_TX, 470 .addr = 0xe6c60020, 471 .chcr = CHCR_TX(XMIT_SZ_8BIT), 472 .mid_rid = 0x29, 473 }, { 474 .slave_id = SHDMA_SLAVE_SCIF2_RX, 475 .addr = 0xe6c60024, 476 .chcr = CHCR_RX(XMIT_SZ_8BIT), 477 .mid_rid = 0x2a, 478 }, { 479 .slave_id = SHDMA_SLAVE_SCIF3_TX, 480 .addr = 0xe6c70020, 481 .chcr = CHCR_TX(XMIT_SZ_8BIT), 482 .mid_rid = 0x2d, 483 }, { 484 .slave_id = SHDMA_SLAVE_SCIF3_RX, 485 .addr = 0xe6c70024, 486 .chcr = CHCR_RX(XMIT_SZ_8BIT), 487 .mid_rid = 0x2e, 488 }, { 489 .slave_id = SHDMA_SLAVE_SCIF4_TX, 490 .addr = 0xe6c80020, 491 .chcr = CHCR_TX(XMIT_SZ_8BIT), 492 .mid_rid = 0x39, 493 }, { 494 .slave_id = SHDMA_SLAVE_SCIF4_RX, 495 .addr = 0xe6c80024, 496 .chcr = CHCR_RX(XMIT_SZ_8BIT), 497 .mid_rid = 0x3a, 498 }, { 499 .slave_id = SHDMA_SLAVE_SCIF5_TX, 500 .addr = 0xe6cb0020, 501 .chcr = CHCR_TX(XMIT_SZ_8BIT), 502 .mid_rid = 0x35, 503 }, { 504 .slave_id = SHDMA_SLAVE_SCIF5_RX, 505 .addr = 0xe6cb0024, 506 .chcr = CHCR_RX(XMIT_SZ_8BIT), 507 .mid_rid = 0x36, 508 }, { 509 .slave_id = SHDMA_SLAVE_SCIF6_TX, 510 .addr = 0xe6cc0020, 511 .chcr = CHCR_TX(XMIT_SZ_8BIT), 512 .mid_rid = 0x1d, 513 }, { 514 .slave_id = SHDMA_SLAVE_SCIF6_RX, 515 .addr = 0xe6cc0024, 516 .chcr = CHCR_RX(XMIT_SZ_8BIT), 517 .mid_rid = 0x1e, 518 }, { 519 .slave_id = SHDMA_SLAVE_SCIF7_TX, 520 .addr = 0xe6cd0020, 521 .chcr = CHCR_TX(XMIT_SZ_8BIT), 522 .mid_rid = 0x19, 523 }, { 524 .slave_id = SHDMA_SLAVE_SCIF7_RX, 525 .addr = 0xe6cd0024, 526 .chcr = CHCR_RX(XMIT_SZ_8BIT), 527 .mid_rid = 0x1a, 528 }, { 529 .slave_id = SHDMA_SLAVE_SCIF8_TX, 530 .addr = 0xe6c30040, 531 .chcr = CHCR_TX(XMIT_SZ_8BIT), 532 .mid_rid = 0x3d, 533 }, { 534 .slave_id = SHDMA_SLAVE_SCIF8_RX, 535 .addr = 0xe6c30060, 536 .chcr = CHCR_RX(XMIT_SZ_8BIT), 537 .mid_rid = 0x3e, 538 }, { 539 .slave_id = SHDMA_SLAVE_SDHI0_TX, 540 .addr = 0xee100030, 541 .chcr = CHCR_TX(XMIT_SZ_16BIT), 542 .mid_rid = 0xc1, 543 }, { 544 .slave_id = SHDMA_SLAVE_SDHI0_RX, 545 .addr = 0xee100030, 546 .chcr = CHCR_RX(XMIT_SZ_16BIT), 547 .mid_rid = 0xc2, 548 }, { 549 .slave_id = SHDMA_SLAVE_SDHI1_TX, 550 .addr = 0xee120030, 551 .chcr = CHCR_TX(XMIT_SZ_16BIT), 552 .mid_rid = 0xc9, 553 }, { 554 .slave_id = SHDMA_SLAVE_SDHI1_RX, 555 .addr = 0xee120030, 556 .chcr = CHCR_RX(XMIT_SZ_16BIT), 557 .mid_rid = 0xca, 558 }, { 559 .slave_id = SHDMA_SLAVE_SDHI2_TX, 560 .addr = 0xee140030, 561 .chcr = CHCR_TX(XMIT_SZ_16BIT), 562 .mid_rid = 0xcd, 563 }, { 564 .slave_id = SHDMA_SLAVE_SDHI2_RX, 565 .addr = 0xee140030, 566 .chcr = CHCR_RX(XMIT_SZ_16BIT), 567 .mid_rid = 0xce, 568 }, { 569 .slave_id = SHDMA_SLAVE_MMCIF_TX, 570 .addr = 0xe6bd0034, 571 .chcr = CHCR_TX(XMIT_SZ_32BIT), 572 .mid_rid = 0xd1, 573 }, { 574 .slave_id = SHDMA_SLAVE_MMCIF_RX, 575 .addr = 0xe6bd0034, 576 .chcr = CHCR_RX(XMIT_SZ_32BIT), 577 .mid_rid = 0xd2, 578 }, 579 }; 580 581 #define DMAE_CHANNEL(_offset) \ 582 { \ 583 .offset = _offset - 0x20, \ 584 .dmars = _offset - 0x20 + 0x40, \ 585 } 586 587 static const struct sh_dmae_channel sh73a0_dmae_channels[] = { 588 DMAE_CHANNEL(0x8000), 589 DMAE_CHANNEL(0x8080), 590 DMAE_CHANNEL(0x8100), 591 DMAE_CHANNEL(0x8180), 592 DMAE_CHANNEL(0x8200), 593 DMAE_CHANNEL(0x8280), 594 DMAE_CHANNEL(0x8300), 595 DMAE_CHANNEL(0x8380), 596 DMAE_CHANNEL(0x8400), 597 DMAE_CHANNEL(0x8480), 598 DMAE_CHANNEL(0x8500), 599 DMAE_CHANNEL(0x8580), 600 DMAE_CHANNEL(0x8600), 601 DMAE_CHANNEL(0x8680), 602 DMAE_CHANNEL(0x8700), 603 DMAE_CHANNEL(0x8780), 604 DMAE_CHANNEL(0x8800), 605 DMAE_CHANNEL(0x8880), 606 DMAE_CHANNEL(0x8900), 607 DMAE_CHANNEL(0x8980), 608 }; 609 610 static struct sh_dmae_pdata sh73a0_dmae_platform_data = { 611 .slave = sh73a0_dmae_slaves, 612 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), 613 .channel = sh73a0_dmae_channels, 614 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), 615 .ts_low_shift = TS_LOW_SHIFT, 616 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 617 .ts_high_shift = TS_HI_SHIFT, 618 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 619 .ts_shift = dma_ts_shift, 620 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 621 .dmaor_init = DMAOR_DME, 622 }; 623 624 static struct resource sh73a0_dmae_resources[] = { 625 { 626 /* Registers including DMAOR and channels including DMARSx */ 627 .start = 0xfe000020, 628 .end = 0xfe008a00 - 1, 629 .flags = IORESOURCE_MEM, 630 }, 631 { 632 .name = "error_irq", 633 .start = gic_spi(129), 634 .end = gic_spi(129), 635 .flags = IORESOURCE_IRQ, 636 }, 637 { 638 /* IRQ for channels 0-19 */ 639 .start = gic_spi(109), 640 .end = gic_spi(128), 641 .flags = IORESOURCE_IRQ, 642 }, 643 }; 644 645 static struct platform_device dma0_device = { 646 .name = "sh-dma-engine", 647 .id = 0, 648 .resource = sh73a0_dmae_resources, 649 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), 650 .dev = { 651 .platform_data = &sh73a0_dmae_platform_data, 652 }, 653 }; 654 655 /* MPDMAC */ 656 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = { 657 { 658 .slave_id = SHDMA_SLAVE_FSI2A_RX, 659 .addr = 0xec230020, 660 .chcr = CHCR_RX(XMIT_SZ_32BIT), 661 .mid_rid = 0xd6, /* CHECK ME */ 662 }, { 663 .slave_id = SHDMA_SLAVE_FSI2A_TX, 664 .addr = 0xec230024, 665 .chcr = CHCR_TX(XMIT_SZ_32BIT), 666 .mid_rid = 0xd5, /* CHECK ME */ 667 }, { 668 .slave_id = SHDMA_SLAVE_FSI2C_RX, 669 .addr = 0xec230060, 670 .chcr = CHCR_RX(XMIT_SZ_32BIT), 671 .mid_rid = 0xda, /* CHECK ME */ 672 }, { 673 .slave_id = SHDMA_SLAVE_FSI2C_TX, 674 .addr = 0xec230064, 675 .chcr = CHCR_TX(XMIT_SZ_32BIT), 676 .mid_rid = 0xd9, /* CHECK ME */ 677 }, { 678 .slave_id = SHDMA_SLAVE_FSI2B_RX, 679 .addr = 0xec240020, 680 .chcr = CHCR_RX(XMIT_SZ_32BIT), 681 .mid_rid = 0x8e, /* CHECK ME */ 682 }, { 683 .slave_id = SHDMA_SLAVE_FSI2B_TX, 684 .addr = 0xec240024, 685 .chcr = CHCR_RX(XMIT_SZ_32BIT), 686 .mid_rid = 0x8d, /* CHECK ME */ 687 }, { 688 .slave_id = SHDMA_SLAVE_FSI2D_RX, 689 .addr = 0xec240060, 690 .chcr = CHCR_RX(XMIT_SZ_32BIT), 691 .mid_rid = 0x9a, /* CHECK ME */ 692 }, 693 }; 694 695 #define MPDMA_CHANNEL(a, b, c) \ 696 { \ 697 .offset = a, \ 698 .dmars = b, \ 699 .dmars_bit = c, \ 700 .chclr_offset = (0x220 - 0x20) + a \ 701 } 702 703 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = { 704 MPDMA_CHANNEL(0x00, 0, 0), 705 MPDMA_CHANNEL(0x10, 0, 8), 706 MPDMA_CHANNEL(0x20, 4, 0), 707 MPDMA_CHANNEL(0x30, 4, 8), 708 MPDMA_CHANNEL(0x50, 8, 0), 709 MPDMA_CHANNEL(0x70, 8, 8), 710 }; 711 712 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { 713 .slave = sh73a0_mpdma_slaves, 714 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves), 715 .channel = sh73a0_mpdma_channels, 716 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels), 717 .ts_low_shift = TS_LOW_SHIFT, 718 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 719 .ts_high_shift = TS_HI_SHIFT, 720 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 721 .ts_shift = dma_ts_shift, 722 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 723 .dmaor_init = DMAOR_DME, 724 .chclr_present = 1, 725 }; 726 727 /* Resource order important! */ 728 static struct resource sh73a0_mpdma_resources[] = { 729 { 730 /* Channel registers and DMAOR */ 731 .start = 0xec618020, 732 .end = 0xec61828f, 733 .flags = IORESOURCE_MEM, 734 }, 735 { 736 /* DMARSx */ 737 .start = 0xec619000, 738 .end = 0xec61900b, 739 .flags = IORESOURCE_MEM, 740 }, 741 { 742 .name = "error_irq", 743 .start = gic_spi(181), 744 .end = gic_spi(181), 745 .flags = IORESOURCE_IRQ, 746 }, 747 { 748 /* IRQ for channels 0-5 */ 749 .start = gic_spi(175), 750 .end = gic_spi(180), 751 .flags = IORESOURCE_IRQ, 752 }, 753 }; 754 755 static struct platform_device mpdma0_device = { 756 .name = "sh-dma-engine", 757 .id = 1, 758 .resource = sh73a0_mpdma_resources, 759 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources), 760 .dev = { 761 .platform_data = &sh73a0_mpdma_platform_data, 762 }, 763 }; 764 765 static struct resource pmu_resources[] = { 766 [0] = { 767 .start = gic_spi(55), 768 .end = gic_spi(55), 769 .flags = IORESOURCE_IRQ, 770 }, 771 [1] = { 772 .start = gic_spi(56), 773 .end = gic_spi(56), 774 .flags = IORESOURCE_IRQ, 775 }, 776 }; 777 778 static struct platform_device pmu_device = { 779 .name = "arm-pmu", 780 .id = -1, 781 .num_resources = ARRAY_SIZE(pmu_resources), 782 .resource = pmu_resources, 783 }; 784 785 /* an IPMMU module for ICB */ 786 static struct resource ipmmu_resources[] = { 787 [0] = { 788 .name = "IPMMU", 789 .start = 0xfe951000, 790 .end = 0xfe9510ff, 791 .flags = IORESOURCE_MEM, 792 }, 793 }; 794 795 static const char * const ipmmu_dev_names[] = { 796 "sh_mobile_lcdc_fb.0", 797 }; 798 799 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { 800 .dev_names = ipmmu_dev_names, 801 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), 802 }; 803 804 static struct platform_device ipmmu_device = { 805 .name = "ipmmu", 806 .id = -1, 807 .dev = { 808 .platform_data = &ipmmu_platform_data, 809 }, 810 .resource = ipmmu_resources, 811 .num_resources = ARRAY_SIZE(ipmmu_resources), 812 }; 813 814 static struct platform_device *sh73a0_early_devices_dt[] __initdata = { 815 &scif0_device, 816 &scif1_device, 817 &scif2_device, 818 &scif3_device, 819 &scif4_device, 820 &scif5_device, 821 &scif6_device, 822 &scif7_device, 823 &scif8_device, 824 &cmt10_device, 825 }; 826 827 static struct platform_device *sh73a0_early_devices[] __initdata = { 828 &tmu00_device, 829 &tmu01_device, 830 &ipmmu_device, 831 }; 832 833 static struct platform_device *sh73a0_late_devices[] __initdata = { 834 &i2c0_device, 835 &i2c1_device, 836 &i2c2_device, 837 &i2c3_device, 838 &i2c4_device, 839 &dma0_device, 840 &mpdma0_device, 841 &pmu_device, 842 }; 843 844 #define SRCR2 IOMEM(0xe61580b0) 845 846 void __init sh73a0_add_standard_devices(void) 847 { 848 /* Clear software reset bit on SY-DMAC module */ 849 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); 850 851 platform_add_devices(sh73a0_early_devices_dt, 852 ARRAY_SIZE(sh73a0_early_devices_dt)); 853 platform_add_devices(sh73a0_early_devices, 854 ARRAY_SIZE(sh73a0_early_devices)); 855 platform_add_devices(sh73a0_late_devices, 856 ARRAY_SIZE(sh73a0_late_devices)); 857 } 858 859 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 860 void __init __weak sh73a0_register_twd(void) { } 861 862 void __init sh73a0_earlytimer_init(void) 863 { 864 sh73a0_clock_init(); 865 shmobile_earlytimer_init(); 866 sh73a0_register_twd(); 867 } 868 869 void __init sh73a0_add_early_devices(void) 870 { 871 early_platform_add_devices(sh73a0_early_devices_dt, 872 ARRAY_SIZE(sh73a0_early_devices_dt)); 873 early_platform_add_devices(sh73a0_early_devices, 874 ARRAY_SIZE(sh73a0_early_devices)); 875 876 /* setup early console here as well */ 877 shmobile_setup_console(); 878 } 879 880 #ifdef CONFIG_USE_OF 881 882 /* Please note that the clock initialisation shcheme used in 883 * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt() 884 * does not work with SMP as there is a yet to be resolved lock-up in 885 * workqueue initialisation. 886 * 887 * CONFIG_SMP should be disabled when using this code. 888 */ 889 890 void __init sh73a0_add_early_devices_dt(void) 891 { 892 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ 893 894 early_platform_add_devices(sh73a0_early_devices_dt, 895 ARRAY_SIZE(sh73a0_early_devices_dt)); 896 897 /* setup early console here as well */ 898 shmobile_setup_console(); 899 } 900 901 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = { 902 {}, 903 }; 904 905 void __init sh73a0_add_standard_devices_dt(void) 906 { 907 /* clocks are setup late during boot in the case of DT */ 908 sh73a0_clock_init(); 909 910 platform_add_devices(sh73a0_early_devices_dt, 911 ARRAY_SIZE(sh73a0_early_devices_dt)); 912 of_platform_populate(NULL, of_default_bus_match_table, 913 sh73a0_auxdata_lookup, NULL); 914 } 915 916 static const char *sh73a0_boards_compat_dt[] __initdata = { 917 "renesas,sh73a0", 918 NULL, 919 }; 920 921 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") 922 .smp = smp_ops(sh73a0_smp_ops), 923 .map_io = sh73a0_map_io, 924 .init_early = sh73a0_add_early_devices_dt, 925 .nr_irqs = NR_IRQS_LEGACY, 926 .init_irq = irqchip_init, 927 .init_machine = sh73a0_add_standard_devices_dt, 928 .init_time = shmobile_timer_init, 929 .dt_compat = sh73a0_boards_compat_dt, 930 MACHINE_END 931 #endif /* CONFIG_USE_OF */ 932