1 /*
2  * sh73a0 processor support
3  *
4  * Copyright (C) 2010  Takashi Yoshii
5  * Copyright (C) 2010  Magnus Damm
6  * Copyright (C) 2008  Yoshihiro Shimoda
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; version 2 of the License.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
20  */
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
28 #include <linux/io.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_intc.h>
31 #include <linux/sh_timer.h>
32 #include <mach/hardware.h>
33 #include <asm/mach-types.h>
34 #include <asm/mach/arch.h>
35 
36 static struct plat_sci_port scif0_platform_data = {
37 	.mapbase	= 0xe6c40000,
38 	.flags		= UPF_BOOT_AUTOCONF,
39 	.scscr		= SCSCR_RE | SCSCR_TE,
40 	.scbrr_algo_id	= SCBRR_ALGO_4,
41 	.type		= PORT_SCIFA,
42 	.irqs		= { gic_spi(72), gic_spi(72),
43 			    gic_spi(72), gic_spi(72) },
44 };
45 
46 static struct platform_device scif0_device = {
47 	.name		= "sh-sci",
48 	.id		= 0,
49 	.dev		= {
50 		.platform_data	= &scif0_platform_data,
51 	},
52 };
53 
54 static struct plat_sci_port scif1_platform_data = {
55 	.mapbase	= 0xe6c50000,
56 	.flags		= UPF_BOOT_AUTOCONF,
57 	.scscr		= SCSCR_RE | SCSCR_TE,
58 	.scbrr_algo_id	= SCBRR_ALGO_4,
59 	.type		= PORT_SCIFA,
60 	.irqs		= { gic_spi(73), gic_spi(73),
61 			    gic_spi(73), gic_spi(73) },
62 };
63 
64 static struct platform_device scif1_device = {
65 	.name		= "sh-sci",
66 	.id		= 1,
67 	.dev		= {
68 		.platform_data	= &scif1_platform_data,
69 	},
70 };
71 
72 static struct plat_sci_port scif2_platform_data = {
73 	.mapbase	= 0xe6c60000,
74 	.flags		= UPF_BOOT_AUTOCONF,
75 	.scscr		= SCSCR_RE | SCSCR_TE,
76 	.scbrr_algo_id	= SCBRR_ALGO_4,
77 	.type		= PORT_SCIFA,
78 	.irqs		= { gic_spi(74), gic_spi(74),
79 			    gic_spi(74), gic_spi(74) },
80 };
81 
82 static struct platform_device scif2_device = {
83 	.name		= "sh-sci",
84 	.id		= 2,
85 	.dev		= {
86 		.platform_data	= &scif2_platform_data,
87 	},
88 };
89 
90 static struct plat_sci_port scif3_platform_data = {
91 	.mapbase	= 0xe6c70000,
92 	.flags		= UPF_BOOT_AUTOCONF,
93 	.scscr		= SCSCR_RE | SCSCR_TE,
94 	.scbrr_algo_id	= SCBRR_ALGO_4,
95 	.type		= PORT_SCIFA,
96 	.irqs		= { gic_spi(75), gic_spi(75),
97 			    gic_spi(75), gic_spi(75) },
98 };
99 
100 static struct platform_device scif3_device = {
101 	.name		= "sh-sci",
102 	.id		= 3,
103 	.dev		= {
104 		.platform_data	= &scif3_platform_data,
105 	},
106 };
107 
108 static struct plat_sci_port scif4_platform_data = {
109 	.mapbase	= 0xe6c80000,
110 	.flags		= UPF_BOOT_AUTOCONF,
111 	.scscr		= SCSCR_RE | SCSCR_TE,
112 	.scbrr_algo_id	= SCBRR_ALGO_4,
113 	.type		= PORT_SCIFA,
114 	.irqs		= { gic_spi(78), gic_spi(78),
115 			    gic_spi(78), gic_spi(78) },
116 };
117 
118 static struct platform_device scif4_device = {
119 	.name		= "sh-sci",
120 	.id		= 4,
121 	.dev		= {
122 		.platform_data	= &scif4_platform_data,
123 	},
124 };
125 
126 static struct plat_sci_port scif5_platform_data = {
127 	.mapbase	= 0xe6cb0000,
128 	.flags		= UPF_BOOT_AUTOCONF,
129 	.scscr		= SCSCR_RE | SCSCR_TE,
130 	.scbrr_algo_id	= SCBRR_ALGO_4,
131 	.type		= PORT_SCIFA,
132 	.irqs		= { gic_spi(79), gic_spi(79),
133 			    gic_spi(79), gic_spi(79) },
134 };
135 
136 static struct platform_device scif5_device = {
137 	.name		= "sh-sci",
138 	.id		= 5,
139 	.dev		= {
140 		.platform_data	= &scif5_platform_data,
141 	},
142 };
143 
144 static struct plat_sci_port scif6_platform_data = {
145 	.mapbase	= 0xe6cc0000,
146 	.flags		= UPF_BOOT_AUTOCONF,
147 	.scscr		= SCSCR_RE | SCSCR_TE,
148 	.scbrr_algo_id	= SCBRR_ALGO_4,
149 	.type		= PORT_SCIFA,
150 	.irqs		= { gic_spi(156), gic_spi(156),
151 			    gic_spi(156), gic_spi(156) },
152 };
153 
154 static struct platform_device scif6_device = {
155 	.name		= "sh-sci",
156 	.id		= 6,
157 	.dev		= {
158 		.platform_data	= &scif6_platform_data,
159 	},
160 };
161 
162 static struct plat_sci_port scif7_platform_data = {
163 	.mapbase	= 0xe6cd0000,
164 	.flags		= UPF_BOOT_AUTOCONF,
165 	.scscr		= SCSCR_RE | SCSCR_TE,
166 	.scbrr_algo_id	= SCBRR_ALGO_4,
167 	.type		= PORT_SCIFA,
168 	.irqs		= { gic_spi(143), gic_spi(143),
169 			    gic_spi(143), gic_spi(143) },
170 };
171 
172 static struct platform_device scif7_device = {
173 	.name		= "sh-sci",
174 	.id		= 7,
175 	.dev		= {
176 		.platform_data	= &scif7_platform_data,
177 	},
178 };
179 
180 static struct plat_sci_port scif8_platform_data = {
181 	.mapbase	= 0xe6c30000,
182 	.flags		= UPF_BOOT_AUTOCONF,
183 	.scscr		= SCSCR_RE | SCSCR_TE,
184 	.scbrr_algo_id	= SCBRR_ALGO_4,
185 	.type		= PORT_SCIFB,
186 	.irqs		= { gic_spi(80), gic_spi(80),
187 			    gic_spi(80), gic_spi(80) },
188 };
189 
190 static struct platform_device scif8_device = {
191 	.name		= "sh-sci",
192 	.id		= 8,
193 	.dev		= {
194 		.platform_data	= &scif8_platform_data,
195 	},
196 };
197 
198 static struct sh_timer_config cmt10_platform_data = {
199 	.name = "CMT10",
200 	.channel_offset = 0x10,
201 	.timer_bit = 0,
202 	.clockevent_rating = 125,
203 	.clocksource_rating = 125,
204 };
205 
206 static struct resource cmt10_resources[] = {
207 	[0] = {
208 		.name	= "CMT10",
209 		.start	= 0xe6138010,
210 		.end	= 0xe613801b,
211 		.flags	= IORESOURCE_MEM,
212 	},
213 	[1] = {
214 		.start	= gic_spi(65),
215 		.flags	= IORESOURCE_IRQ,
216 	},
217 };
218 
219 static struct platform_device cmt10_device = {
220 	.name		= "sh_cmt",
221 	.id		= 10,
222 	.dev = {
223 		.platform_data	= &cmt10_platform_data,
224 	},
225 	.resource	= cmt10_resources,
226 	.num_resources	= ARRAY_SIZE(cmt10_resources),
227 };
228 
229 /* TMU */
230 static struct sh_timer_config tmu00_platform_data = {
231 	.name = "TMU00",
232 	.channel_offset = 0x4,
233 	.timer_bit = 0,
234 	.clockevent_rating = 200,
235 };
236 
237 static struct resource tmu00_resources[] = {
238 	[0] = {
239 		.name	= "TMU00",
240 		.start	= 0xfff60008,
241 		.end	= 0xfff60013,
242 		.flags	= IORESOURCE_MEM,
243 	},
244 	[1] = {
245 		.start	= intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
246 		.flags	= IORESOURCE_IRQ,
247 	},
248 };
249 
250 static struct platform_device tmu00_device = {
251 	.name		= "sh_tmu",
252 	.id		= 0,
253 	.dev = {
254 		.platform_data	= &tmu00_platform_data,
255 	},
256 	.resource	= tmu00_resources,
257 	.num_resources	= ARRAY_SIZE(tmu00_resources),
258 };
259 
260 static struct sh_timer_config tmu01_platform_data = {
261 	.name = "TMU01",
262 	.channel_offset = 0x10,
263 	.timer_bit = 1,
264 	.clocksource_rating = 200,
265 };
266 
267 static struct resource tmu01_resources[] = {
268 	[0] = {
269 		.name	= "TMU01",
270 		.start	= 0xfff60014,
271 		.end	= 0xfff6001f,
272 		.flags	= IORESOURCE_MEM,
273 	},
274 	[1] = {
275 		.start	= intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
276 		.flags	= IORESOURCE_IRQ,
277 	},
278 };
279 
280 static struct platform_device tmu01_device = {
281 	.name		= "sh_tmu",
282 	.id		= 1,
283 	.dev = {
284 		.platform_data	= &tmu01_platform_data,
285 	},
286 	.resource	= tmu01_resources,
287 	.num_resources	= ARRAY_SIZE(tmu01_resources),
288 };
289 
290 static struct resource i2c0_resources[] = {
291 	[0] = {
292 		.name	= "IIC0",
293 		.start	= 0xe6820000,
294 		.end	= 0xe6820425 - 1,
295 		.flags	= IORESOURCE_MEM,
296 	},
297 	[1] = {
298 		.start	= gic_spi(167),
299 		.end	= gic_spi(170),
300 		.flags	= IORESOURCE_IRQ,
301 	},
302 };
303 
304 static struct resource i2c1_resources[] = {
305 	[0] = {
306 		.name	= "IIC1",
307 		.start	= 0xe6822000,
308 		.end	= 0xe6822425 - 1,
309 		.flags	= IORESOURCE_MEM,
310 	},
311 	[1] = {
312 		.start	= gic_spi(51),
313 		.end	= gic_spi(54),
314 		.flags	= IORESOURCE_IRQ,
315 	},
316 };
317 
318 static struct resource i2c2_resources[] = {
319 	[0] = {
320 		.name	= "IIC2",
321 		.start	= 0xe6824000,
322 		.end	= 0xe6824425 - 1,
323 		.flags	= IORESOURCE_MEM,
324 	},
325 	[1] = {
326 		.start	= gic_spi(171),
327 		.end	= gic_spi(174),
328 		.flags	= IORESOURCE_IRQ,
329 	},
330 };
331 
332 static struct resource i2c3_resources[] = {
333 	[0] = {
334 		.name	= "IIC3",
335 		.start	= 0xe6826000,
336 		.end	= 0xe6826425 - 1,
337 		.flags	= IORESOURCE_MEM,
338 	},
339 	[1] = {
340 		.start	= gic_spi(183),
341 		.end	= gic_spi(186),
342 		.flags	= IORESOURCE_IRQ,
343 	},
344 };
345 
346 static struct resource i2c4_resources[] = {
347 	[0] = {
348 		.name	= "IIC4",
349 		.start	= 0xe6828000,
350 		.end	= 0xe6828425 - 1,
351 		.flags	= IORESOURCE_MEM,
352 	},
353 	[1] = {
354 		.start	= gic_spi(187),
355 		.end	= gic_spi(190),
356 		.flags	= IORESOURCE_IRQ,
357 	},
358 };
359 
360 static struct platform_device i2c0_device = {
361 	.name		= "i2c-sh_mobile",
362 	.id		= 0,
363 	.resource	= i2c0_resources,
364 	.num_resources	= ARRAY_SIZE(i2c0_resources),
365 };
366 
367 static struct platform_device i2c1_device = {
368 	.name		= "i2c-sh_mobile",
369 	.id		= 1,
370 	.resource	= i2c1_resources,
371 	.num_resources	= ARRAY_SIZE(i2c1_resources),
372 };
373 
374 static struct platform_device i2c2_device = {
375 	.name		= "i2c-sh_mobile",
376 	.id		= 2,
377 	.resource	= i2c2_resources,
378 	.num_resources	= ARRAY_SIZE(i2c2_resources),
379 };
380 
381 static struct platform_device i2c3_device = {
382 	.name		= "i2c-sh_mobile",
383 	.id		= 3,
384 	.resource	= i2c3_resources,
385 	.num_resources	= ARRAY_SIZE(i2c3_resources),
386 };
387 
388 static struct platform_device i2c4_device = {
389 	.name		= "i2c-sh_mobile",
390 	.id		= 4,
391 	.resource	= i2c4_resources,
392 	.num_resources	= ARRAY_SIZE(i2c4_resources),
393 };
394 
395 static struct platform_device *sh73a0_early_devices[] __initdata = {
396 	&scif0_device,
397 	&scif1_device,
398 	&scif2_device,
399 	&scif3_device,
400 	&scif4_device,
401 	&scif5_device,
402 	&scif6_device,
403 	&scif7_device,
404 	&scif8_device,
405 	&cmt10_device,
406 	&tmu00_device,
407 	&tmu01_device,
408 };
409 
410 static struct platform_device *sh73a0_late_devices[] __initdata = {
411 	&i2c0_device,
412 	&i2c1_device,
413 	&i2c2_device,
414 	&i2c3_device,
415 	&i2c4_device,
416 };
417 
418 void __init sh73a0_add_standard_devices(void)
419 {
420 	platform_add_devices(sh73a0_early_devices,
421 			    ARRAY_SIZE(sh73a0_early_devices));
422 	platform_add_devices(sh73a0_late_devices,
423 			    ARRAY_SIZE(sh73a0_late_devices));
424 }
425 
426 void __init sh73a0_add_early_devices(void)
427 {
428 	early_platform_add_devices(sh73a0_early_devices,
429 				   ARRAY_SIZE(sh73a0_early_devices));
430 }
431