1 /*
2  * sh73a0 processor support
3  *
4  * Copyright (C) 2010  Takashi Yoshii
5  * Copyright (C) 2010  Magnus Damm
6  * Copyright (C) 2008  Yoshihiro Shimoda
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; version 2 of the License.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
20  */
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
29 #include <linux/io.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/platform_data/sh_ipmmu.h>
35 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
36 #include <mach/dma-register.h>
37 #include <mach/irqs.h>
38 #include <mach/sh73a0.h>
39 #include <mach/common.h>
40 #include <asm/mach-types.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/time.h>
44 
45 static struct map_desc sh73a0_io_desc[] __initdata = {
46 	/* create a 1:1 entity map for 0xe6xxxxxx
47 	 * used by CPGA, INTC and PFC.
48 	 */
49 	{
50 		.virtual	= 0xe6000000,
51 		.pfn		= __phys_to_pfn(0xe6000000),
52 		.length		= 256 << 20,
53 		.type		= MT_DEVICE_NONSHARED
54 	},
55 };
56 
57 void __init sh73a0_map_io(void)
58 {
59 	iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
60 }
61 
62 /* PFC */
63 static struct resource pfc_resources[] __initdata = {
64 	DEFINE_RES_MEM(0xe6050000, 0x8000),
65 	DEFINE_RES_MEM(0xe605801c, 0x000c),
66 };
67 
68 void __init sh73a0_pinmux_init(void)
69 {
70 	platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
71 					ARRAY_SIZE(pfc_resources));
72 }
73 
74 /* SCIF */
75 #define SH73A0_SCIF(scif_type, index, baseaddr, irq)		\
76 static struct plat_sci_port scif##index##_platform_data = {	\
77 	.type		= scif_type,				\
78 	.flags		= UPF_BOOT_AUTOCONF,			\
79 	.scscr		= SCSCR_RE | SCSCR_TE,			\
80 };								\
81 								\
82 static struct resource scif##index##_resources[] = {		\
83 	DEFINE_RES_MEM(baseaddr, 0x100),			\
84 	DEFINE_RES_IRQ(irq),					\
85 };								\
86 								\
87 static struct platform_device scif##index##_device = {		\
88 	.name		= "sh-sci",				\
89 	.id		= index,				\
90 	.resource	= scif##index##_resources,		\
91 	.num_resources	= ARRAY_SIZE(scif##index##_resources),	\
92 	.dev		= {					\
93 		.platform_data	= &scif##index##_platform_data,	\
94 	},							\
95 }
96 
97 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
98 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
99 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
100 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
101 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
102 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
103 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
104 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
105 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
106 
107 static struct sh_timer_config cmt1_platform_data = {
108 	.channels_mask = 0x3f,
109 };
110 
111 static struct resource cmt1_resources[] = {
112 	DEFINE_RES_MEM(0xe6138000, 0x200),
113 	DEFINE_RES_IRQ(gic_spi(65)),
114 };
115 
116 static struct platform_device cmt1_device = {
117 	.name		= "sh-cmt-48",
118 	.id		= 1,
119 	.dev = {
120 		.platform_data	= &cmt1_platform_data,
121 	},
122 	.resource	= cmt1_resources,
123 	.num_resources	= ARRAY_SIZE(cmt1_resources),
124 };
125 
126 /* TMU */
127 static struct sh_timer_config tmu0_platform_data = {
128 	.channels_mask = 7,
129 };
130 
131 static struct resource tmu0_resources[] = {
132 	DEFINE_RES_MEM(0xfff60000, 0x2c),
133 	DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
134 	DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
135 	DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
136 };
137 
138 static struct platform_device tmu0_device = {
139 	.name		= "sh-tmu",
140 	.id		= 0,
141 	.dev = {
142 		.platform_data	= &tmu0_platform_data,
143 	},
144 	.resource	= tmu0_resources,
145 	.num_resources	= ARRAY_SIZE(tmu0_resources),
146 };
147 
148 static struct resource i2c0_resources[] = {
149 	[0] = DEFINE_RES_MEM(0xe6820000, 0x426),
150 	[1] = {
151 		.start	= gic_spi(167),
152 		.end	= gic_spi(170),
153 		.flags	= IORESOURCE_IRQ,
154 	},
155 };
156 
157 static struct resource i2c1_resources[] = {
158 	[0] = DEFINE_RES_MEM(0xe6822000, 0x426),
159 	[1] = {
160 		.start	= gic_spi(51),
161 		.end	= gic_spi(54),
162 		.flags	= IORESOURCE_IRQ,
163 	},
164 };
165 
166 static struct resource i2c2_resources[] = {
167 	[0] = DEFINE_RES_MEM(0xe6824000, 0x426),
168 	[1] = {
169 		.start	= gic_spi(171),
170 		.end	= gic_spi(174),
171 		.flags	= IORESOURCE_IRQ,
172 	},
173 };
174 
175 static struct resource i2c3_resources[] = {
176 	[0] = DEFINE_RES_MEM(0xe6826000, 0x426),
177 	[1] = {
178 		.start	= gic_spi(183),
179 		.end	= gic_spi(186),
180 		.flags	= IORESOURCE_IRQ,
181 	},
182 };
183 
184 static struct resource i2c4_resources[] = {
185 	[0] = DEFINE_RES_MEM(0xe6828000, 0x426),
186 	[1] = {
187 		.start	= gic_spi(187),
188 		.end	= gic_spi(190),
189 		.flags	= IORESOURCE_IRQ,
190 	},
191 };
192 
193 static struct platform_device i2c0_device = {
194 	.name		= "i2c-sh_mobile",
195 	.id		= 0,
196 	.resource	= i2c0_resources,
197 	.num_resources	= ARRAY_SIZE(i2c0_resources),
198 };
199 
200 static struct platform_device i2c1_device = {
201 	.name		= "i2c-sh_mobile",
202 	.id		= 1,
203 	.resource	= i2c1_resources,
204 	.num_resources	= ARRAY_SIZE(i2c1_resources),
205 };
206 
207 static struct platform_device i2c2_device = {
208 	.name		= "i2c-sh_mobile",
209 	.id		= 2,
210 	.resource	= i2c2_resources,
211 	.num_resources	= ARRAY_SIZE(i2c2_resources),
212 };
213 
214 static struct platform_device i2c3_device = {
215 	.name		= "i2c-sh_mobile",
216 	.id		= 3,
217 	.resource	= i2c3_resources,
218 	.num_resources	= ARRAY_SIZE(i2c3_resources),
219 };
220 
221 static struct platform_device i2c4_device = {
222 	.name		= "i2c-sh_mobile",
223 	.id		= 4,
224 	.resource	= i2c4_resources,
225 	.num_resources	= ARRAY_SIZE(i2c4_resources),
226 };
227 
228 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
229 	{
230 		.slave_id	= SHDMA_SLAVE_SCIF0_TX,
231 		.addr		= 0xe6c40020,
232 		.chcr		= CHCR_TX(XMIT_SZ_8BIT),
233 		.mid_rid	= 0x21,
234 	}, {
235 		.slave_id	= SHDMA_SLAVE_SCIF0_RX,
236 		.addr		= 0xe6c40024,
237 		.chcr		= CHCR_RX(XMIT_SZ_8BIT),
238 		.mid_rid	= 0x22,
239 	}, {
240 		.slave_id	= SHDMA_SLAVE_SCIF1_TX,
241 		.addr		= 0xe6c50020,
242 		.chcr		= CHCR_TX(XMIT_SZ_8BIT),
243 		.mid_rid	= 0x25,
244 	}, {
245 		.slave_id	= SHDMA_SLAVE_SCIF1_RX,
246 		.addr		= 0xe6c50024,
247 		.chcr		= CHCR_RX(XMIT_SZ_8BIT),
248 		.mid_rid	= 0x26,
249 	}, {
250 		.slave_id	= SHDMA_SLAVE_SCIF2_TX,
251 		.addr		= 0xe6c60020,
252 		.chcr		= CHCR_TX(XMIT_SZ_8BIT),
253 		.mid_rid	= 0x29,
254 	}, {
255 		.slave_id	= SHDMA_SLAVE_SCIF2_RX,
256 		.addr		= 0xe6c60024,
257 		.chcr		= CHCR_RX(XMIT_SZ_8BIT),
258 		.mid_rid	= 0x2a,
259 	}, {
260 		.slave_id	= SHDMA_SLAVE_SCIF3_TX,
261 		.addr		= 0xe6c70020,
262 		.chcr		= CHCR_TX(XMIT_SZ_8BIT),
263 		.mid_rid	= 0x2d,
264 	}, {
265 		.slave_id	= SHDMA_SLAVE_SCIF3_RX,
266 		.addr		= 0xe6c70024,
267 		.chcr		= CHCR_RX(XMIT_SZ_8BIT),
268 		.mid_rid	= 0x2e,
269 	}, {
270 		.slave_id	= SHDMA_SLAVE_SCIF4_TX,
271 		.addr		= 0xe6c80020,
272 		.chcr		= CHCR_TX(XMIT_SZ_8BIT),
273 		.mid_rid	= 0x39,
274 	}, {
275 		.slave_id	= SHDMA_SLAVE_SCIF4_RX,
276 		.addr		= 0xe6c80024,
277 		.chcr		= CHCR_RX(XMIT_SZ_8BIT),
278 		.mid_rid	= 0x3a,
279 	}, {
280 		.slave_id	= SHDMA_SLAVE_SCIF5_TX,
281 		.addr		= 0xe6cb0020,
282 		.chcr		= CHCR_TX(XMIT_SZ_8BIT),
283 		.mid_rid	= 0x35,
284 	}, {
285 		.slave_id	= SHDMA_SLAVE_SCIF5_RX,
286 		.addr		= 0xe6cb0024,
287 		.chcr		= CHCR_RX(XMIT_SZ_8BIT),
288 		.mid_rid	= 0x36,
289 	}, {
290 		.slave_id	= SHDMA_SLAVE_SCIF6_TX,
291 		.addr		= 0xe6cc0020,
292 		.chcr		= CHCR_TX(XMIT_SZ_8BIT),
293 		.mid_rid	= 0x1d,
294 	}, {
295 		.slave_id	= SHDMA_SLAVE_SCIF6_RX,
296 		.addr		= 0xe6cc0024,
297 		.chcr		= CHCR_RX(XMIT_SZ_8BIT),
298 		.mid_rid	= 0x1e,
299 	}, {
300 		.slave_id	= SHDMA_SLAVE_SCIF7_TX,
301 		.addr		= 0xe6cd0020,
302 		.chcr		= CHCR_TX(XMIT_SZ_8BIT),
303 		.mid_rid	= 0x19,
304 	}, {
305 		.slave_id	= SHDMA_SLAVE_SCIF7_RX,
306 		.addr		= 0xe6cd0024,
307 		.chcr		= CHCR_RX(XMIT_SZ_8BIT),
308 		.mid_rid	= 0x1a,
309 	}, {
310 		.slave_id	= SHDMA_SLAVE_SCIF8_TX,
311 		.addr		= 0xe6c30040,
312 		.chcr		= CHCR_TX(XMIT_SZ_8BIT),
313 		.mid_rid	= 0x3d,
314 	}, {
315 		.slave_id	= SHDMA_SLAVE_SCIF8_RX,
316 		.addr		= 0xe6c30060,
317 		.chcr		= CHCR_RX(XMIT_SZ_8BIT),
318 		.mid_rid	= 0x3e,
319 	}, {
320 		.slave_id	= SHDMA_SLAVE_SDHI0_TX,
321 		.addr		= 0xee100030,
322 		.chcr		= CHCR_TX(XMIT_SZ_16BIT),
323 		.mid_rid	= 0xc1,
324 	}, {
325 		.slave_id	= SHDMA_SLAVE_SDHI0_RX,
326 		.addr		= 0xee100030,
327 		.chcr		= CHCR_RX(XMIT_SZ_16BIT),
328 		.mid_rid	= 0xc2,
329 	}, {
330 		.slave_id	= SHDMA_SLAVE_SDHI1_TX,
331 		.addr		= 0xee120030,
332 		.chcr		= CHCR_TX(XMIT_SZ_16BIT),
333 		.mid_rid	= 0xc9,
334 	}, {
335 		.slave_id	= SHDMA_SLAVE_SDHI1_RX,
336 		.addr		= 0xee120030,
337 		.chcr		= CHCR_RX(XMIT_SZ_16BIT),
338 		.mid_rid	= 0xca,
339 	}, {
340 		.slave_id	= SHDMA_SLAVE_SDHI2_TX,
341 		.addr		= 0xee140030,
342 		.chcr		= CHCR_TX(XMIT_SZ_16BIT),
343 		.mid_rid	= 0xcd,
344 	}, {
345 		.slave_id	= SHDMA_SLAVE_SDHI2_RX,
346 		.addr		= 0xee140030,
347 		.chcr		= CHCR_RX(XMIT_SZ_16BIT),
348 		.mid_rid	= 0xce,
349 	}, {
350 		.slave_id	= SHDMA_SLAVE_MMCIF_TX,
351 		.addr		= 0xe6bd0034,
352 		.chcr		= CHCR_TX(XMIT_SZ_32BIT),
353 		.mid_rid	= 0xd1,
354 	}, {
355 		.slave_id	= SHDMA_SLAVE_MMCIF_RX,
356 		.addr		= 0xe6bd0034,
357 		.chcr		= CHCR_RX(XMIT_SZ_32BIT),
358 		.mid_rid	= 0xd2,
359 	},
360 };
361 
362 #define DMAE_CHANNEL(_offset)					\
363 	{							\
364 		.offset         = _offset - 0x20,		\
365 		.dmars          = _offset - 0x20 + 0x40,	\
366 	}
367 
368 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
369 	DMAE_CHANNEL(0x8000),
370 	DMAE_CHANNEL(0x8080),
371 	DMAE_CHANNEL(0x8100),
372 	DMAE_CHANNEL(0x8180),
373 	DMAE_CHANNEL(0x8200),
374 	DMAE_CHANNEL(0x8280),
375 	DMAE_CHANNEL(0x8300),
376 	DMAE_CHANNEL(0x8380),
377 	DMAE_CHANNEL(0x8400),
378 	DMAE_CHANNEL(0x8480),
379 	DMAE_CHANNEL(0x8500),
380 	DMAE_CHANNEL(0x8580),
381 	DMAE_CHANNEL(0x8600),
382 	DMAE_CHANNEL(0x8680),
383 	DMAE_CHANNEL(0x8700),
384 	DMAE_CHANNEL(0x8780),
385 	DMAE_CHANNEL(0x8800),
386 	DMAE_CHANNEL(0x8880),
387 	DMAE_CHANNEL(0x8900),
388 	DMAE_CHANNEL(0x8980),
389 };
390 
391 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
392 	.slave          = sh73a0_dmae_slaves,
393 	.slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
394 	.channel        = sh73a0_dmae_channels,
395 	.channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
396 	.ts_low_shift   = TS_LOW_SHIFT,
397 	.ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
398 	.ts_high_shift  = TS_HI_SHIFT,
399 	.ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
400 	.ts_shift       = dma_ts_shift,
401 	.ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
402 	.dmaor_init     = DMAOR_DME,
403 };
404 
405 static struct resource sh73a0_dmae_resources[] = {
406 	DEFINE_RES_MEM(0xfe000020, 0x89e0),
407 	{
408 		.name	= "error_irq",
409 		.start  = gic_spi(129),
410 		.end    = gic_spi(129),
411 		.flags  = IORESOURCE_IRQ,
412 	},
413 	{
414 		/* IRQ for channels 0-19 */
415 		.start  = gic_spi(109),
416 		.end    = gic_spi(128),
417 		.flags  = IORESOURCE_IRQ,
418 	},
419 };
420 
421 static struct platform_device dma0_device = {
422 	.name		= "sh-dma-engine",
423 	.id		= 0,
424 	.resource	= sh73a0_dmae_resources,
425 	.num_resources	= ARRAY_SIZE(sh73a0_dmae_resources),
426 	.dev		= {
427 		.platform_data	= &sh73a0_dmae_platform_data,
428 	},
429 };
430 
431 /* MPDMAC */
432 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
433 	{
434 		.slave_id	= SHDMA_SLAVE_FSI2A_RX,
435 		.addr		= 0xec230020,
436 		.chcr		= CHCR_RX(XMIT_SZ_32BIT),
437 		.mid_rid	= 0xd6, /* CHECK ME */
438 	}, {
439 		.slave_id	= SHDMA_SLAVE_FSI2A_TX,
440 		.addr		= 0xec230024,
441 		.chcr		= CHCR_TX(XMIT_SZ_32BIT),
442 		.mid_rid	= 0xd5, /* CHECK ME */
443 	}, {
444 		.slave_id	= SHDMA_SLAVE_FSI2C_RX,
445 		.addr		= 0xec230060,
446 		.chcr		= CHCR_RX(XMIT_SZ_32BIT),
447 		.mid_rid	= 0xda, /* CHECK ME */
448 	}, {
449 		.slave_id	= SHDMA_SLAVE_FSI2C_TX,
450 		.addr		= 0xec230064,
451 		.chcr		= CHCR_TX(XMIT_SZ_32BIT),
452 		.mid_rid	= 0xd9, /* CHECK ME */
453 	}, {
454 		.slave_id	= SHDMA_SLAVE_FSI2B_RX,
455 		.addr		= 0xec240020,
456 		.chcr		= CHCR_RX(XMIT_SZ_32BIT),
457 		.mid_rid	= 0x8e, /* CHECK ME */
458 	}, {
459 		.slave_id	= SHDMA_SLAVE_FSI2B_TX,
460 		.addr		= 0xec240024,
461 		.chcr		= CHCR_RX(XMIT_SZ_32BIT),
462 		.mid_rid	= 0x8d, /* CHECK ME */
463 	}, {
464 		.slave_id	= SHDMA_SLAVE_FSI2D_RX,
465 		.addr		=  0xec240060,
466 		.chcr		= CHCR_RX(XMIT_SZ_32BIT),
467 		.mid_rid	= 0x9a, /* CHECK ME */
468 	},
469 };
470 
471 #define MPDMA_CHANNEL(a, b, c)			\
472 {						\
473 	.offset		= a,			\
474 	.dmars		= b,			\
475 	.dmars_bit	= c,			\
476 	.chclr_offset	= (0x220 - 0x20) + a	\
477 }
478 
479 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
480 	MPDMA_CHANNEL(0x00, 0, 0),
481 	MPDMA_CHANNEL(0x10, 0, 8),
482 	MPDMA_CHANNEL(0x20, 4, 0),
483 	MPDMA_CHANNEL(0x30, 4, 8),
484 	MPDMA_CHANNEL(0x50, 8, 0),
485 	MPDMA_CHANNEL(0x70, 8, 8),
486 };
487 
488 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
489 	.slave		= sh73a0_mpdma_slaves,
490 	.slave_num	= ARRAY_SIZE(sh73a0_mpdma_slaves),
491 	.channel	= sh73a0_mpdma_channels,
492 	.channel_num	= ARRAY_SIZE(sh73a0_mpdma_channels),
493 	.ts_low_shift	= TS_LOW_SHIFT,
494 	.ts_low_mask	= TS_LOW_BIT << TS_LOW_SHIFT,
495 	.ts_high_shift	= TS_HI_SHIFT,
496 	.ts_high_mask	= TS_HI_BIT << TS_HI_SHIFT,
497 	.ts_shift	= dma_ts_shift,
498 	.ts_shift_num	= ARRAY_SIZE(dma_ts_shift),
499 	.dmaor_init	= DMAOR_DME,
500 	.chclr_present	= 1,
501 };
502 
503 /* Resource order important! */
504 static struct resource sh73a0_mpdma_resources[] = {
505 	/* Channel registers and DMAOR */
506 	DEFINE_RES_MEM(0xec618020, 0x270),
507 	/* DMARSx */
508 	DEFINE_RES_MEM(0xec619000, 0xc),
509 	{
510 		.name	= "error_irq",
511 		.start	= gic_spi(181),
512 		.end	= gic_spi(181),
513 		.flags	= IORESOURCE_IRQ,
514 	},
515 	{
516 		/* IRQ for channels 0-5 */
517 		.start	= gic_spi(175),
518 		.end	= gic_spi(180),
519 		.flags	= IORESOURCE_IRQ,
520 	},
521 };
522 
523 static struct platform_device mpdma0_device = {
524 	.name		= "sh-dma-engine",
525 	.id		= 1,
526 	.resource	= sh73a0_mpdma_resources,
527 	.num_resources	= ARRAY_SIZE(sh73a0_mpdma_resources),
528 	.dev		= {
529 		.platform_data	= &sh73a0_mpdma_platform_data,
530 	},
531 };
532 
533 static struct resource pmu_resources[] = {
534 	[0] = {
535 		.start	= gic_spi(55),
536 		.end	= gic_spi(55),
537 		.flags	= IORESOURCE_IRQ,
538 	},
539 	[1] = {
540 		.start	= gic_spi(56),
541 		.end	= gic_spi(56),
542 		.flags	= IORESOURCE_IRQ,
543 	},
544 };
545 
546 static struct platform_device pmu_device = {
547 	.name		= "arm-pmu",
548 	.id		= -1,
549 	.num_resources	= ARRAY_SIZE(pmu_resources),
550 	.resource	= pmu_resources,
551 };
552 
553 /* an IPMMU module for ICB */
554 static struct resource ipmmu_resources[] = {
555 	DEFINE_RES_MEM(0xfe951000, 0x100),
556 };
557 
558 static const char * const ipmmu_dev_names[] = {
559 	"sh_mobile_lcdc_fb.0",
560 };
561 
562 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
563 	.dev_names = ipmmu_dev_names,
564 	.num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
565 };
566 
567 static struct platform_device ipmmu_device = {
568 	.name           = "ipmmu",
569 	.id             = -1,
570 	.dev = {
571 		.platform_data = &ipmmu_platform_data,
572 	},
573 	.resource       = ipmmu_resources,
574 	.num_resources  = ARRAY_SIZE(ipmmu_resources),
575 };
576 
577 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
578 	.irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
579 };
580 
581 static struct resource irqpin0_resources[] = {
582 	DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
583 	DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
584 	DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
585 	DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
586 	DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
587 	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
588 	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
589 	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
590 	DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
591 	DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
592 	DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
593 	DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
594 	DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
595 };
596 
597 static struct platform_device irqpin0_device = {
598 	.name		= "renesas_intc_irqpin",
599 	.id		= 0,
600 	.resource	= irqpin0_resources,
601 	.num_resources	= ARRAY_SIZE(irqpin0_resources),
602 	.dev		= {
603 		.platform_data	= &irqpin0_platform_data,
604 	},
605 };
606 
607 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
608 	.irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
609 	.control_parent = true, /* Disable spurious IRQ10 */
610 };
611 
612 static struct resource irqpin1_resources[] = {
613 	DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
614 	DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
615 	DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
616 	DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
617 	DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
618 	DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
619 	DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
620 	DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
621 	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
622 	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
623 	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
624 	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
625 	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
626 };
627 
628 static struct platform_device irqpin1_device = {
629 	.name		= "renesas_intc_irqpin",
630 	.id		= 1,
631 	.resource	= irqpin1_resources,
632 	.num_resources	= ARRAY_SIZE(irqpin1_resources),
633 	.dev		= {
634 		.platform_data	= &irqpin1_platform_data,
635 	},
636 };
637 
638 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
639 	.irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
640 };
641 
642 static struct resource irqpin2_resources[] = {
643 	DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
644 	DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
645 	DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
646 	DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
647 	DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
648 	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
649 	DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
650 	DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
651 	DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
652 	DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
653 	DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
654 	DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
655 	DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
656 };
657 
658 static struct platform_device irqpin2_device = {
659 	.name		= "renesas_intc_irqpin",
660 	.id		= 2,
661 	.resource	= irqpin2_resources,
662 	.num_resources	= ARRAY_SIZE(irqpin2_resources),
663 	.dev		= {
664 		.platform_data	= &irqpin2_platform_data,
665 	},
666 };
667 
668 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
669 	.irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
670 };
671 
672 static struct resource irqpin3_resources[] = {
673 	DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
674 	DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
675 	DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
676 	DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
677 	DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
678 	DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
679 	DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
680 	DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
681 	DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
682 	DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
683 	DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
684 	DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
685 	DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
686 };
687 
688 static struct platform_device irqpin3_device = {
689 	.name		= "renesas_intc_irqpin",
690 	.id		= 3,
691 	.resource	= irqpin3_resources,
692 	.num_resources	= ARRAY_SIZE(irqpin3_resources),
693 	.dev		= {
694 		.platform_data	= &irqpin3_platform_data,
695 	},
696 };
697 
698 static struct platform_device *sh73a0_devices_dt[] __initdata = {
699 	&scif0_device,
700 	&scif1_device,
701 	&scif2_device,
702 	&scif3_device,
703 	&scif4_device,
704 	&scif5_device,
705 	&scif6_device,
706 	&scif7_device,
707 	&scif8_device,
708 	&cmt1_device,
709 };
710 
711 static struct platform_device *sh73a0_early_devices[] __initdata = {
712 	&tmu0_device,
713 	&ipmmu_device,
714 };
715 
716 static struct platform_device *sh73a0_late_devices[] __initdata = {
717 	&i2c0_device,
718 	&i2c1_device,
719 	&i2c2_device,
720 	&i2c3_device,
721 	&i2c4_device,
722 	&dma0_device,
723 	&mpdma0_device,
724 	&pmu_device,
725 	&irqpin0_device,
726 	&irqpin1_device,
727 	&irqpin2_device,
728 	&irqpin3_device,
729 };
730 
731 #define SRCR2          IOMEM(0xe61580b0)
732 
733 void __init sh73a0_add_standard_devices(void)
734 {
735 	/* Clear software reset bit on SY-DMAC module */
736 	__raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
737 
738 	platform_add_devices(sh73a0_devices_dt,
739 			    ARRAY_SIZE(sh73a0_devices_dt));
740 	platform_add_devices(sh73a0_early_devices,
741 			    ARRAY_SIZE(sh73a0_early_devices));
742 	platform_add_devices(sh73a0_late_devices,
743 			    ARRAY_SIZE(sh73a0_late_devices));
744 }
745 
746 void __init sh73a0_init_delay(void)
747 {
748 	shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
749 }
750 
751 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
752 void __init __weak sh73a0_register_twd(void) { }
753 
754 void __init sh73a0_earlytimer_init(void)
755 {
756 	sh73a0_init_delay();
757 	sh73a0_clock_init();
758 	shmobile_earlytimer_init();
759 	sh73a0_register_twd();
760 }
761 
762 void __init sh73a0_add_early_devices(void)
763 {
764 	early_platform_add_devices(sh73a0_devices_dt,
765 				   ARRAY_SIZE(sh73a0_devices_dt));
766 	early_platform_add_devices(sh73a0_early_devices,
767 				   ARRAY_SIZE(sh73a0_early_devices));
768 
769 	/* setup early console here as well */
770 	shmobile_setup_console();
771 }
772 
773 #ifdef CONFIG_USE_OF
774 
775 void __init sh73a0_add_standard_devices_dt(void)
776 {
777 	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
778 
779 	/* clocks are setup late during boot in the case of DT */
780 	sh73a0_clock_init();
781 
782 	platform_add_devices(sh73a0_devices_dt,
783 			     ARRAY_SIZE(sh73a0_devices_dt));
784 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
785 
786 	/* Instantiate cpufreq-cpu0 */
787 	platform_device_register_full(&devinfo);
788 }
789 
790 static const char *sh73a0_boards_compat_dt[] __initdata = {
791 	"renesas,sh73a0",
792 	NULL,
793 };
794 
795 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
796 	.smp		= smp_ops(sh73a0_smp_ops),
797 	.map_io		= sh73a0_map_io,
798 	.init_early	= sh73a0_init_delay,
799 	.nr_irqs	= NR_IRQS_LEGACY,
800 	.init_machine	= sh73a0_add_standard_devices_dt,
801 	.dt_compat	= sh73a0_boards_compat_dt,
802 MACHINE_END
803 #endif /* CONFIG_USE_OF */
804