1 /* 2 * sh73a0 processor support 3 * 4 * Copyright (C) 2010 Takashi Yoshii 5 * Copyright (C) 2010 Magnus Damm 6 * Copyright (C) 2008 Yoshihiro Shimoda 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/platform_device.h> 26 #include <linux/of_platform.h> 27 #include <linux/delay.h> 28 #include <linux/input.h> 29 #include <linux/io.h> 30 #include <linux/serial_sci.h> 31 #include <linux/sh_dma.h> 32 #include <linux/sh_timer.h> 33 #include <linux/platform_data/sh_ipmmu.h> 34 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 35 36 #include <asm/mach-types.h> 37 #include <asm/mach/map.h> 38 #include <asm/mach/arch.h> 39 #include <asm/mach/time.h> 40 41 #include "common.h" 42 #include "dma-register.h" 43 #include "irqs.h" 44 #include "sh73a0.h" 45 46 static struct map_desc sh73a0_io_desc[] __initdata = { 47 /* create a 1:1 entity map for 0xe6xxxxxx 48 * used by CPGA, INTC and PFC. 49 */ 50 { 51 .virtual = 0xe6000000, 52 .pfn = __phys_to_pfn(0xe6000000), 53 .length = 256 << 20, 54 .type = MT_DEVICE_NONSHARED 55 }, 56 }; 57 58 void __init sh73a0_map_io(void) 59 { 60 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); 61 } 62 63 /* PFC */ 64 static struct resource pfc_resources[] __initdata = { 65 DEFINE_RES_MEM(0xe6050000, 0x8000), 66 DEFINE_RES_MEM(0xe605801c, 0x000c), 67 }; 68 69 void __init sh73a0_pinmux_init(void) 70 { 71 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources, 72 ARRAY_SIZE(pfc_resources)); 73 } 74 75 /* SCIF */ 76 #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \ 77 static struct plat_sci_port scif##index##_platform_data = { \ 78 .type = scif_type, \ 79 .flags = UPF_BOOT_AUTOCONF, \ 80 .scscr = SCSCR_RE | SCSCR_TE, \ 81 }; \ 82 \ 83 static struct resource scif##index##_resources[] = { \ 84 DEFINE_RES_MEM(baseaddr, 0x100), \ 85 DEFINE_RES_IRQ(irq), \ 86 }; \ 87 \ 88 static struct platform_device scif##index##_device = { \ 89 .name = "sh-sci", \ 90 .id = index, \ 91 .resource = scif##index##_resources, \ 92 .num_resources = ARRAY_SIZE(scif##index##_resources), \ 93 .dev = { \ 94 .platform_data = &scif##index##_platform_data, \ 95 }, \ 96 } 97 98 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72)); 99 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); 100 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); 101 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); 102 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); 103 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); 104 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); 105 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); 106 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); 107 108 static struct sh_timer_config cmt1_platform_data = { 109 .channels_mask = 0x3f, 110 }; 111 112 static struct resource cmt1_resources[] = { 113 DEFINE_RES_MEM(0xe6138000, 0x200), 114 DEFINE_RES_IRQ(gic_spi(65)), 115 }; 116 117 static struct platform_device cmt1_device = { 118 .name = "sh-cmt-48", 119 .id = 1, 120 .dev = { 121 .platform_data = &cmt1_platform_data, 122 }, 123 .resource = cmt1_resources, 124 .num_resources = ARRAY_SIZE(cmt1_resources), 125 }; 126 127 /* TMU */ 128 static struct sh_timer_config tmu0_platform_data = { 129 .channels_mask = 7, 130 }; 131 132 static struct resource tmu0_resources[] = { 133 DEFINE_RES_MEM(0xfff60000, 0x2c), 134 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)), 135 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)), 136 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)), 137 }; 138 139 static struct platform_device tmu0_device = { 140 .name = "sh-tmu", 141 .id = 0, 142 .dev = { 143 .platform_data = &tmu0_platform_data, 144 }, 145 .resource = tmu0_resources, 146 .num_resources = ARRAY_SIZE(tmu0_resources), 147 }; 148 149 static struct resource i2c0_resources[] = { 150 [0] = DEFINE_RES_MEM(0xe6820000, 0x426), 151 [1] = { 152 .start = gic_spi(167), 153 .end = gic_spi(170), 154 .flags = IORESOURCE_IRQ, 155 }, 156 }; 157 158 static struct resource i2c1_resources[] = { 159 [0] = DEFINE_RES_MEM(0xe6822000, 0x426), 160 [1] = { 161 .start = gic_spi(51), 162 .end = gic_spi(54), 163 .flags = IORESOURCE_IRQ, 164 }, 165 }; 166 167 static struct resource i2c2_resources[] = { 168 [0] = DEFINE_RES_MEM(0xe6824000, 0x426), 169 [1] = { 170 .start = gic_spi(171), 171 .end = gic_spi(174), 172 .flags = IORESOURCE_IRQ, 173 }, 174 }; 175 176 static struct resource i2c3_resources[] = { 177 [0] = DEFINE_RES_MEM(0xe6826000, 0x426), 178 [1] = { 179 .start = gic_spi(183), 180 .end = gic_spi(186), 181 .flags = IORESOURCE_IRQ, 182 }, 183 }; 184 185 static struct resource i2c4_resources[] = { 186 [0] = DEFINE_RES_MEM(0xe6828000, 0x426), 187 [1] = { 188 .start = gic_spi(187), 189 .end = gic_spi(190), 190 .flags = IORESOURCE_IRQ, 191 }, 192 }; 193 194 static struct platform_device i2c0_device = { 195 .name = "i2c-sh_mobile", 196 .id = 0, 197 .resource = i2c0_resources, 198 .num_resources = ARRAY_SIZE(i2c0_resources), 199 }; 200 201 static struct platform_device i2c1_device = { 202 .name = "i2c-sh_mobile", 203 .id = 1, 204 .resource = i2c1_resources, 205 .num_resources = ARRAY_SIZE(i2c1_resources), 206 }; 207 208 static struct platform_device i2c2_device = { 209 .name = "i2c-sh_mobile", 210 .id = 2, 211 .resource = i2c2_resources, 212 .num_resources = ARRAY_SIZE(i2c2_resources), 213 }; 214 215 static struct platform_device i2c3_device = { 216 .name = "i2c-sh_mobile", 217 .id = 3, 218 .resource = i2c3_resources, 219 .num_resources = ARRAY_SIZE(i2c3_resources), 220 }; 221 222 static struct platform_device i2c4_device = { 223 .name = "i2c-sh_mobile", 224 .id = 4, 225 .resource = i2c4_resources, 226 .num_resources = ARRAY_SIZE(i2c4_resources), 227 }; 228 229 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { 230 { 231 .slave_id = SHDMA_SLAVE_SCIF0_TX, 232 .addr = 0xe6c40020, 233 .chcr = CHCR_TX(XMIT_SZ_8BIT), 234 .mid_rid = 0x21, 235 }, { 236 .slave_id = SHDMA_SLAVE_SCIF0_RX, 237 .addr = 0xe6c40024, 238 .chcr = CHCR_RX(XMIT_SZ_8BIT), 239 .mid_rid = 0x22, 240 }, { 241 .slave_id = SHDMA_SLAVE_SCIF1_TX, 242 .addr = 0xe6c50020, 243 .chcr = CHCR_TX(XMIT_SZ_8BIT), 244 .mid_rid = 0x25, 245 }, { 246 .slave_id = SHDMA_SLAVE_SCIF1_RX, 247 .addr = 0xe6c50024, 248 .chcr = CHCR_RX(XMIT_SZ_8BIT), 249 .mid_rid = 0x26, 250 }, { 251 .slave_id = SHDMA_SLAVE_SCIF2_TX, 252 .addr = 0xe6c60020, 253 .chcr = CHCR_TX(XMIT_SZ_8BIT), 254 .mid_rid = 0x29, 255 }, { 256 .slave_id = SHDMA_SLAVE_SCIF2_RX, 257 .addr = 0xe6c60024, 258 .chcr = CHCR_RX(XMIT_SZ_8BIT), 259 .mid_rid = 0x2a, 260 }, { 261 .slave_id = SHDMA_SLAVE_SCIF3_TX, 262 .addr = 0xe6c70020, 263 .chcr = CHCR_TX(XMIT_SZ_8BIT), 264 .mid_rid = 0x2d, 265 }, { 266 .slave_id = SHDMA_SLAVE_SCIF3_RX, 267 .addr = 0xe6c70024, 268 .chcr = CHCR_RX(XMIT_SZ_8BIT), 269 .mid_rid = 0x2e, 270 }, { 271 .slave_id = SHDMA_SLAVE_SCIF4_TX, 272 .addr = 0xe6c80020, 273 .chcr = CHCR_TX(XMIT_SZ_8BIT), 274 .mid_rid = 0x39, 275 }, { 276 .slave_id = SHDMA_SLAVE_SCIF4_RX, 277 .addr = 0xe6c80024, 278 .chcr = CHCR_RX(XMIT_SZ_8BIT), 279 .mid_rid = 0x3a, 280 }, { 281 .slave_id = SHDMA_SLAVE_SCIF5_TX, 282 .addr = 0xe6cb0020, 283 .chcr = CHCR_TX(XMIT_SZ_8BIT), 284 .mid_rid = 0x35, 285 }, { 286 .slave_id = SHDMA_SLAVE_SCIF5_RX, 287 .addr = 0xe6cb0024, 288 .chcr = CHCR_RX(XMIT_SZ_8BIT), 289 .mid_rid = 0x36, 290 }, { 291 .slave_id = SHDMA_SLAVE_SCIF6_TX, 292 .addr = 0xe6cc0020, 293 .chcr = CHCR_TX(XMIT_SZ_8BIT), 294 .mid_rid = 0x1d, 295 }, { 296 .slave_id = SHDMA_SLAVE_SCIF6_RX, 297 .addr = 0xe6cc0024, 298 .chcr = CHCR_RX(XMIT_SZ_8BIT), 299 .mid_rid = 0x1e, 300 }, { 301 .slave_id = SHDMA_SLAVE_SCIF7_TX, 302 .addr = 0xe6cd0020, 303 .chcr = CHCR_TX(XMIT_SZ_8BIT), 304 .mid_rid = 0x19, 305 }, { 306 .slave_id = SHDMA_SLAVE_SCIF7_RX, 307 .addr = 0xe6cd0024, 308 .chcr = CHCR_RX(XMIT_SZ_8BIT), 309 .mid_rid = 0x1a, 310 }, { 311 .slave_id = SHDMA_SLAVE_SCIF8_TX, 312 .addr = 0xe6c30040, 313 .chcr = CHCR_TX(XMIT_SZ_8BIT), 314 .mid_rid = 0x3d, 315 }, { 316 .slave_id = SHDMA_SLAVE_SCIF8_RX, 317 .addr = 0xe6c30060, 318 .chcr = CHCR_RX(XMIT_SZ_8BIT), 319 .mid_rid = 0x3e, 320 }, { 321 .slave_id = SHDMA_SLAVE_SDHI0_TX, 322 .addr = 0xee100030, 323 .chcr = CHCR_TX(XMIT_SZ_16BIT), 324 .mid_rid = 0xc1, 325 }, { 326 .slave_id = SHDMA_SLAVE_SDHI0_RX, 327 .addr = 0xee100030, 328 .chcr = CHCR_RX(XMIT_SZ_16BIT), 329 .mid_rid = 0xc2, 330 }, { 331 .slave_id = SHDMA_SLAVE_SDHI1_TX, 332 .addr = 0xee120030, 333 .chcr = CHCR_TX(XMIT_SZ_16BIT), 334 .mid_rid = 0xc9, 335 }, { 336 .slave_id = SHDMA_SLAVE_SDHI1_RX, 337 .addr = 0xee120030, 338 .chcr = CHCR_RX(XMIT_SZ_16BIT), 339 .mid_rid = 0xca, 340 }, { 341 .slave_id = SHDMA_SLAVE_SDHI2_TX, 342 .addr = 0xee140030, 343 .chcr = CHCR_TX(XMIT_SZ_16BIT), 344 .mid_rid = 0xcd, 345 }, { 346 .slave_id = SHDMA_SLAVE_SDHI2_RX, 347 .addr = 0xee140030, 348 .chcr = CHCR_RX(XMIT_SZ_16BIT), 349 .mid_rid = 0xce, 350 }, { 351 .slave_id = SHDMA_SLAVE_MMCIF_TX, 352 .addr = 0xe6bd0034, 353 .chcr = CHCR_TX(XMIT_SZ_32BIT), 354 .mid_rid = 0xd1, 355 }, { 356 .slave_id = SHDMA_SLAVE_MMCIF_RX, 357 .addr = 0xe6bd0034, 358 .chcr = CHCR_RX(XMIT_SZ_32BIT), 359 .mid_rid = 0xd2, 360 }, 361 }; 362 363 #define DMAE_CHANNEL(_offset) \ 364 { \ 365 .offset = _offset - 0x20, \ 366 .dmars = _offset - 0x20 + 0x40, \ 367 } 368 369 static const struct sh_dmae_channel sh73a0_dmae_channels[] = { 370 DMAE_CHANNEL(0x8000), 371 DMAE_CHANNEL(0x8080), 372 DMAE_CHANNEL(0x8100), 373 DMAE_CHANNEL(0x8180), 374 DMAE_CHANNEL(0x8200), 375 DMAE_CHANNEL(0x8280), 376 DMAE_CHANNEL(0x8300), 377 DMAE_CHANNEL(0x8380), 378 DMAE_CHANNEL(0x8400), 379 DMAE_CHANNEL(0x8480), 380 DMAE_CHANNEL(0x8500), 381 DMAE_CHANNEL(0x8580), 382 DMAE_CHANNEL(0x8600), 383 DMAE_CHANNEL(0x8680), 384 DMAE_CHANNEL(0x8700), 385 DMAE_CHANNEL(0x8780), 386 DMAE_CHANNEL(0x8800), 387 DMAE_CHANNEL(0x8880), 388 DMAE_CHANNEL(0x8900), 389 DMAE_CHANNEL(0x8980), 390 }; 391 392 static struct sh_dmae_pdata sh73a0_dmae_platform_data = { 393 .slave = sh73a0_dmae_slaves, 394 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), 395 .channel = sh73a0_dmae_channels, 396 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), 397 .ts_low_shift = TS_LOW_SHIFT, 398 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 399 .ts_high_shift = TS_HI_SHIFT, 400 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 401 .ts_shift = dma_ts_shift, 402 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 403 .dmaor_init = DMAOR_DME, 404 }; 405 406 static struct resource sh73a0_dmae_resources[] = { 407 DEFINE_RES_MEM(0xfe000020, 0x89e0), 408 { 409 .name = "error_irq", 410 .start = gic_spi(129), 411 .end = gic_spi(129), 412 .flags = IORESOURCE_IRQ, 413 }, 414 { 415 /* IRQ for channels 0-19 */ 416 .start = gic_spi(109), 417 .end = gic_spi(128), 418 .flags = IORESOURCE_IRQ, 419 }, 420 }; 421 422 static struct platform_device dma0_device = { 423 .name = "sh-dma-engine", 424 .id = 0, 425 .resource = sh73a0_dmae_resources, 426 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), 427 .dev = { 428 .platform_data = &sh73a0_dmae_platform_data, 429 }, 430 }; 431 432 /* MPDMAC */ 433 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = { 434 { 435 .slave_id = SHDMA_SLAVE_FSI2A_RX, 436 .addr = 0xec230020, 437 .chcr = CHCR_RX(XMIT_SZ_32BIT), 438 .mid_rid = 0xd6, /* CHECK ME */ 439 }, { 440 .slave_id = SHDMA_SLAVE_FSI2A_TX, 441 .addr = 0xec230024, 442 .chcr = CHCR_TX(XMIT_SZ_32BIT), 443 .mid_rid = 0xd5, /* CHECK ME */ 444 }, { 445 .slave_id = SHDMA_SLAVE_FSI2C_RX, 446 .addr = 0xec230060, 447 .chcr = CHCR_RX(XMIT_SZ_32BIT), 448 .mid_rid = 0xda, /* CHECK ME */ 449 }, { 450 .slave_id = SHDMA_SLAVE_FSI2C_TX, 451 .addr = 0xec230064, 452 .chcr = CHCR_TX(XMIT_SZ_32BIT), 453 .mid_rid = 0xd9, /* CHECK ME */ 454 }, { 455 .slave_id = SHDMA_SLAVE_FSI2B_RX, 456 .addr = 0xec240020, 457 .chcr = CHCR_RX(XMIT_SZ_32BIT), 458 .mid_rid = 0x8e, /* CHECK ME */ 459 }, { 460 .slave_id = SHDMA_SLAVE_FSI2B_TX, 461 .addr = 0xec240024, 462 .chcr = CHCR_RX(XMIT_SZ_32BIT), 463 .mid_rid = 0x8d, /* CHECK ME */ 464 }, { 465 .slave_id = SHDMA_SLAVE_FSI2D_RX, 466 .addr = 0xec240060, 467 .chcr = CHCR_RX(XMIT_SZ_32BIT), 468 .mid_rid = 0x9a, /* CHECK ME */ 469 }, 470 }; 471 472 #define MPDMA_CHANNEL(a, b, c) \ 473 { \ 474 .offset = a, \ 475 .dmars = b, \ 476 .dmars_bit = c, \ 477 .chclr_offset = (0x220 - 0x20) + a \ 478 } 479 480 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = { 481 MPDMA_CHANNEL(0x00, 0, 0), 482 MPDMA_CHANNEL(0x10, 0, 8), 483 MPDMA_CHANNEL(0x20, 4, 0), 484 MPDMA_CHANNEL(0x30, 4, 8), 485 MPDMA_CHANNEL(0x50, 8, 0), 486 MPDMA_CHANNEL(0x70, 8, 8), 487 }; 488 489 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { 490 .slave = sh73a0_mpdma_slaves, 491 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves), 492 .channel = sh73a0_mpdma_channels, 493 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels), 494 .ts_low_shift = TS_LOW_SHIFT, 495 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 496 .ts_high_shift = TS_HI_SHIFT, 497 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 498 .ts_shift = dma_ts_shift, 499 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 500 .dmaor_init = DMAOR_DME, 501 .chclr_present = 1, 502 }; 503 504 /* Resource order important! */ 505 static struct resource sh73a0_mpdma_resources[] = { 506 /* Channel registers and DMAOR */ 507 DEFINE_RES_MEM(0xec618020, 0x270), 508 /* DMARSx */ 509 DEFINE_RES_MEM(0xec619000, 0xc), 510 { 511 .name = "error_irq", 512 .start = gic_spi(181), 513 .end = gic_spi(181), 514 .flags = IORESOURCE_IRQ, 515 }, 516 { 517 /* IRQ for channels 0-5 */ 518 .start = gic_spi(175), 519 .end = gic_spi(180), 520 .flags = IORESOURCE_IRQ, 521 }, 522 }; 523 524 static struct platform_device mpdma0_device = { 525 .name = "sh-dma-engine", 526 .id = 1, 527 .resource = sh73a0_mpdma_resources, 528 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources), 529 .dev = { 530 .platform_data = &sh73a0_mpdma_platform_data, 531 }, 532 }; 533 534 static struct resource pmu_resources[] = { 535 [0] = { 536 .start = gic_spi(55), 537 .end = gic_spi(55), 538 .flags = IORESOURCE_IRQ, 539 }, 540 [1] = { 541 .start = gic_spi(56), 542 .end = gic_spi(56), 543 .flags = IORESOURCE_IRQ, 544 }, 545 }; 546 547 static struct platform_device pmu_device = { 548 .name = "arm-pmu", 549 .id = -1, 550 .num_resources = ARRAY_SIZE(pmu_resources), 551 .resource = pmu_resources, 552 }; 553 554 /* an IPMMU module for ICB */ 555 static struct resource ipmmu_resources[] = { 556 DEFINE_RES_MEM(0xfe951000, 0x100), 557 }; 558 559 static const char * const ipmmu_dev_names[] = { 560 "sh_mobile_lcdc_fb.0", 561 }; 562 563 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { 564 .dev_names = ipmmu_dev_names, 565 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), 566 }; 567 568 static struct platform_device ipmmu_device = { 569 .name = "ipmmu", 570 .id = -1, 571 .dev = { 572 .platform_data = &ipmmu_platform_data, 573 }, 574 .resource = ipmmu_resources, 575 .num_resources = ARRAY_SIZE(ipmmu_resources), 576 }; 577 578 static struct renesas_intc_irqpin_config irqpin0_platform_data = { 579 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ 580 }; 581 582 static struct resource irqpin0_resources[] = { 583 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ 584 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ 585 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ 586 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ 587 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ 588 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ 589 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ 590 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ 591 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ 592 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ 593 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ 594 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ 595 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ 596 }; 597 598 static struct platform_device irqpin0_device = { 599 .name = "renesas_intc_irqpin", 600 .id = 0, 601 .resource = irqpin0_resources, 602 .num_resources = ARRAY_SIZE(irqpin0_resources), 603 .dev = { 604 .platform_data = &irqpin0_platform_data, 605 }, 606 }; 607 608 static struct renesas_intc_irqpin_config irqpin1_platform_data = { 609 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ 610 .control_parent = true, /* Disable spurious IRQ10 */ 611 }; 612 613 static struct resource irqpin1_resources[] = { 614 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ 615 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ 616 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ 617 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ 618 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ 619 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ 620 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ 621 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ 622 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ 623 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ 624 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ 625 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ 626 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ 627 }; 628 629 static struct platform_device irqpin1_device = { 630 .name = "renesas_intc_irqpin", 631 .id = 1, 632 .resource = irqpin1_resources, 633 .num_resources = ARRAY_SIZE(irqpin1_resources), 634 .dev = { 635 .platform_data = &irqpin1_platform_data, 636 }, 637 }; 638 639 static struct renesas_intc_irqpin_config irqpin2_platform_data = { 640 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ 641 }; 642 643 static struct resource irqpin2_resources[] = { 644 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ 645 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ 646 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ 647 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ 648 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ 649 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ 650 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ 651 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ 652 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ 653 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ 654 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ 655 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ 656 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ 657 }; 658 659 static struct platform_device irqpin2_device = { 660 .name = "renesas_intc_irqpin", 661 .id = 2, 662 .resource = irqpin2_resources, 663 .num_resources = ARRAY_SIZE(irqpin2_resources), 664 .dev = { 665 .platform_data = &irqpin2_platform_data, 666 }, 667 }; 668 669 static struct renesas_intc_irqpin_config irqpin3_platform_data = { 670 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ 671 }; 672 673 static struct resource irqpin3_resources[] = { 674 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ 675 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ 676 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ 677 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ 678 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ 679 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ 680 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ 681 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ 682 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ 683 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ 684 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ 685 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ 686 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ 687 }; 688 689 static struct platform_device irqpin3_device = { 690 .name = "renesas_intc_irqpin", 691 .id = 3, 692 .resource = irqpin3_resources, 693 .num_resources = ARRAY_SIZE(irqpin3_resources), 694 .dev = { 695 .platform_data = &irqpin3_platform_data, 696 }, 697 }; 698 699 static struct platform_device *sh73a0_devices_dt[] __initdata = { 700 &cmt1_device, 701 }; 702 703 static struct platform_device *sh73a0_early_devices[] __initdata = { 704 &scif0_device, 705 &scif1_device, 706 &scif2_device, 707 &scif3_device, 708 &scif4_device, 709 &scif5_device, 710 &scif6_device, 711 &scif7_device, 712 &scif8_device, 713 &tmu0_device, 714 &ipmmu_device, 715 }; 716 717 static struct platform_device *sh73a0_late_devices[] __initdata = { 718 &i2c0_device, 719 &i2c1_device, 720 &i2c2_device, 721 &i2c3_device, 722 &i2c4_device, 723 &dma0_device, 724 &mpdma0_device, 725 &pmu_device, 726 &irqpin0_device, 727 &irqpin1_device, 728 &irqpin2_device, 729 &irqpin3_device, 730 }; 731 732 #define SRCR2 IOMEM(0xe61580b0) 733 734 void __init sh73a0_add_standard_devices(void) 735 { 736 /* Clear software reset bit on SY-DMAC module */ 737 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); 738 739 platform_add_devices(sh73a0_devices_dt, 740 ARRAY_SIZE(sh73a0_devices_dt)); 741 platform_add_devices(sh73a0_early_devices, 742 ARRAY_SIZE(sh73a0_early_devices)); 743 platform_add_devices(sh73a0_late_devices, 744 ARRAY_SIZE(sh73a0_late_devices)); 745 } 746 747 void __init sh73a0_init_delay(void) 748 { 749 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ 750 } 751 752 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 753 void __init __weak sh73a0_register_twd(void) { } 754 755 void __init sh73a0_earlytimer_init(void) 756 { 757 sh73a0_init_delay(); 758 sh73a0_clock_init(); 759 shmobile_earlytimer_init(); 760 sh73a0_register_twd(); 761 } 762 763 void __init sh73a0_add_early_devices(void) 764 { 765 early_platform_add_devices(sh73a0_devices_dt, 766 ARRAY_SIZE(sh73a0_devices_dt)); 767 early_platform_add_devices(sh73a0_early_devices, 768 ARRAY_SIZE(sh73a0_early_devices)); 769 770 /* setup early console here as well */ 771 shmobile_setup_console(); 772 } 773 774 #ifdef CONFIG_USE_OF 775 776 void __init sh73a0_add_standard_devices_dt(void) 777 { 778 struct platform_device_info devinfo = { .name = "cpufreq-dt", .id = -1, }; 779 780 /* clocks are setup late during boot in the case of DT */ 781 sh73a0_clock_init(); 782 783 platform_add_devices(sh73a0_devices_dt, 784 ARRAY_SIZE(sh73a0_devices_dt)); 785 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 786 787 /* Instantiate cpufreq-dt */ 788 platform_device_register_full(&devinfo); 789 } 790 791 static const char *sh73a0_boards_compat_dt[] __initdata = { 792 "renesas,sh73a0", 793 NULL, 794 }; 795 796 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") 797 .smp = smp_ops(sh73a0_smp_ops), 798 .map_io = sh73a0_map_io, 799 .init_early = sh73a0_init_delay, 800 .nr_irqs = NR_IRQS_LEGACY, 801 .init_machine = sh73a0_add_standard_devices_dt, 802 .dt_compat = sh73a0_boards_compat_dt, 803 MACHINE_END 804 #endif /* CONFIG_USE_OF */ 805