1 /* 2 * sh73a0 processor support 3 * 4 * Copyright (C) 2010 Takashi Yoshii 5 * Copyright (C) 2010 Magnus Damm 6 * Copyright (C) 2008 Yoshihiro Shimoda 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/platform_device.h> 26 #include <linux/of_platform.h> 27 #include <linux/delay.h> 28 #include <linux/input.h> 29 #include <linux/io.h> 30 #include <linux/serial_sci.h> 31 #include <linux/sh_dma.h> 32 #include <linux/sh_intc.h> 33 #include <linux/sh_timer.h> 34 #include <linux/platform_data/sh_ipmmu.h> 35 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 36 #include <mach/dma-register.h> 37 #include <mach/irqs.h> 38 #include <mach/sh73a0.h> 39 #include <mach/common.h> 40 #include <asm/mach-types.h> 41 #include <asm/mach/map.h> 42 #include <asm/mach/arch.h> 43 #include <asm/mach/time.h> 44 45 static struct map_desc sh73a0_io_desc[] __initdata = { 46 /* create a 1:1 entity map for 0xe6xxxxxx 47 * used by CPGA, INTC and PFC. 48 */ 49 { 50 .virtual = 0xe6000000, 51 .pfn = __phys_to_pfn(0xe6000000), 52 .length = 256 << 20, 53 .type = MT_DEVICE_NONSHARED 54 }, 55 }; 56 57 void __init sh73a0_map_io(void) 58 { 59 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); 60 } 61 62 /* PFC */ 63 static struct resource pfc_resources[] __initdata = { 64 DEFINE_RES_MEM(0xe6050000, 0x8000), 65 DEFINE_RES_MEM(0xe605801c, 0x000c), 66 }; 67 68 void __init sh73a0_pinmux_init(void) 69 { 70 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources, 71 ARRAY_SIZE(pfc_resources)); 72 } 73 74 /* SCIF */ 75 #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \ 76 static struct plat_sci_port scif##index##_platform_data = { \ 77 .type = scif_type, \ 78 .flags = UPF_BOOT_AUTOCONF, \ 79 .scscr = SCSCR_RE | SCSCR_TE, \ 80 }; \ 81 \ 82 static struct resource scif##index##_resources[] = { \ 83 DEFINE_RES_MEM(baseaddr, 0x100), \ 84 DEFINE_RES_IRQ(irq), \ 85 }; \ 86 \ 87 static struct platform_device scif##index##_device = { \ 88 .name = "sh-sci", \ 89 .id = index, \ 90 .resource = scif##index##_resources, \ 91 .num_resources = ARRAY_SIZE(scif##index##_resources), \ 92 .dev = { \ 93 .platform_data = &scif##index##_platform_data, \ 94 }, \ 95 } 96 97 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72)); 98 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); 99 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); 100 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); 101 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); 102 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); 103 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); 104 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); 105 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); 106 107 static struct sh_timer_config cmt1_platform_data = { 108 .channels_mask = 0x3f, 109 }; 110 111 static struct resource cmt1_resources[] = { 112 DEFINE_RES_MEM(0xe6138000, 0x200), 113 DEFINE_RES_IRQ(gic_spi(65)), 114 }; 115 116 static struct platform_device cmt1_device = { 117 .name = "sh-cmt-48", 118 .id = 1, 119 .dev = { 120 .platform_data = &cmt1_platform_data, 121 }, 122 .resource = cmt1_resources, 123 .num_resources = ARRAY_SIZE(cmt1_resources), 124 }; 125 126 /* TMU */ 127 static struct sh_timer_config tmu00_platform_data = { 128 .name = "TMU00", 129 .channel_offset = 0x4, 130 .timer_bit = 0, 131 .clockevent_rating = 200, 132 }; 133 134 static struct resource tmu00_resources[] = { 135 [0] = DEFINE_RES_MEM(0xfff60008, 0xc), 136 [1] = { 137 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ 138 .flags = IORESOURCE_IRQ, 139 }, 140 }; 141 142 static struct platform_device tmu00_device = { 143 .name = "sh_tmu", 144 .id = 0, 145 .dev = { 146 .platform_data = &tmu00_platform_data, 147 }, 148 .resource = tmu00_resources, 149 .num_resources = ARRAY_SIZE(tmu00_resources), 150 }; 151 152 static struct sh_timer_config tmu01_platform_data = { 153 .name = "TMU01", 154 .channel_offset = 0x10, 155 .timer_bit = 1, 156 .clocksource_rating = 200, 157 }; 158 159 static struct resource tmu01_resources[] = { 160 [0] = DEFINE_RES_MEM(0xfff60014, 0xc), 161 [1] = { 162 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ 163 .flags = IORESOURCE_IRQ, 164 }, 165 }; 166 167 static struct platform_device tmu01_device = { 168 .name = "sh_tmu", 169 .id = 1, 170 .dev = { 171 .platform_data = &tmu01_platform_data, 172 }, 173 .resource = tmu01_resources, 174 .num_resources = ARRAY_SIZE(tmu01_resources), 175 }; 176 177 static struct resource i2c0_resources[] = { 178 [0] = DEFINE_RES_MEM(0xe6820000, 0x426), 179 [1] = { 180 .start = gic_spi(167), 181 .end = gic_spi(170), 182 .flags = IORESOURCE_IRQ, 183 }, 184 }; 185 186 static struct resource i2c1_resources[] = { 187 [0] = DEFINE_RES_MEM(0xe6822000, 0x426), 188 [1] = { 189 .start = gic_spi(51), 190 .end = gic_spi(54), 191 .flags = IORESOURCE_IRQ, 192 }, 193 }; 194 195 static struct resource i2c2_resources[] = { 196 [0] = DEFINE_RES_MEM(0xe6824000, 0x426), 197 [1] = { 198 .start = gic_spi(171), 199 .end = gic_spi(174), 200 .flags = IORESOURCE_IRQ, 201 }, 202 }; 203 204 static struct resource i2c3_resources[] = { 205 [0] = DEFINE_RES_MEM(0xe6826000, 0x426), 206 [1] = { 207 .start = gic_spi(183), 208 .end = gic_spi(186), 209 .flags = IORESOURCE_IRQ, 210 }, 211 }; 212 213 static struct resource i2c4_resources[] = { 214 [0] = DEFINE_RES_MEM(0xe6828000, 0x426), 215 [1] = { 216 .start = gic_spi(187), 217 .end = gic_spi(190), 218 .flags = IORESOURCE_IRQ, 219 }, 220 }; 221 222 static struct platform_device i2c0_device = { 223 .name = "i2c-sh_mobile", 224 .id = 0, 225 .resource = i2c0_resources, 226 .num_resources = ARRAY_SIZE(i2c0_resources), 227 }; 228 229 static struct platform_device i2c1_device = { 230 .name = "i2c-sh_mobile", 231 .id = 1, 232 .resource = i2c1_resources, 233 .num_resources = ARRAY_SIZE(i2c1_resources), 234 }; 235 236 static struct platform_device i2c2_device = { 237 .name = "i2c-sh_mobile", 238 .id = 2, 239 .resource = i2c2_resources, 240 .num_resources = ARRAY_SIZE(i2c2_resources), 241 }; 242 243 static struct platform_device i2c3_device = { 244 .name = "i2c-sh_mobile", 245 .id = 3, 246 .resource = i2c3_resources, 247 .num_resources = ARRAY_SIZE(i2c3_resources), 248 }; 249 250 static struct platform_device i2c4_device = { 251 .name = "i2c-sh_mobile", 252 .id = 4, 253 .resource = i2c4_resources, 254 .num_resources = ARRAY_SIZE(i2c4_resources), 255 }; 256 257 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { 258 { 259 .slave_id = SHDMA_SLAVE_SCIF0_TX, 260 .addr = 0xe6c40020, 261 .chcr = CHCR_TX(XMIT_SZ_8BIT), 262 .mid_rid = 0x21, 263 }, { 264 .slave_id = SHDMA_SLAVE_SCIF0_RX, 265 .addr = 0xe6c40024, 266 .chcr = CHCR_RX(XMIT_SZ_8BIT), 267 .mid_rid = 0x22, 268 }, { 269 .slave_id = SHDMA_SLAVE_SCIF1_TX, 270 .addr = 0xe6c50020, 271 .chcr = CHCR_TX(XMIT_SZ_8BIT), 272 .mid_rid = 0x25, 273 }, { 274 .slave_id = SHDMA_SLAVE_SCIF1_RX, 275 .addr = 0xe6c50024, 276 .chcr = CHCR_RX(XMIT_SZ_8BIT), 277 .mid_rid = 0x26, 278 }, { 279 .slave_id = SHDMA_SLAVE_SCIF2_TX, 280 .addr = 0xe6c60020, 281 .chcr = CHCR_TX(XMIT_SZ_8BIT), 282 .mid_rid = 0x29, 283 }, { 284 .slave_id = SHDMA_SLAVE_SCIF2_RX, 285 .addr = 0xe6c60024, 286 .chcr = CHCR_RX(XMIT_SZ_8BIT), 287 .mid_rid = 0x2a, 288 }, { 289 .slave_id = SHDMA_SLAVE_SCIF3_TX, 290 .addr = 0xe6c70020, 291 .chcr = CHCR_TX(XMIT_SZ_8BIT), 292 .mid_rid = 0x2d, 293 }, { 294 .slave_id = SHDMA_SLAVE_SCIF3_RX, 295 .addr = 0xe6c70024, 296 .chcr = CHCR_RX(XMIT_SZ_8BIT), 297 .mid_rid = 0x2e, 298 }, { 299 .slave_id = SHDMA_SLAVE_SCIF4_TX, 300 .addr = 0xe6c80020, 301 .chcr = CHCR_TX(XMIT_SZ_8BIT), 302 .mid_rid = 0x39, 303 }, { 304 .slave_id = SHDMA_SLAVE_SCIF4_RX, 305 .addr = 0xe6c80024, 306 .chcr = CHCR_RX(XMIT_SZ_8BIT), 307 .mid_rid = 0x3a, 308 }, { 309 .slave_id = SHDMA_SLAVE_SCIF5_TX, 310 .addr = 0xe6cb0020, 311 .chcr = CHCR_TX(XMIT_SZ_8BIT), 312 .mid_rid = 0x35, 313 }, { 314 .slave_id = SHDMA_SLAVE_SCIF5_RX, 315 .addr = 0xe6cb0024, 316 .chcr = CHCR_RX(XMIT_SZ_8BIT), 317 .mid_rid = 0x36, 318 }, { 319 .slave_id = SHDMA_SLAVE_SCIF6_TX, 320 .addr = 0xe6cc0020, 321 .chcr = CHCR_TX(XMIT_SZ_8BIT), 322 .mid_rid = 0x1d, 323 }, { 324 .slave_id = SHDMA_SLAVE_SCIF6_RX, 325 .addr = 0xe6cc0024, 326 .chcr = CHCR_RX(XMIT_SZ_8BIT), 327 .mid_rid = 0x1e, 328 }, { 329 .slave_id = SHDMA_SLAVE_SCIF7_TX, 330 .addr = 0xe6cd0020, 331 .chcr = CHCR_TX(XMIT_SZ_8BIT), 332 .mid_rid = 0x19, 333 }, { 334 .slave_id = SHDMA_SLAVE_SCIF7_RX, 335 .addr = 0xe6cd0024, 336 .chcr = CHCR_RX(XMIT_SZ_8BIT), 337 .mid_rid = 0x1a, 338 }, { 339 .slave_id = SHDMA_SLAVE_SCIF8_TX, 340 .addr = 0xe6c30040, 341 .chcr = CHCR_TX(XMIT_SZ_8BIT), 342 .mid_rid = 0x3d, 343 }, { 344 .slave_id = SHDMA_SLAVE_SCIF8_RX, 345 .addr = 0xe6c30060, 346 .chcr = CHCR_RX(XMIT_SZ_8BIT), 347 .mid_rid = 0x3e, 348 }, { 349 .slave_id = SHDMA_SLAVE_SDHI0_TX, 350 .addr = 0xee100030, 351 .chcr = CHCR_TX(XMIT_SZ_16BIT), 352 .mid_rid = 0xc1, 353 }, { 354 .slave_id = SHDMA_SLAVE_SDHI0_RX, 355 .addr = 0xee100030, 356 .chcr = CHCR_RX(XMIT_SZ_16BIT), 357 .mid_rid = 0xc2, 358 }, { 359 .slave_id = SHDMA_SLAVE_SDHI1_TX, 360 .addr = 0xee120030, 361 .chcr = CHCR_TX(XMIT_SZ_16BIT), 362 .mid_rid = 0xc9, 363 }, { 364 .slave_id = SHDMA_SLAVE_SDHI1_RX, 365 .addr = 0xee120030, 366 .chcr = CHCR_RX(XMIT_SZ_16BIT), 367 .mid_rid = 0xca, 368 }, { 369 .slave_id = SHDMA_SLAVE_SDHI2_TX, 370 .addr = 0xee140030, 371 .chcr = CHCR_TX(XMIT_SZ_16BIT), 372 .mid_rid = 0xcd, 373 }, { 374 .slave_id = SHDMA_SLAVE_SDHI2_RX, 375 .addr = 0xee140030, 376 .chcr = CHCR_RX(XMIT_SZ_16BIT), 377 .mid_rid = 0xce, 378 }, { 379 .slave_id = SHDMA_SLAVE_MMCIF_TX, 380 .addr = 0xe6bd0034, 381 .chcr = CHCR_TX(XMIT_SZ_32BIT), 382 .mid_rid = 0xd1, 383 }, { 384 .slave_id = SHDMA_SLAVE_MMCIF_RX, 385 .addr = 0xe6bd0034, 386 .chcr = CHCR_RX(XMIT_SZ_32BIT), 387 .mid_rid = 0xd2, 388 }, 389 }; 390 391 #define DMAE_CHANNEL(_offset) \ 392 { \ 393 .offset = _offset - 0x20, \ 394 .dmars = _offset - 0x20 + 0x40, \ 395 } 396 397 static const struct sh_dmae_channel sh73a0_dmae_channels[] = { 398 DMAE_CHANNEL(0x8000), 399 DMAE_CHANNEL(0x8080), 400 DMAE_CHANNEL(0x8100), 401 DMAE_CHANNEL(0x8180), 402 DMAE_CHANNEL(0x8200), 403 DMAE_CHANNEL(0x8280), 404 DMAE_CHANNEL(0x8300), 405 DMAE_CHANNEL(0x8380), 406 DMAE_CHANNEL(0x8400), 407 DMAE_CHANNEL(0x8480), 408 DMAE_CHANNEL(0x8500), 409 DMAE_CHANNEL(0x8580), 410 DMAE_CHANNEL(0x8600), 411 DMAE_CHANNEL(0x8680), 412 DMAE_CHANNEL(0x8700), 413 DMAE_CHANNEL(0x8780), 414 DMAE_CHANNEL(0x8800), 415 DMAE_CHANNEL(0x8880), 416 DMAE_CHANNEL(0x8900), 417 DMAE_CHANNEL(0x8980), 418 }; 419 420 static struct sh_dmae_pdata sh73a0_dmae_platform_data = { 421 .slave = sh73a0_dmae_slaves, 422 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), 423 .channel = sh73a0_dmae_channels, 424 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), 425 .ts_low_shift = TS_LOW_SHIFT, 426 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 427 .ts_high_shift = TS_HI_SHIFT, 428 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 429 .ts_shift = dma_ts_shift, 430 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 431 .dmaor_init = DMAOR_DME, 432 }; 433 434 static struct resource sh73a0_dmae_resources[] = { 435 DEFINE_RES_MEM(0xfe000020, 0x89e0), 436 { 437 .name = "error_irq", 438 .start = gic_spi(129), 439 .end = gic_spi(129), 440 .flags = IORESOURCE_IRQ, 441 }, 442 { 443 /* IRQ for channels 0-19 */ 444 .start = gic_spi(109), 445 .end = gic_spi(128), 446 .flags = IORESOURCE_IRQ, 447 }, 448 }; 449 450 static struct platform_device dma0_device = { 451 .name = "sh-dma-engine", 452 .id = 0, 453 .resource = sh73a0_dmae_resources, 454 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), 455 .dev = { 456 .platform_data = &sh73a0_dmae_platform_data, 457 }, 458 }; 459 460 /* MPDMAC */ 461 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = { 462 { 463 .slave_id = SHDMA_SLAVE_FSI2A_RX, 464 .addr = 0xec230020, 465 .chcr = CHCR_RX(XMIT_SZ_32BIT), 466 .mid_rid = 0xd6, /* CHECK ME */ 467 }, { 468 .slave_id = SHDMA_SLAVE_FSI2A_TX, 469 .addr = 0xec230024, 470 .chcr = CHCR_TX(XMIT_SZ_32BIT), 471 .mid_rid = 0xd5, /* CHECK ME */ 472 }, { 473 .slave_id = SHDMA_SLAVE_FSI2C_RX, 474 .addr = 0xec230060, 475 .chcr = CHCR_RX(XMIT_SZ_32BIT), 476 .mid_rid = 0xda, /* CHECK ME */ 477 }, { 478 .slave_id = SHDMA_SLAVE_FSI2C_TX, 479 .addr = 0xec230064, 480 .chcr = CHCR_TX(XMIT_SZ_32BIT), 481 .mid_rid = 0xd9, /* CHECK ME */ 482 }, { 483 .slave_id = SHDMA_SLAVE_FSI2B_RX, 484 .addr = 0xec240020, 485 .chcr = CHCR_RX(XMIT_SZ_32BIT), 486 .mid_rid = 0x8e, /* CHECK ME */ 487 }, { 488 .slave_id = SHDMA_SLAVE_FSI2B_TX, 489 .addr = 0xec240024, 490 .chcr = CHCR_RX(XMIT_SZ_32BIT), 491 .mid_rid = 0x8d, /* CHECK ME */ 492 }, { 493 .slave_id = SHDMA_SLAVE_FSI2D_RX, 494 .addr = 0xec240060, 495 .chcr = CHCR_RX(XMIT_SZ_32BIT), 496 .mid_rid = 0x9a, /* CHECK ME */ 497 }, 498 }; 499 500 #define MPDMA_CHANNEL(a, b, c) \ 501 { \ 502 .offset = a, \ 503 .dmars = b, \ 504 .dmars_bit = c, \ 505 .chclr_offset = (0x220 - 0x20) + a \ 506 } 507 508 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = { 509 MPDMA_CHANNEL(0x00, 0, 0), 510 MPDMA_CHANNEL(0x10, 0, 8), 511 MPDMA_CHANNEL(0x20, 4, 0), 512 MPDMA_CHANNEL(0x30, 4, 8), 513 MPDMA_CHANNEL(0x50, 8, 0), 514 MPDMA_CHANNEL(0x70, 8, 8), 515 }; 516 517 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { 518 .slave = sh73a0_mpdma_slaves, 519 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves), 520 .channel = sh73a0_mpdma_channels, 521 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels), 522 .ts_low_shift = TS_LOW_SHIFT, 523 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 524 .ts_high_shift = TS_HI_SHIFT, 525 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 526 .ts_shift = dma_ts_shift, 527 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 528 .dmaor_init = DMAOR_DME, 529 .chclr_present = 1, 530 }; 531 532 /* Resource order important! */ 533 static struct resource sh73a0_mpdma_resources[] = { 534 /* Channel registers and DMAOR */ 535 DEFINE_RES_MEM(0xec618020, 0x270), 536 /* DMARSx */ 537 DEFINE_RES_MEM(0xec619000, 0xc), 538 { 539 .name = "error_irq", 540 .start = gic_spi(181), 541 .end = gic_spi(181), 542 .flags = IORESOURCE_IRQ, 543 }, 544 { 545 /* IRQ for channels 0-5 */ 546 .start = gic_spi(175), 547 .end = gic_spi(180), 548 .flags = IORESOURCE_IRQ, 549 }, 550 }; 551 552 static struct platform_device mpdma0_device = { 553 .name = "sh-dma-engine", 554 .id = 1, 555 .resource = sh73a0_mpdma_resources, 556 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources), 557 .dev = { 558 .platform_data = &sh73a0_mpdma_platform_data, 559 }, 560 }; 561 562 static struct resource pmu_resources[] = { 563 [0] = { 564 .start = gic_spi(55), 565 .end = gic_spi(55), 566 .flags = IORESOURCE_IRQ, 567 }, 568 [1] = { 569 .start = gic_spi(56), 570 .end = gic_spi(56), 571 .flags = IORESOURCE_IRQ, 572 }, 573 }; 574 575 static struct platform_device pmu_device = { 576 .name = "arm-pmu", 577 .id = -1, 578 .num_resources = ARRAY_SIZE(pmu_resources), 579 .resource = pmu_resources, 580 }; 581 582 /* an IPMMU module for ICB */ 583 static struct resource ipmmu_resources[] = { 584 DEFINE_RES_MEM(0xfe951000, 0x100), 585 }; 586 587 static const char * const ipmmu_dev_names[] = { 588 "sh_mobile_lcdc_fb.0", 589 }; 590 591 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { 592 .dev_names = ipmmu_dev_names, 593 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), 594 }; 595 596 static struct platform_device ipmmu_device = { 597 .name = "ipmmu", 598 .id = -1, 599 .dev = { 600 .platform_data = &ipmmu_platform_data, 601 }, 602 .resource = ipmmu_resources, 603 .num_resources = ARRAY_SIZE(ipmmu_resources), 604 }; 605 606 static struct renesas_intc_irqpin_config irqpin0_platform_data = { 607 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ 608 }; 609 610 static struct resource irqpin0_resources[] = { 611 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ 612 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ 613 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ 614 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ 615 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ 616 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ 617 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ 618 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ 619 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ 620 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ 621 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ 622 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ 623 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ 624 }; 625 626 static struct platform_device irqpin0_device = { 627 .name = "renesas_intc_irqpin", 628 .id = 0, 629 .resource = irqpin0_resources, 630 .num_resources = ARRAY_SIZE(irqpin0_resources), 631 .dev = { 632 .platform_data = &irqpin0_platform_data, 633 }, 634 }; 635 636 static struct renesas_intc_irqpin_config irqpin1_platform_data = { 637 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ 638 .control_parent = true, /* Disable spurious IRQ10 */ 639 }; 640 641 static struct resource irqpin1_resources[] = { 642 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ 643 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ 644 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ 645 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ 646 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ 647 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ 648 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ 649 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ 650 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ 651 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ 652 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ 653 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ 654 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ 655 }; 656 657 static struct platform_device irqpin1_device = { 658 .name = "renesas_intc_irqpin", 659 .id = 1, 660 .resource = irqpin1_resources, 661 .num_resources = ARRAY_SIZE(irqpin1_resources), 662 .dev = { 663 .platform_data = &irqpin1_platform_data, 664 }, 665 }; 666 667 static struct renesas_intc_irqpin_config irqpin2_platform_data = { 668 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ 669 }; 670 671 static struct resource irqpin2_resources[] = { 672 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ 673 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ 674 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ 675 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ 676 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ 677 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ 678 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ 679 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ 680 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ 681 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ 682 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ 683 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ 684 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ 685 }; 686 687 static struct platform_device irqpin2_device = { 688 .name = "renesas_intc_irqpin", 689 .id = 2, 690 .resource = irqpin2_resources, 691 .num_resources = ARRAY_SIZE(irqpin2_resources), 692 .dev = { 693 .platform_data = &irqpin2_platform_data, 694 }, 695 }; 696 697 static struct renesas_intc_irqpin_config irqpin3_platform_data = { 698 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ 699 }; 700 701 static struct resource irqpin3_resources[] = { 702 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ 703 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ 704 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ 705 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ 706 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ 707 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ 708 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ 709 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ 710 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ 711 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ 712 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ 713 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ 714 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ 715 }; 716 717 static struct platform_device irqpin3_device = { 718 .name = "renesas_intc_irqpin", 719 .id = 3, 720 .resource = irqpin3_resources, 721 .num_resources = ARRAY_SIZE(irqpin3_resources), 722 .dev = { 723 .platform_data = &irqpin3_platform_data, 724 }, 725 }; 726 727 static struct platform_device *sh73a0_devices_dt[] __initdata = { 728 &scif0_device, 729 &scif1_device, 730 &scif2_device, 731 &scif3_device, 732 &scif4_device, 733 &scif5_device, 734 &scif6_device, 735 &scif7_device, 736 &scif8_device, 737 &cmt1_device, 738 }; 739 740 static struct platform_device *sh73a0_early_devices[] __initdata = { 741 &tmu00_device, 742 &tmu01_device, 743 &ipmmu_device, 744 }; 745 746 static struct platform_device *sh73a0_late_devices[] __initdata = { 747 &i2c0_device, 748 &i2c1_device, 749 &i2c2_device, 750 &i2c3_device, 751 &i2c4_device, 752 &dma0_device, 753 &mpdma0_device, 754 &pmu_device, 755 &irqpin0_device, 756 &irqpin1_device, 757 &irqpin2_device, 758 &irqpin3_device, 759 }; 760 761 #define SRCR2 IOMEM(0xe61580b0) 762 763 void __init sh73a0_add_standard_devices(void) 764 { 765 /* Clear software reset bit on SY-DMAC module */ 766 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); 767 768 platform_add_devices(sh73a0_devices_dt, 769 ARRAY_SIZE(sh73a0_devices_dt)); 770 platform_add_devices(sh73a0_early_devices, 771 ARRAY_SIZE(sh73a0_early_devices)); 772 platform_add_devices(sh73a0_late_devices, 773 ARRAY_SIZE(sh73a0_late_devices)); 774 } 775 776 void __init sh73a0_init_delay(void) 777 { 778 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ 779 } 780 781 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 782 void __init __weak sh73a0_register_twd(void) { } 783 784 void __init sh73a0_earlytimer_init(void) 785 { 786 sh73a0_init_delay(); 787 sh73a0_clock_init(); 788 shmobile_earlytimer_init(); 789 sh73a0_register_twd(); 790 } 791 792 void __init sh73a0_add_early_devices(void) 793 { 794 early_platform_add_devices(sh73a0_devices_dt, 795 ARRAY_SIZE(sh73a0_devices_dt)); 796 early_platform_add_devices(sh73a0_early_devices, 797 ARRAY_SIZE(sh73a0_early_devices)); 798 799 /* setup early console here as well */ 800 shmobile_setup_console(); 801 } 802 803 #ifdef CONFIG_USE_OF 804 805 void __init sh73a0_add_standard_devices_dt(void) 806 { 807 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; 808 809 /* clocks are setup late during boot in the case of DT */ 810 sh73a0_clock_init(); 811 812 platform_add_devices(sh73a0_devices_dt, 813 ARRAY_SIZE(sh73a0_devices_dt)); 814 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 815 816 /* Instantiate cpufreq-cpu0 */ 817 platform_device_register_full(&devinfo); 818 } 819 820 static const char *sh73a0_boards_compat_dt[] __initdata = { 821 "renesas,sh73a0", 822 NULL, 823 }; 824 825 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") 826 .smp = smp_ops(sh73a0_smp_ops), 827 .map_io = sh73a0_map_io, 828 .init_early = sh73a0_init_delay, 829 .nr_irqs = NR_IRQS_LEGACY, 830 .init_machine = sh73a0_add_standard_devices_dt, 831 .dt_compat = sh73a0_boards_compat_dt, 832 MACHINE_END 833 #endif /* CONFIG_USE_OF */ 834