1 /* 2 * sh73a0 processor support 3 * 4 * Copyright (C) 2010 Takashi Yoshii 5 * Copyright (C) 2010 Magnus Damm 6 * Copyright (C) 2008 Yoshihiro Shimoda 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/platform_device.h> 26 #include <linux/of_platform.h> 27 #include <linux/delay.h> 28 #include <linux/input.h> 29 #include <linux/io.h> 30 #include <linux/serial_sci.h> 31 #include <linux/sh_dma.h> 32 #include <linux/sh_timer.h> 33 #include <linux/platform_data/sh_ipmmu.h> 34 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 35 #include <mach/dma-register.h> 36 #include <mach/irqs.h> 37 #include <mach/sh73a0.h> 38 #include <mach/common.h> 39 #include <asm/mach-types.h> 40 #include <asm/mach/map.h> 41 #include <asm/mach/arch.h> 42 #include <asm/mach/time.h> 43 44 static struct map_desc sh73a0_io_desc[] __initdata = { 45 /* create a 1:1 entity map for 0xe6xxxxxx 46 * used by CPGA, INTC and PFC. 47 */ 48 { 49 .virtual = 0xe6000000, 50 .pfn = __phys_to_pfn(0xe6000000), 51 .length = 256 << 20, 52 .type = MT_DEVICE_NONSHARED 53 }, 54 }; 55 56 void __init sh73a0_map_io(void) 57 { 58 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); 59 } 60 61 /* PFC */ 62 static struct resource pfc_resources[] __initdata = { 63 DEFINE_RES_MEM(0xe6050000, 0x8000), 64 DEFINE_RES_MEM(0xe605801c, 0x000c), 65 }; 66 67 void __init sh73a0_pinmux_init(void) 68 { 69 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources, 70 ARRAY_SIZE(pfc_resources)); 71 } 72 73 /* SCIF */ 74 #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \ 75 static struct plat_sci_port scif##index##_platform_data = { \ 76 .type = scif_type, \ 77 .flags = UPF_BOOT_AUTOCONF, \ 78 .scscr = SCSCR_RE | SCSCR_TE, \ 79 }; \ 80 \ 81 static struct resource scif##index##_resources[] = { \ 82 DEFINE_RES_MEM(baseaddr, 0x100), \ 83 DEFINE_RES_IRQ(irq), \ 84 }; \ 85 \ 86 static struct platform_device scif##index##_device = { \ 87 .name = "sh-sci", \ 88 .id = index, \ 89 .resource = scif##index##_resources, \ 90 .num_resources = ARRAY_SIZE(scif##index##_resources), \ 91 .dev = { \ 92 .platform_data = &scif##index##_platform_data, \ 93 }, \ 94 } 95 96 SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72)); 97 SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); 98 SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); 99 SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); 100 SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); 101 SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); 102 SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); 103 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); 104 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); 105 106 static struct sh_timer_config cmt1_platform_data = { 107 .channels_mask = 0x3f, 108 }; 109 110 static struct resource cmt1_resources[] = { 111 DEFINE_RES_MEM(0xe6138000, 0x200), 112 DEFINE_RES_IRQ(gic_spi(65)), 113 }; 114 115 static struct platform_device cmt1_device = { 116 .name = "sh-cmt-48", 117 .id = 1, 118 .dev = { 119 .platform_data = &cmt1_platform_data, 120 }, 121 .resource = cmt1_resources, 122 .num_resources = ARRAY_SIZE(cmt1_resources), 123 }; 124 125 /* TMU */ 126 static struct sh_timer_config tmu0_platform_data = { 127 .channels_mask = 7, 128 }; 129 130 static struct resource tmu0_resources[] = { 131 DEFINE_RES_MEM(0xfff60000, 0x2c), 132 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)), 133 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)), 134 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)), 135 }; 136 137 static struct platform_device tmu0_device = { 138 .name = "sh-tmu", 139 .id = 0, 140 .dev = { 141 .platform_data = &tmu0_platform_data, 142 }, 143 .resource = tmu0_resources, 144 .num_resources = ARRAY_SIZE(tmu0_resources), 145 }; 146 147 static struct resource i2c0_resources[] = { 148 [0] = DEFINE_RES_MEM(0xe6820000, 0x426), 149 [1] = { 150 .start = gic_spi(167), 151 .end = gic_spi(170), 152 .flags = IORESOURCE_IRQ, 153 }, 154 }; 155 156 static struct resource i2c1_resources[] = { 157 [0] = DEFINE_RES_MEM(0xe6822000, 0x426), 158 [1] = { 159 .start = gic_spi(51), 160 .end = gic_spi(54), 161 .flags = IORESOURCE_IRQ, 162 }, 163 }; 164 165 static struct resource i2c2_resources[] = { 166 [0] = DEFINE_RES_MEM(0xe6824000, 0x426), 167 [1] = { 168 .start = gic_spi(171), 169 .end = gic_spi(174), 170 .flags = IORESOURCE_IRQ, 171 }, 172 }; 173 174 static struct resource i2c3_resources[] = { 175 [0] = DEFINE_RES_MEM(0xe6826000, 0x426), 176 [1] = { 177 .start = gic_spi(183), 178 .end = gic_spi(186), 179 .flags = IORESOURCE_IRQ, 180 }, 181 }; 182 183 static struct resource i2c4_resources[] = { 184 [0] = DEFINE_RES_MEM(0xe6828000, 0x426), 185 [1] = { 186 .start = gic_spi(187), 187 .end = gic_spi(190), 188 .flags = IORESOURCE_IRQ, 189 }, 190 }; 191 192 static struct platform_device i2c0_device = { 193 .name = "i2c-sh_mobile", 194 .id = 0, 195 .resource = i2c0_resources, 196 .num_resources = ARRAY_SIZE(i2c0_resources), 197 }; 198 199 static struct platform_device i2c1_device = { 200 .name = "i2c-sh_mobile", 201 .id = 1, 202 .resource = i2c1_resources, 203 .num_resources = ARRAY_SIZE(i2c1_resources), 204 }; 205 206 static struct platform_device i2c2_device = { 207 .name = "i2c-sh_mobile", 208 .id = 2, 209 .resource = i2c2_resources, 210 .num_resources = ARRAY_SIZE(i2c2_resources), 211 }; 212 213 static struct platform_device i2c3_device = { 214 .name = "i2c-sh_mobile", 215 .id = 3, 216 .resource = i2c3_resources, 217 .num_resources = ARRAY_SIZE(i2c3_resources), 218 }; 219 220 static struct platform_device i2c4_device = { 221 .name = "i2c-sh_mobile", 222 .id = 4, 223 .resource = i2c4_resources, 224 .num_resources = ARRAY_SIZE(i2c4_resources), 225 }; 226 227 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { 228 { 229 .slave_id = SHDMA_SLAVE_SCIF0_TX, 230 .addr = 0xe6c40020, 231 .chcr = CHCR_TX(XMIT_SZ_8BIT), 232 .mid_rid = 0x21, 233 }, { 234 .slave_id = SHDMA_SLAVE_SCIF0_RX, 235 .addr = 0xe6c40024, 236 .chcr = CHCR_RX(XMIT_SZ_8BIT), 237 .mid_rid = 0x22, 238 }, { 239 .slave_id = SHDMA_SLAVE_SCIF1_TX, 240 .addr = 0xe6c50020, 241 .chcr = CHCR_TX(XMIT_SZ_8BIT), 242 .mid_rid = 0x25, 243 }, { 244 .slave_id = SHDMA_SLAVE_SCIF1_RX, 245 .addr = 0xe6c50024, 246 .chcr = CHCR_RX(XMIT_SZ_8BIT), 247 .mid_rid = 0x26, 248 }, { 249 .slave_id = SHDMA_SLAVE_SCIF2_TX, 250 .addr = 0xe6c60020, 251 .chcr = CHCR_TX(XMIT_SZ_8BIT), 252 .mid_rid = 0x29, 253 }, { 254 .slave_id = SHDMA_SLAVE_SCIF2_RX, 255 .addr = 0xe6c60024, 256 .chcr = CHCR_RX(XMIT_SZ_8BIT), 257 .mid_rid = 0x2a, 258 }, { 259 .slave_id = SHDMA_SLAVE_SCIF3_TX, 260 .addr = 0xe6c70020, 261 .chcr = CHCR_TX(XMIT_SZ_8BIT), 262 .mid_rid = 0x2d, 263 }, { 264 .slave_id = SHDMA_SLAVE_SCIF3_RX, 265 .addr = 0xe6c70024, 266 .chcr = CHCR_RX(XMIT_SZ_8BIT), 267 .mid_rid = 0x2e, 268 }, { 269 .slave_id = SHDMA_SLAVE_SCIF4_TX, 270 .addr = 0xe6c80020, 271 .chcr = CHCR_TX(XMIT_SZ_8BIT), 272 .mid_rid = 0x39, 273 }, { 274 .slave_id = SHDMA_SLAVE_SCIF4_RX, 275 .addr = 0xe6c80024, 276 .chcr = CHCR_RX(XMIT_SZ_8BIT), 277 .mid_rid = 0x3a, 278 }, { 279 .slave_id = SHDMA_SLAVE_SCIF5_TX, 280 .addr = 0xe6cb0020, 281 .chcr = CHCR_TX(XMIT_SZ_8BIT), 282 .mid_rid = 0x35, 283 }, { 284 .slave_id = SHDMA_SLAVE_SCIF5_RX, 285 .addr = 0xe6cb0024, 286 .chcr = CHCR_RX(XMIT_SZ_8BIT), 287 .mid_rid = 0x36, 288 }, { 289 .slave_id = SHDMA_SLAVE_SCIF6_TX, 290 .addr = 0xe6cc0020, 291 .chcr = CHCR_TX(XMIT_SZ_8BIT), 292 .mid_rid = 0x1d, 293 }, { 294 .slave_id = SHDMA_SLAVE_SCIF6_RX, 295 .addr = 0xe6cc0024, 296 .chcr = CHCR_RX(XMIT_SZ_8BIT), 297 .mid_rid = 0x1e, 298 }, { 299 .slave_id = SHDMA_SLAVE_SCIF7_TX, 300 .addr = 0xe6cd0020, 301 .chcr = CHCR_TX(XMIT_SZ_8BIT), 302 .mid_rid = 0x19, 303 }, { 304 .slave_id = SHDMA_SLAVE_SCIF7_RX, 305 .addr = 0xe6cd0024, 306 .chcr = CHCR_RX(XMIT_SZ_8BIT), 307 .mid_rid = 0x1a, 308 }, { 309 .slave_id = SHDMA_SLAVE_SCIF8_TX, 310 .addr = 0xe6c30040, 311 .chcr = CHCR_TX(XMIT_SZ_8BIT), 312 .mid_rid = 0x3d, 313 }, { 314 .slave_id = SHDMA_SLAVE_SCIF8_RX, 315 .addr = 0xe6c30060, 316 .chcr = CHCR_RX(XMIT_SZ_8BIT), 317 .mid_rid = 0x3e, 318 }, { 319 .slave_id = SHDMA_SLAVE_SDHI0_TX, 320 .addr = 0xee100030, 321 .chcr = CHCR_TX(XMIT_SZ_16BIT), 322 .mid_rid = 0xc1, 323 }, { 324 .slave_id = SHDMA_SLAVE_SDHI0_RX, 325 .addr = 0xee100030, 326 .chcr = CHCR_RX(XMIT_SZ_16BIT), 327 .mid_rid = 0xc2, 328 }, { 329 .slave_id = SHDMA_SLAVE_SDHI1_TX, 330 .addr = 0xee120030, 331 .chcr = CHCR_TX(XMIT_SZ_16BIT), 332 .mid_rid = 0xc9, 333 }, { 334 .slave_id = SHDMA_SLAVE_SDHI1_RX, 335 .addr = 0xee120030, 336 .chcr = CHCR_RX(XMIT_SZ_16BIT), 337 .mid_rid = 0xca, 338 }, { 339 .slave_id = SHDMA_SLAVE_SDHI2_TX, 340 .addr = 0xee140030, 341 .chcr = CHCR_TX(XMIT_SZ_16BIT), 342 .mid_rid = 0xcd, 343 }, { 344 .slave_id = SHDMA_SLAVE_SDHI2_RX, 345 .addr = 0xee140030, 346 .chcr = CHCR_RX(XMIT_SZ_16BIT), 347 .mid_rid = 0xce, 348 }, { 349 .slave_id = SHDMA_SLAVE_MMCIF_TX, 350 .addr = 0xe6bd0034, 351 .chcr = CHCR_TX(XMIT_SZ_32BIT), 352 .mid_rid = 0xd1, 353 }, { 354 .slave_id = SHDMA_SLAVE_MMCIF_RX, 355 .addr = 0xe6bd0034, 356 .chcr = CHCR_RX(XMIT_SZ_32BIT), 357 .mid_rid = 0xd2, 358 }, 359 }; 360 361 #define DMAE_CHANNEL(_offset) \ 362 { \ 363 .offset = _offset - 0x20, \ 364 .dmars = _offset - 0x20 + 0x40, \ 365 } 366 367 static const struct sh_dmae_channel sh73a0_dmae_channels[] = { 368 DMAE_CHANNEL(0x8000), 369 DMAE_CHANNEL(0x8080), 370 DMAE_CHANNEL(0x8100), 371 DMAE_CHANNEL(0x8180), 372 DMAE_CHANNEL(0x8200), 373 DMAE_CHANNEL(0x8280), 374 DMAE_CHANNEL(0x8300), 375 DMAE_CHANNEL(0x8380), 376 DMAE_CHANNEL(0x8400), 377 DMAE_CHANNEL(0x8480), 378 DMAE_CHANNEL(0x8500), 379 DMAE_CHANNEL(0x8580), 380 DMAE_CHANNEL(0x8600), 381 DMAE_CHANNEL(0x8680), 382 DMAE_CHANNEL(0x8700), 383 DMAE_CHANNEL(0x8780), 384 DMAE_CHANNEL(0x8800), 385 DMAE_CHANNEL(0x8880), 386 DMAE_CHANNEL(0x8900), 387 DMAE_CHANNEL(0x8980), 388 }; 389 390 static struct sh_dmae_pdata sh73a0_dmae_platform_data = { 391 .slave = sh73a0_dmae_slaves, 392 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), 393 .channel = sh73a0_dmae_channels, 394 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), 395 .ts_low_shift = TS_LOW_SHIFT, 396 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 397 .ts_high_shift = TS_HI_SHIFT, 398 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 399 .ts_shift = dma_ts_shift, 400 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 401 .dmaor_init = DMAOR_DME, 402 }; 403 404 static struct resource sh73a0_dmae_resources[] = { 405 DEFINE_RES_MEM(0xfe000020, 0x89e0), 406 { 407 .name = "error_irq", 408 .start = gic_spi(129), 409 .end = gic_spi(129), 410 .flags = IORESOURCE_IRQ, 411 }, 412 { 413 /* IRQ for channels 0-19 */ 414 .start = gic_spi(109), 415 .end = gic_spi(128), 416 .flags = IORESOURCE_IRQ, 417 }, 418 }; 419 420 static struct platform_device dma0_device = { 421 .name = "sh-dma-engine", 422 .id = 0, 423 .resource = sh73a0_dmae_resources, 424 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), 425 .dev = { 426 .platform_data = &sh73a0_dmae_platform_data, 427 }, 428 }; 429 430 /* MPDMAC */ 431 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = { 432 { 433 .slave_id = SHDMA_SLAVE_FSI2A_RX, 434 .addr = 0xec230020, 435 .chcr = CHCR_RX(XMIT_SZ_32BIT), 436 .mid_rid = 0xd6, /* CHECK ME */ 437 }, { 438 .slave_id = SHDMA_SLAVE_FSI2A_TX, 439 .addr = 0xec230024, 440 .chcr = CHCR_TX(XMIT_SZ_32BIT), 441 .mid_rid = 0xd5, /* CHECK ME */ 442 }, { 443 .slave_id = SHDMA_SLAVE_FSI2C_RX, 444 .addr = 0xec230060, 445 .chcr = CHCR_RX(XMIT_SZ_32BIT), 446 .mid_rid = 0xda, /* CHECK ME */ 447 }, { 448 .slave_id = SHDMA_SLAVE_FSI2C_TX, 449 .addr = 0xec230064, 450 .chcr = CHCR_TX(XMIT_SZ_32BIT), 451 .mid_rid = 0xd9, /* CHECK ME */ 452 }, { 453 .slave_id = SHDMA_SLAVE_FSI2B_RX, 454 .addr = 0xec240020, 455 .chcr = CHCR_RX(XMIT_SZ_32BIT), 456 .mid_rid = 0x8e, /* CHECK ME */ 457 }, { 458 .slave_id = SHDMA_SLAVE_FSI2B_TX, 459 .addr = 0xec240024, 460 .chcr = CHCR_RX(XMIT_SZ_32BIT), 461 .mid_rid = 0x8d, /* CHECK ME */ 462 }, { 463 .slave_id = SHDMA_SLAVE_FSI2D_RX, 464 .addr = 0xec240060, 465 .chcr = CHCR_RX(XMIT_SZ_32BIT), 466 .mid_rid = 0x9a, /* CHECK ME */ 467 }, 468 }; 469 470 #define MPDMA_CHANNEL(a, b, c) \ 471 { \ 472 .offset = a, \ 473 .dmars = b, \ 474 .dmars_bit = c, \ 475 .chclr_offset = (0x220 - 0x20) + a \ 476 } 477 478 static const struct sh_dmae_channel sh73a0_mpdma_channels[] = { 479 MPDMA_CHANNEL(0x00, 0, 0), 480 MPDMA_CHANNEL(0x10, 0, 8), 481 MPDMA_CHANNEL(0x20, 4, 0), 482 MPDMA_CHANNEL(0x30, 4, 8), 483 MPDMA_CHANNEL(0x50, 8, 0), 484 MPDMA_CHANNEL(0x70, 8, 8), 485 }; 486 487 static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { 488 .slave = sh73a0_mpdma_slaves, 489 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves), 490 .channel = sh73a0_mpdma_channels, 491 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels), 492 .ts_low_shift = TS_LOW_SHIFT, 493 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 494 .ts_high_shift = TS_HI_SHIFT, 495 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 496 .ts_shift = dma_ts_shift, 497 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 498 .dmaor_init = DMAOR_DME, 499 .chclr_present = 1, 500 }; 501 502 /* Resource order important! */ 503 static struct resource sh73a0_mpdma_resources[] = { 504 /* Channel registers and DMAOR */ 505 DEFINE_RES_MEM(0xec618020, 0x270), 506 /* DMARSx */ 507 DEFINE_RES_MEM(0xec619000, 0xc), 508 { 509 .name = "error_irq", 510 .start = gic_spi(181), 511 .end = gic_spi(181), 512 .flags = IORESOURCE_IRQ, 513 }, 514 { 515 /* IRQ for channels 0-5 */ 516 .start = gic_spi(175), 517 .end = gic_spi(180), 518 .flags = IORESOURCE_IRQ, 519 }, 520 }; 521 522 static struct platform_device mpdma0_device = { 523 .name = "sh-dma-engine", 524 .id = 1, 525 .resource = sh73a0_mpdma_resources, 526 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources), 527 .dev = { 528 .platform_data = &sh73a0_mpdma_platform_data, 529 }, 530 }; 531 532 static struct resource pmu_resources[] = { 533 [0] = { 534 .start = gic_spi(55), 535 .end = gic_spi(55), 536 .flags = IORESOURCE_IRQ, 537 }, 538 [1] = { 539 .start = gic_spi(56), 540 .end = gic_spi(56), 541 .flags = IORESOURCE_IRQ, 542 }, 543 }; 544 545 static struct platform_device pmu_device = { 546 .name = "arm-pmu", 547 .id = -1, 548 .num_resources = ARRAY_SIZE(pmu_resources), 549 .resource = pmu_resources, 550 }; 551 552 /* an IPMMU module for ICB */ 553 static struct resource ipmmu_resources[] = { 554 DEFINE_RES_MEM(0xfe951000, 0x100), 555 }; 556 557 static const char * const ipmmu_dev_names[] = { 558 "sh_mobile_lcdc_fb.0", 559 }; 560 561 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { 562 .dev_names = ipmmu_dev_names, 563 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), 564 }; 565 566 static struct platform_device ipmmu_device = { 567 .name = "ipmmu", 568 .id = -1, 569 .dev = { 570 .platform_data = &ipmmu_platform_data, 571 }, 572 .resource = ipmmu_resources, 573 .num_resources = ARRAY_SIZE(ipmmu_resources), 574 }; 575 576 static struct renesas_intc_irqpin_config irqpin0_platform_data = { 577 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ 578 }; 579 580 static struct resource irqpin0_resources[] = { 581 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ 582 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ 583 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ 584 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ 585 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ 586 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ 587 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ 588 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ 589 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ 590 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ 591 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ 592 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ 593 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ 594 }; 595 596 static struct platform_device irqpin0_device = { 597 .name = "renesas_intc_irqpin", 598 .id = 0, 599 .resource = irqpin0_resources, 600 .num_resources = ARRAY_SIZE(irqpin0_resources), 601 .dev = { 602 .platform_data = &irqpin0_platform_data, 603 }, 604 }; 605 606 static struct renesas_intc_irqpin_config irqpin1_platform_data = { 607 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ 608 .control_parent = true, /* Disable spurious IRQ10 */ 609 }; 610 611 static struct resource irqpin1_resources[] = { 612 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ 613 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ 614 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ 615 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ 616 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ 617 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ 618 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ 619 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ 620 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ 621 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ 622 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ 623 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ 624 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ 625 }; 626 627 static struct platform_device irqpin1_device = { 628 .name = "renesas_intc_irqpin", 629 .id = 1, 630 .resource = irqpin1_resources, 631 .num_resources = ARRAY_SIZE(irqpin1_resources), 632 .dev = { 633 .platform_data = &irqpin1_platform_data, 634 }, 635 }; 636 637 static struct renesas_intc_irqpin_config irqpin2_platform_data = { 638 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ 639 }; 640 641 static struct resource irqpin2_resources[] = { 642 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ 643 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ 644 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ 645 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ 646 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ 647 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ 648 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ 649 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ 650 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ 651 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ 652 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ 653 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ 654 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ 655 }; 656 657 static struct platform_device irqpin2_device = { 658 .name = "renesas_intc_irqpin", 659 .id = 2, 660 .resource = irqpin2_resources, 661 .num_resources = ARRAY_SIZE(irqpin2_resources), 662 .dev = { 663 .platform_data = &irqpin2_platform_data, 664 }, 665 }; 666 667 static struct renesas_intc_irqpin_config irqpin3_platform_data = { 668 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ 669 }; 670 671 static struct resource irqpin3_resources[] = { 672 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ 673 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ 674 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ 675 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ 676 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ 677 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ 678 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ 679 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ 680 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ 681 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ 682 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ 683 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ 684 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ 685 }; 686 687 static struct platform_device irqpin3_device = { 688 .name = "renesas_intc_irqpin", 689 .id = 3, 690 .resource = irqpin3_resources, 691 .num_resources = ARRAY_SIZE(irqpin3_resources), 692 .dev = { 693 .platform_data = &irqpin3_platform_data, 694 }, 695 }; 696 697 static struct platform_device *sh73a0_devices_dt[] __initdata = { 698 &scif0_device, 699 &scif1_device, 700 &scif2_device, 701 &scif3_device, 702 &scif4_device, 703 &scif5_device, 704 &scif6_device, 705 &scif7_device, 706 &scif8_device, 707 &cmt1_device, 708 }; 709 710 static struct platform_device *sh73a0_early_devices[] __initdata = { 711 &tmu0_device, 712 &ipmmu_device, 713 }; 714 715 static struct platform_device *sh73a0_late_devices[] __initdata = { 716 &i2c0_device, 717 &i2c1_device, 718 &i2c2_device, 719 &i2c3_device, 720 &i2c4_device, 721 &dma0_device, 722 &mpdma0_device, 723 &pmu_device, 724 &irqpin0_device, 725 &irqpin1_device, 726 &irqpin2_device, 727 &irqpin3_device, 728 }; 729 730 #define SRCR2 IOMEM(0xe61580b0) 731 732 void __init sh73a0_add_standard_devices(void) 733 { 734 /* Clear software reset bit on SY-DMAC module */ 735 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); 736 737 platform_add_devices(sh73a0_devices_dt, 738 ARRAY_SIZE(sh73a0_devices_dt)); 739 platform_add_devices(sh73a0_early_devices, 740 ARRAY_SIZE(sh73a0_early_devices)); 741 platform_add_devices(sh73a0_late_devices, 742 ARRAY_SIZE(sh73a0_late_devices)); 743 } 744 745 void __init sh73a0_init_delay(void) 746 { 747 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */ 748 } 749 750 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 751 void __init __weak sh73a0_register_twd(void) { } 752 753 void __init sh73a0_earlytimer_init(void) 754 { 755 sh73a0_init_delay(); 756 sh73a0_clock_init(); 757 shmobile_earlytimer_init(); 758 sh73a0_register_twd(); 759 } 760 761 void __init sh73a0_add_early_devices(void) 762 { 763 early_platform_add_devices(sh73a0_devices_dt, 764 ARRAY_SIZE(sh73a0_devices_dt)); 765 early_platform_add_devices(sh73a0_early_devices, 766 ARRAY_SIZE(sh73a0_early_devices)); 767 768 /* setup early console here as well */ 769 shmobile_setup_console(); 770 } 771 772 #ifdef CONFIG_USE_OF 773 774 void __init sh73a0_add_standard_devices_dt(void) 775 { 776 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; 777 778 /* clocks are setup late during boot in the case of DT */ 779 sh73a0_clock_init(); 780 781 platform_add_devices(sh73a0_devices_dt, 782 ARRAY_SIZE(sh73a0_devices_dt)); 783 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 784 785 /* Instantiate cpufreq-cpu0 */ 786 platform_device_register_full(&devinfo); 787 } 788 789 static const char *sh73a0_boards_compat_dt[] __initdata = { 790 "renesas,sh73a0", 791 NULL, 792 }; 793 794 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") 795 .smp = smp_ops(sh73a0_smp_ops), 796 .map_io = sh73a0_map_io, 797 .init_early = sh73a0_init_delay, 798 .nr_irqs = NR_IRQS_LEGACY, 799 .init_machine = sh73a0_add_standard_devices_dt, 800 .dt_compat = sh73a0_boards_compat_dt, 801 MACHINE_END 802 #endif /* CONFIG_USE_OF */ 803