1 /* 2 * r8a7779 processor support 3 * 4 * Copyright (C) 2011, 2013 Renesas Solutions Corp. 5 * Copyright (C) 2011 Magnus Damm 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/irqchip.h> 26 #include <linux/irqchip/arm-gic.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_data/dma-rcar-hpbdma.h> 29 #include <linux/platform_data/gpio-rcar.h> 30 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 31 #include <linux/platform_device.h> 32 #include <linux/delay.h> 33 #include <linux/input.h> 34 #include <linux/io.h> 35 #include <linux/serial_sci.h> 36 #include <linux/sh_timer.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/usb/otg.h> 39 #include <linux/usb/hcd.h> 40 #include <linux/usb/ehci_pdriver.h> 41 #include <linux/usb/ohci_pdriver.h> 42 #include <linux/pm_runtime.h> 43 #include <mach/irqs.h> 44 #include <mach/r8a7779.h> 45 #include <mach/common.h> 46 #include <asm/mach-types.h> 47 #include <asm/mach/arch.h> 48 #include <asm/mach/time.h> 49 #include <asm/mach/map.h> 50 #include <asm/hardware/cache-l2x0.h> 51 52 static struct map_desc r8a7779_io_desc[] __initdata = { 53 /* 2M entity map for 0xf0000000 (MPCORE) */ 54 { 55 .virtual = 0xf0000000, 56 .pfn = __phys_to_pfn(0xf0000000), 57 .length = SZ_2M, 58 .type = MT_DEVICE_NONSHARED 59 }, 60 /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ 61 { 62 .virtual = 0xfe000000, 63 .pfn = __phys_to_pfn(0xfe000000), 64 .length = SZ_16M, 65 .type = MT_DEVICE_NONSHARED 66 }, 67 }; 68 69 void __init r8a7779_map_io(void) 70 { 71 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); 72 } 73 74 /* IRQ */ 75 #define INT2SMSKCR0 IOMEM(0xfe7822a0) 76 #define INT2SMSKCR1 IOMEM(0xfe7822a4) 77 #define INT2SMSKCR2 IOMEM(0xfe7822a8) 78 #define INT2SMSKCR3 IOMEM(0xfe7822ac) 79 #define INT2SMSKCR4 IOMEM(0xfe7822b0) 80 81 #define INT2NTSR0 IOMEM(0xfe700060) 82 #define INT2NTSR1 IOMEM(0xfe700064) 83 84 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = { 85 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 86 .sense_bitfield_width = 2, 87 }; 88 89 static struct resource irqpin0_resources[] __initdata = { 90 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 91 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 92 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 93 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 94 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 95 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ 96 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ 97 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ 98 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ 99 }; 100 101 void __init r8a7779_init_irq_extpin_dt(int irlm) 102 { 103 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 104 u32 tmp; 105 106 if (!icr0) { 107 pr_warn("r8a7779: unable to setup external irq pin mode\n"); 108 return; 109 } 110 111 tmp = ioread32(icr0); 112 if (irlm) 113 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 114 else 115 tmp &= ~(1 << 23); /* IRL mode - not supported */ 116 tmp |= (1 << 21); /* LVLMODE = 1 */ 117 iowrite32(tmp, icr0); 118 iounmap(icr0); 119 } 120 121 void __init r8a7779_init_irq_extpin(int irlm) 122 { 123 r8a7779_init_irq_extpin_dt(irlm); 124 if (irlm) 125 platform_device_register_resndata( 126 &platform_bus, "renesas_intc_irqpin", -1, 127 irqpin0_resources, ARRAY_SIZE(irqpin0_resources), 128 &irqpin0_platform_data, sizeof(irqpin0_platform_data)); 129 } 130 131 /* PFC/GPIO */ 132 static struct resource r8a7779_pfc_resources[] = { 133 DEFINE_RES_MEM(0xfffc0000, 0x023c), 134 }; 135 136 static struct platform_device r8a7779_pfc_device = { 137 .name = "pfc-r8a7779", 138 .id = -1, 139 .resource = r8a7779_pfc_resources, 140 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), 141 }; 142 143 #define R8A7779_GPIO(idx, npins) \ 144 static struct resource r8a7779_gpio##idx##_resources[] = { \ 145 DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \ 146 DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \ 147 }; \ 148 \ 149 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ 150 .gpio_base = 32 * (idx), \ 151 .irq_base = 0, \ 152 .number_of_pins = npins, \ 153 .pctl_name = "pfc-r8a7779", \ 154 }; \ 155 \ 156 static struct platform_device r8a7779_gpio##idx##_device = { \ 157 .name = "gpio_rcar", \ 158 .id = idx, \ 159 .resource = r8a7779_gpio##idx##_resources, \ 160 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \ 161 .dev = { \ 162 .platform_data = &r8a7779_gpio##idx##_platform_data, \ 163 }, \ 164 } 165 166 R8A7779_GPIO(0, 32); 167 R8A7779_GPIO(1, 32); 168 R8A7779_GPIO(2, 32); 169 R8A7779_GPIO(3, 32); 170 R8A7779_GPIO(4, 32); 171 R8A7779_GPIO(5, 32); 172 R8A7779_GPIO(6, 9); 173 174 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = { 175 &r8a7779_pfc_device, 176 &r8a7779_gpio0_device, 177 &r8a7779_gpio1_device, 178 &r8a7779_gpio2_device, 179 &r8a7779_gpio3_device, 180 &r8a7779_gpio4_device, 181 &r8a7779_gpio5_device, 182 &r8a7779_gpio6_device, 183 }; 184 185 void __init r8a7779_pinmux_init(void) 186 { 187 platform_add_devices(r8a7779_pinctrl_devices, 188 ARRAY_SIZE(r8a7779_pinctrl_devices)); 189 } 190 191 /* SCIF */ 192 #define R8A7779_SCIF(index, baseaddr, irq) \ 193 static struct plat_sci_port scif##index##_platform_data = { \ 194 .type = PORT_SCIF, \ 195 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 197 }; \ 198 \ 199 static struct resource scif##index##_resources[] = { \ 200 DEFINE_RES_MEM(baseaddr, 0x100), \ 201 DEFINE_RES_IRQ(irq), \ 202 }; \ 203 \ 204 static struct platform_device scif##index##_device = { \ 205 .name = "sh-sci", \ 206 .id = index, \ 207 .resource = scif##index##_resources, \ 208 .num_resources = ARRAY_SIZE(scif##index##_resources), \ 209 .dev = { \ 210 .platform_data = &scif##index##_platform_data, \ 211 }, \ 212 } 213 214 R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78)); 215 R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79)); 216 R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a)); 217 R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b)); 218 R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c)); 219 R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d)); 220 221 /* TMU */ 222 static struct sh_timer_config tmu00_platform_data = { 223 .name = "TMU00", 224 .channel_offset = 0x4, 225 .timer_bit = 0, 226 .clockevent_rating = 200, 227 }; 228 229 static struct resource tmu00_resources[] = { 230 [0] = { 231 .name = "TMU00", 232 .start = 0xffd80008, 233 .end = 0xffd80013, 234 .flags = IORESOURCE_MEM, 235 }, 236 [1] = { 237 .start = gic_iid(0x40), 238 .flags = IORESOURCE_IRQ, 239 }, 240 }; 241 242 static struct platform_device tmu00_device = { 243 .name = "sh_tmu", 244 .id = 0, 245 .dev = { 246 .platform_data = &tmu00_platform_data, 247 }, 248 .resource = tmu00_resources, 249 .num_resources = ARRAY_SIZE(tmu00_resources), 250 }; 251 252 static struct sh_timer_config tmu01_platform_data = { 253 .name = "TMU01", 254 .channel_offset = 0x10, 255 .timer_bit = 1, 256 .clocksource_rating = 200, 257 }; 258 259 static struct resource tmu01_resources[] = { 260 [0] = { 261 .name = "TMU01", 262 .start = 0xffd80014, 263 .end = 0xffd8001f, 264 .flags = IORESOURCE_MEM, 265 }, 266 [1] = { 267 .start = gic_iid(0x41), 268 .flags = IORESOURCE_IRQ, 269 }, 270 }; 271 272 static struct platform_device tmu01_device = { 273 .name = "sh_tmu", 274 .id = 1, 275 .dev = { 276 .platform_data = &tmu01_platform_data, 277 }, 278 .resource = tmu01_resources, 279 .num_resources = ARRAY_SIZE(tmu01_resources), 280 }; 281 282 /* I2C */ 283 static struct resource rcar_i2c0_res[] = { 284 { 285 .start = 0xffc70000, 286 .end = 0xffc70fff, 287 .flags = IORESOURCE_MEM, 288 }, { 289 .start = gic_iid(0x6f), 290 .flags = IORESOURCE_IRQ, 291 }, 292 }; 293 294 static struct platform_device i2c0_device = { 295 .name = "i2c-rcar", 296 .id = 0, 297 .resource = rcar_i2c0_res, 298 .num_resources = ARRAY_SIZE(rcar_i2c0_res), 299 }; 300 301 static struct resource rcar_i2c1_res[] = { 302 { 303 .start = 0xffc71000, 304 .end = 0xffc71fff, 305 .flags = IORESOURCE_MEM, 306 }, { 307 .start = gic_iid(0x72), 308 .flags = IORESOURCE_IRQ, 309 }, 310 }; 311 312 static struct platform_device i2c1_device = { 313 .name = "i2c-rcar", 314 .id = 1, 315 .resource = rcar_i2c1_res, 316 .num_resources = ARRAY_SIZE(rcar_i2c1_res), 317 }; 318 319 static struct resource rcar_i2c2_res[] = { 320 { 321 .start = 0xffc72000, 322 .end = 0xffc72fff, 323 .flags = IORESOURCE_MEM, 324 }, { 325 .start = gic_iid(0x70), 326 .flags = IORESOURCE_IRQ, 327 }, 328 }; 329 330 static struct platform_device i2c2_device = { 331 .name = "i2c-rcar", 332 .id = 2, 333 .resource = rcar_i2c2_res, 334 .num_resources = ARRAY_SIZE(rcar_i2c2_res), 335 }; 336 337 static struct resource rcar_i2c3_res[] = { 338 { 339 .start = 0xffc73000, 340 .end = 0xffc73fff, 341 .flags = IORESOURCE_MEM, 342 }, { 343 .start = gic_iid(0x71), 344 .flags = IORESOURCE_IRQ, 345 }, 346 }; 347 348 static struct platform_device i2c3_device = { 349 .name = "i2c-rcar", 350 .id = 3, 351 .resource = rcar_i2c3_res, 352 .num_resources = ARRAY_SIZE(rcar_i2c3_res), 353 }; 354 355 static struct resource sata_resources[] = { 356 [0] = { 357 .name = "rcar-sata", 358 .start = 0xfc600000, 359 .end = 0xfc601fff, 360 .flags = IORESOURCE_MEM, 361 }, 362 [1] = { 363 .start = gic_iid(0x84), 364 .flags = IORESOURCE_IRQ, 365 }, 366 }; 367 368 static struct platform_device sata_device = { 369 .name = "sata_rcar", 370 .id = -1, 371 .resource = sata_resources, 372 .num_resources = ARRAY_SIZE(sata_resources), 373 .dev = { 374 .dma_mask = &sata_device.dev.coherent_dma_mask, 375 .coherent_dma_mask = DMA_BIT_MASK(32), 376 }, 377 }; 378 379 /* USB */ 380 static struct usb_phy *phy; 381 382 static int usb_power_on(struct platform_device *pdev) 383 { 384 if (IS_ERR(phy)) 385 return PTR_ERR(phy); 386 387 pm_runtime_enable(&pdev->dev); 388 pm_runtime_get_sync(&pdev->dev); 389 390 usb_phy_init(phy); 391 392 return 0; 393 } 394 395 static void usb_power_off(struct platform_device *pdev) 396 { 397 if (IS_ERR(phy)) 398 return; 399 400 usb_phy_shutdown(phy); 401 402 pm_runtime_put_sync(&pdev->dev); 403 pm_runtime_disable(&pdev->dev); 404 } 405 406 static int ehci_init_internal_buffer(struct usb_hcd *hcd) 407 { 408 /* 409 * Below are recommended values from the datasheet; 410 * see [USB :: Setting of EHCI Internal Buffer]. 411 */ 412 /* EHCI IP internal buffer setting */ 413 iowrite32(0x00ff0040, hcd->regs + 0x0094); 414 /* EHCI IP internal buffer enable */ 415 iowrite32(0x00000001, hcd->regs + 0x009C); 416 417 return 0; 418 } 419 420 static struct usb_ehci_pdata ehcix_pdata = { 421 .power_on = usb_power_on, 422 .power_off = usb_power_off, 423 .power_suspend = usb_power_off, 424 .pre_setup = ehci_init_internal_buffer, 425 }; 426 427 static struct resource ehci0_resources[] = { 428 [0] = { 429 .start = 0xffe70000, 430 .end = 0xffe70400 - 1, 431 .flags = IORESOURCE_MEM, 432 }, 433 [1] = { 434 .start = gic_iid(0x4c), 435 .flags = IORESOURCE_IRQ, 436 }, 437 }; 438 439 static struct platform_device ehci0_device = { 440 .name = "ehci-platform", 441 .id = 0, 442 .dev = { 443 .dma_mask = &ehci0_device.dev.coherent_dma_mask, 444 .coherent_dma_mask = 0xffffffff, 445 .platform_data = &ehcix_pdata, 446 }, 447 .num_resources = ARRAY_SIZE(ehci0_resources), 448 .resource = ehci0_resources, 449 }; 450 451 static struct resource ehci1_resources[] = { 452 [0] = { 453 .start = 0xfff70000, 454 .end = 0xfff70400 - 1, 455 .flags = IORESOURCE_MEM, 456 }, 457 [1] = { 458 .start = gic_iid(0x4d), 459 .flags = IORESOURCE_IRQ, 460 }, 461 }; 462 463 static struct platform_device ehci1_device = { 464 .name = "ehci-platform", 465 .id = 1, 466 .dev = { 467 .dma_mask = &ehci1_device.dev.coherent_dma_mask, 468 .coherent_dma_mask = 0xffffffff, 469 .platform_data = &ehcix_pdata, 470 }, 471 .num_resources = ARRAY_SIZE(ehci1_resources), 472 .resource = ehci1_resources, 473 }; 474 475 static struct usb_ohci_pdata ohcix_pdata = { 476 .power_on = usb_power_on, 477 .power_off = usb_power_off, 478 .power_suspend = usb_power_off, 479 }; 480 481 static struct resource ohci0_resources[] = { 482 [0] = { 483 .start = 0xffe70400, 484 .end = 0xffe70800 - 1, 485 .flags = IORESOURCE_MEM, 486 }, 487 [1] = { 488 .start = gic_iid(0x4c), 489 .flags = IORESOURCE_IRQ, 490 }, 491 }; 492 493 static struct platform_device ohci0_device = { 494 .name = "ohci-platform", 495 .id = 0, 496 .dev = { 497 .dma_mask = &ohci0_device.dev.coherent_dma_mask, 498 .coherent_dma_mask = 0xffffffff, 499 .platform_data = &ohcix_pdata, 500 }, 501 .num_resources = ARRAY_SIZE(ohci0_resources), 502 .resource = ohci0_resources, 503 }; 504 505 static struct resource ohci1_resources[] = { 506 [0] = { 507 .start = 0xfff70400, 508 .end = 0xfff70800 - 1, 509 .flags = IORESOURCE_MEM, 510 }, 511 [1] = { 512 .start = gic_iid(0x4d), 513 .flags = IORESOURCE_IRQ, 514 }, 515 }; 516 517 static struct platform_device ohci1_device = { 518 .name = "ohci-platform", 519 .id = 1, 520 .dev = { 521 .dma_mask = &ohci1_device.dev.coherent_dma_mask, 522 .coherent_dma_mask = 0xffffffff, 523 .platform_data = &ohcix_pdata, 524 }, 525 .num_resources = ARRAY_SIZE(ohci1_resources), 526 .resource = ohci1_resources, 527 }; 528 529 /* HPB-DMA */ 530 531 /* Asynchronous mode register bits */ 532 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */ 533 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */ 534 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */ 535 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */ 536 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */ 537 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */ 538 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */ 539 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */ 540 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */ 541 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */ 542 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */ 543 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */ 544 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */ 545 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */ 546 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */ 547 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */ 548 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */ 549 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */ 550 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */ 551 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */ 552 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */ 553 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */ 554 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */ 555 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */ 556 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */ 557 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */ 558 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */ 559 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */ 560 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */ 561 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */ 562 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */ 563 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */ 564 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */ 565 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */ 566 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */ 567 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */ 568 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */ 569 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */ 570 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */ 571 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */ 572 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */ 573 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */ 574 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */ 575 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */ 576 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */ 577 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */ 578 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */ 579 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */ 580 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */ 581 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */ 582 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */ 583 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */ 584 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */ 585 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */ 586 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */ 587 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */ 588 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ 589 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */ 590 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */ 591 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */ 592 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */ 593 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */ 594 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 595 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */ 596 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */ 597 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */ 598 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */ 599 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */ 600 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */ 601 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */ 602 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */ 603 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */ 604 605 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 606 { 607 .id = HPBDMA_SLAVE_SDHI0_TX, 608 .addr = 0xffe4c000 + 0x30, 609 .dcr = HPB_DMAE_DCR_SPDS_16BIT | 610 HPB_DMAE_DCR_DMDL | 611 HPB_DMAE_DCR_DPDS_16BIT, 612 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 613 HPB_DMAE_ASYNCRSTR_ASRST22 | 614 HPB_DMAE_ASYNCRSTR_ASRST23, 615 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE | 616 HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST, 617 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK | 618 HPB_DMAE_ASYNCMDR_ASBTMD21_MASK, 619 .port = 0x0D0C, 620 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 621 .dma_ch = 21, 622 }, { 623 .id = HPBDMA_SLAVE_SDHI0_RX, 624 .addr = 0xffe4c000 + 0x30, 625 .dcr = HPB_DMAE_DCR_SMDL | 626 HPB_DMAE_DCR_SPDS_16BIT | 627 HPB_DMAE_DCR_DPDS_16BIT, 628 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 629 HPB_DMAE_ASYNCRSTR_ASRST22 | 630 HPB_DMAE_ASYNCRSTR_ASRST23, 631 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE | 632 HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST, 633 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK | 634 HPB_DMAE_ASYNCMDR_ASBTMD22_MASK, 635 .port = 0x0D0C, 636 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 637 .dma_ch = 22, 638 }, 639 }; 640 641 static const struct hpb_dmae_channel hpb_dmae_channels[] = { 642 HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 643 HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 644 }; 645 646 static struct hpb_dmae_pdata dma_platform_data __initdata = { 647 .slaves = hpb_dmae_slaves, 648 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), 649 .channels = hpb_dmae_channels, 650 .num_channels = ARRAY_SIZE(hpb_dmae_channels), 651 .ts_shift = { 652 [XMIT_SZ_8BIT] = 0, 653 [XMIT_SZ_16BIT] = 1, 654 [XMIT_SZ_32BIT] = 2, 655 }, 656 .num_hw_channels = 44, 657 }; 658 659 static struct resource hpb_dmae_resources[] __initdata = { 660 /* Channel registers */ 661 DEFINE_RES_MEM(0xffc08000, 0x1000), 662 /* Common registers */ 663 DEFINE_RES_MEM(0xffc09000, 0x170), 664 /* Asynchronous reset registers */ 665 DEFINE_RES_MEM(0xffc00300, 4), 666 /* Asynchronous mode registers */ 667 DEFINE_RES_MEM(0xffc00400, 4), 668 /* IRQ for DMA channels */ 669 DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ), 670 }; 671 672 static void __init r8a7779_register_hpb_dmae(void) 673 { 674 platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, 675 hpb_dmae_resources, 676 ARRAY_SIZE(hpb_dmae_resources), 677 &dma_platform_data, 678 sizeof(dma_platform_data)); 679 } 680 681 static struct platform_device *r8a7779_devices_dt[] __initdata = { 682 &scif0_device, 683 &scif1_device, 684 &scif2_device, 685 &scif3_device, 686 &scif4_device, 687 &scif5_device, 688 &tmu00_device, 689 &tmu01_device, 690 }; 691 692 static struct platform_device *r8a7779_standard_devices[] __initdata = { 693 &i2c0_device, 694 &i2c1_device, 695 &i2c2_device, 696 &i2c3_device, 697 &sata_device, 698 }; 699 700 void __init r8a7779_add_standard_devices(void) 701 { 702 #ifdef CONFIG_CACHE_L2X0 703 /* Early BRESP enable, Shared attribute override enable, 64K*16way */ 704 l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff); 705 #endif 706 r8a7779_pm_init(); 707 708 r8a7779_init_pm_domains(); 709 710 platform_add_devices(r8a7779_devices_dt, 711 ARRAY_SIZE(r8a7779_devices_dt)); 712 platform_add_devices(r8a7779_standard_devices, 713 ARRAY_SIZE(r8a7779_standard_devices)); 714 r8a7779_register_hpb_dmae(); 715 } 716 717 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 718 void __init __weak r8a7779_register_twd(void) { } 719 720 void __init r8a7779_earlytimer_init(void) 721 { 722 r8a7779_clock_init(); 723 r8a7779_register_twd(); 724 shmobile_earlytimer_init(); 725 } 726 727 void __init r8a7779_add_early_devices(void) 728 { 729 early_platform_add_devices(r8a7779_devices_dt, 730 ARRAY_SIZE(r8a7779_devices_dt)); 731 732 /* Early serial console setup is not included here due to 733 * memory map collisions. The SCIF serial ports in r8a7779 734 * are difficult to entity map 1:1 due to collision with the 735 * virtual memory range used by the coherent DMA code on ARM. 736 * 737 * Anyone wanting to debug early can remove UPF_IOREMAP from 738 * the sh-sci serial console platform data, adjust mapbase 739 * to a static M:N virt:phys mapping that needs to be added to 740 * the mappings passed with iotable_init() above. 741 * 742 * Then add a call to shmobile_setup_console() from this function. 743 * 744 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel 745 * command line in case of the marzen board. 746 */ 747 } 748 749 static struct platform_device *r8a7779_late_devices[] __initdata = { 750 &ehci0_device, 751 &ehci1_device, 752 &ohci0_device, 753 &ohci1_device, 754 }; 755 756 void __init r8a7779_init_late(void) 757 { 758 /* get USB PHY */ 759 phy = usb_get_phy(USB_PHY_TYPE_USB2); 760 761 shmobile_init_late(); 762 platform_add_devices(r8a7779_late_devices, 763 ARRAY_SIZE(r8a7779_late_devices)); 764 } 765 766 #ifdef CONFIG_USE_OF 767 static int r8a7779_set_wake(struct irq_data *data, unsigned int on) 768 { 769 return 0; /* always allow wakeup */ 770 } 771 772 void __init r8a7779_init_irq_dt(void) 773 { 774 gic_arch_extn.irq_set_wake = r8a7779_set_wake; 775 776 irqchip_init(); 777 778 /* route all interrupts to ARM */ 779 __raw_writel(0xffffffff, INT2NTSR0); 780 __raw_writel(0x3fffffff, INT2NTSR1); 781 782 /* unmask all known interrupts in INTCS2 */ 783 __raw_writel(0xfffffff0, INT2SMSKCR0); 784 __raw_writel(0xfff7ffff, INT2SMSKCR1); 785 __raw_writel(0xfffbffdf, INT2SMSKCR2); 786 __raw_writel(0xbffffffc, INT2SMSKCR3); 787 __raw_writel(0x003fee3f, INT2SMSKCR4); 788 } 789 790 void __init r8a7779_init_delay(void) 791 { 792 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ 793 } 794 795 void __init r8a7779_add_standard_devices_dt(void) 796 { 797 /* clocks are setup late during boot in the case of DT */ 798 r8a7779_clock_init(); 799 800 platform_add_devices(r8a7779_devices_dt, 801 ARRAY_SIZE(r8a7779_devices_dt)); 802 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 803 } 804 805 static const char *r8a7779_compat_dt[] __initdata = { 806 "renesas,r8a7779", 807 NULL, 808 }; 809 810 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") 811 .map_io = r8a7779_map_io, 812 .init_early = r8a7779_init_delay, 813 .nr_irqs = NR_IRQS_LEGACY, 814 .init_irq = r8a7779_init_irq_dt, 815 .init_machine = r8a7779_add_standard_devices_dt, 816 .init_late = r8a7779_init_late, 817 .dt_compat = r8a7779_compat_dt, 818 MACHINE_END 819 #endif /* CONFIG_USE_OF */ 820