1 /* 2 * r8a7779 processor support 3 * 4 * Copyright (C) 2011, 2013 Renesas Solutions Corp. 5 * Copyright (C) 2011 Magnus Damm 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/irqchip.h> 26 #include <linux/irqchip/arm-gic.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_data/gpio-rcar.h> 29 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 30 #include <linux/platform_device.h> 31 #include <linux/delay.h> 32 #include <linux/input.h> 33 #include <linux/io.h> 34 #include <linux/serial_sci.h> 35 #include <linux/sh_timer.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/usb/otg.h> 38 #include <linux/usb/hcd.h> 39 #include <linux/usb/ehci_pdriver.h> 40 #include <linux/usb/ohci_pdriver.h> 41 #include <linux/pm_runtime.h> 42 #include <mach/irqs.h> 43 #include <mach/r8a7779.h> 44 #include <mach/common.h> 45 #include <asm/mach-types.h> 46 #include <asm/mach/arch.h> 47 #include <asm/mach/time.h> 48 #include <asm/mach/map.h> 49 #include <asm/hardware/cache-l2x0.h> 50 51 static struct map_desc r8a7779_io_desc[] __initdata = { 52 /* 2M entity map for 0xf0000000 (MPCORE) */ 53 { 54 .virtual = 0xf0000000, 55 .pfn = __phys_to_pfn(0xf0000000), 56 .length = SZ_2M, 57 .type = MT_DEVICE_NONSHARED 58 }, 59 /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ 60 { 61 .virtual = 0xfe000000, 62 .pfn = __phys_to_pfn(0xfe000000), 63 .length = SZ_16M, 64 .type = MT_DEVICE_NONSHARED 65 }, 66 }; 67 68 void __init r8a7779_map_io(void) 69 { 70 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); 71 } 72 73 /* IRQ */ 74 #define INT2SMSKCR0 IOMEM(0xfe7822a0) 75 #define INT2SMSKCR1 IOMEM(0xfe7822a4) 76 #define INT2SMSKCR2 IOMEM(0xfe7822a8) 77 #define INT2SMSKCR3 IOMEM(0xfe7822ac) 78 #define INT2SMSKCR4 IOMEM(0xfe7822b0) 79 80 #define INT2NTSR0 IOMEM(0xfe700060) 81 #define INT2NTSR1 IOMEM(0xfe700064) 82 83 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = { 84 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 85 .sense_bitfield_width = 2, 86 }; 87 88 static struct resource irqpin0_resources[] __initdata = { 89 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 90 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 91 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 92 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 93 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 94 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ 95 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ 96 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ 97 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ 98 }; 99 100 void __init r8a7779_init_irq_extpin(int irlm) 101 { 102 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 103 u32 tmp; 104 105 if (!icr0) { 106 pr_warn("r8a7779: unable to setup external irq pin mode\n"); 107 return; 108 } 109 110 tmp = ioread32(icr0); 111 if (irlm) 112 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 113 else 114 tmp &= ~(1 << 23); /* IRL mode - not supported */ 115 tmp |= (1 << 21); /* LVLMODE = 1 */ 116 iowrite32(tmp, icr0); 117 iounmap(icr0); 118 119 if (irlm) 120 platform_device_register_resndata( 121 &platform_bus, "renesas_intc_irqpin", -1, 122 irqpin0_resources, ARRAY_SIZE(irqpin0_resources), 123 &irqpin0_platform_data, sizeof(irqpin0_platform_data)); 124 } 125 126 /* PFC/GPIO */ 127 static struct resource r8a7779_pfc_resources[] = { 128 DEFINE_RES_MEM(0xfffc0000, 0x023c), 129 }; 130 131 static struct platform_device r8a7779_pfc_device = { 132 .name = "pfc-r8a7779", 133 .id = -1, 134 .resource = r8a7779_pfc_resources, 135 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), 136 }; 137 138 #define R8A7779_GPIO(idx, npins) \ 139 static struct resource r8a7779_gpio##idx##_resources[] = { \ 140 DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \ 141 DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \ 142 }; \ 143 \ 144 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ 145 .gpio_base = 32 * (idx), \ 146 .irq_base = 0, \ 147 .number_of_pins = npins, \ 148 .pctl_name = "pfc-r8a7779", \ 149 }; \ 150 \ 151 static struct platform_device r8a7779_gpio##idx##_device = { \ 152 .name = "gpio_rcar", \ 153 .id = idx, \ 154 .resource = r8a7779_gpio##idx##_resources, \ 155 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \ 156 .dev = { \ 157 .platform_data = &r8a7779_gpio##idx##_platform_data, \ 158 }, \ 159 } 160 161 R8A7779_GPIO(0, 32); 162 R8A7779_GPIO(1, 32); 163 R8A7779_GPIO(2, 32); 164 R8A7779_GPIO(3, 32); 165 R8A7779_GPIO(4, 32); 166 R8A7779_GPIO(5, 32); 167 R8A7779_GPIO(6, 9); 168 169 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = { 170 &r8a7779_pfc_device, 171 &r8a7779_gpio0_device, 172 &r8a7779_gpio1_device, 173 &r8a7779_gpio2_device, 174 &r8a7779_gpio3_device, 175 &r8a7779_gpio4_device, 176 &r8a7779_gpio5_device, 177 &r8a7779_gpio6_device, 178 }; 179 180 void __init r8a7779_pinmux_init(void) 181 { 182 platform_add_devices(r8a7779_pinctrl_devices, 183 ARRAY_SIZE(r8a7779_pinctrl_devices)); 184 } 185 186 static struct plat_sci_port scif0_platform_data = { 187 .mapbase = 0xffe40000, 188 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 189 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 190 .scbrr_algo_id = SCBRR_ALGO_2, 191 .type = PORT_SCIF, 192 .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), 193 }; 194 195 static struct platform_device scif0_device = { 196 .name = "sh-sci", 197 .id = 0, 198 .dev = { 199 .platform_data = &scif0_platform_data, 200 }, 201 }; 202 203 static struct plat_sci_port scif1_platform_data = { 204 .mapbase = 0xffe41000, 205 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 206 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 207 .scbrr_algo_id = SCBRR_ALGO_2, 208 .type = PORT_SCIF, 209 .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)), 210 }; 211 212 static struct platform_device scif1_device = { 213 .name = "sh-sci", 214 .id = 1, 215 .dev = { 216 .platform_data = &scif1_platform_data, 217 }, 218 }; 219 220 static struct plat_sci_port scif2_platform_data = { 221 .mapbase = 0xffe42000, 222 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 223 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 224 .scbrr_algo_id = SCBRR_ALGO_2, 225 .type = PORT_SCIF, 226 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)), 227 }; 228 229 static struct platform_device scif2_device = { 230 .name = "sh-sci", 231 .id = 2, 232 .dev = { 233 .platform_data = &scif2_platform_data, 234 }, 235 }; 236 237 static struct plat_sci_port scif3_platform_data = { 238 .mapbase = 0xffe43000, 239 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 240 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 241 .scbrr_algo_id = SCBRR_ALGO_2, 242 .type = PORT_SCIF, 243 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)), 244 }; 245 246 static struct platform_device scif3_device = { 247 .name = "sh-sci", 248 .id = 3, 249 .dev = { 250 .platform_data = &scif3_platform_data, 251 }, 252 }; 253 254 static struct plat_sci_port scif4_platform_data = { 255 .mapbase = 0xffe44000, 256 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 257 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 258 .scbrr_algo_id = SCBRR_ALGO_2, 259 .type = PORT_SCIF, 260 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)), 261 }; 262 263 static struct platform_device scif4_device = { 264 .name = "sh-sci", 265 .id = 4, 266 .dev = { 267 .platform_data = &scif4_platform_data, 268 }, 269 }; 270 271 static struct plat_sci_port scif5_platform_data = { 272 .mapbase = 0xffe45000, 273 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 274 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 275 .scbrr_algo_id = SCBRR_ALGO_2, 276 .type = PORT_SCIF, 277 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)), 278 }; 279 280 static struct platform_device scif5_device = { 281 .name = "sh-sci", 282 .id = 5, 283 .dev = { 284 .platform_data = &scif5_platform_data, 285 }, 286 }; 287 288 /* TMU */ 289 static struct sh_timer_config tmu00_platform_data = { 290 .name = "TMU00", 291 .channel_offset = 0x4, 292 .timer_bit = 0, 293 .clockevent_rating = 200, 294 }; 295 296 static struct resource tmu00_resources[] = { 297 [0] = { 298 .name = "TMU00", 299 .start = 0xffd80008, 300 .end = 0xffd80013, 301 .flags = IORESOURCE_MEM, 302 }, 303 [1] = { 304 .start = gic_iid(0x40), 305 .flags = IORESOURCE_IRQ, 306 }, 307 }; 308 309 static struct platform_device tmu00_device = { 310 .name = "sh_tmu", 311 .id = 0, 312 .dev = { 313 .platform_data = &tmu00_platform_data, 314 }, 315 .resource = tmu00_resources, 316 .num_resources = ARRAY_SIZE(tmu00_resources), 317 }; 318 319 static struct sh_timer_config tmu01_platform_data = { 320 .name = "TMU01", 321 .channel_offset = 0x10, 322 .timer_bit = 1, 323 .clocksource_rating = 200, 324 }; 325 326 static struct resource tmu01_resources[] = { 327 [0] = { 328 .name = "TMU01", 329 .start = 0xffd80014, 330 .end = 0xffd8001f, 331 .flags = IORESOURCE_MEM, 332 }, 333 [1] = { 334 .start = gic_iid(0x41), 335 .flags = IORESOURCE_IRQ, 336 }, 337 }; 338 339 static struct platform_device tmu01_device = { 340 .name = "sh_tmu", 341 .id = 1, 342 .dev = { 343 .platform_data = &tmu01_platform_data, 344 }, 345 .resource = tmu01_resources, 346 .num_resources = ARRAY_SIZE(tmu01_resources), 347 }; 348 349 /* I2C */ 350 static struct resource rcar_i2c0_res[] = { 351 { 352 .start = 0xffc70000, 353 .end = 0xffc70fff, 354 .flags = IORESOURCE_MEM, 355 }, { 356 .start = gic_iid(0x6f), 357 .flags = IORESOURCE_IRQ, 358 }, 359 }; 360 361 static struct platform_device i2c0_device = { 362 .name = "i2c-rcar", 363 .id = 0, 364 .resource = rcar_i2c0_res, 365 .num_resources = ARRAY_SIZE(rcar_i2c0_res), 366 }; 367 368 static struct resource rcar_i2c1_res[] = { 369 { 370 .start = 0xffc71000, 371 .end = 0xffc71fff, 372 .flags = IORESOURCE_MEM, 373 }, { 374 .start = gic_iid(0x72), 375 .flags = IORESOURCE_IRQ, 376 }, 377 }; 378 379 static struct platform_device i2c1_device = { 380 .name = "i2c-rcar", 381 .id = 1, 382 .resource = rcar_i2c1_res, 383 .num_resources = ARRAY_SIZE(rcar_i2c1_res), 384 }; 385 386 static struct resource rcar_i2c2_res[] = { 387 { 388 .start = 0xffc72000, 389 .end = 0xffc72fff, 390 .flags = IORESOURCE_MEM, 391 }, { 392 .start = gic_iid(0x70), 393 .flags = IORESOURCE_IRQ, 394 }, 395 }; 396 397 static struct platform_device i2c2_device = { 398 .name = "i2c-rcar", 399 .id = 2, 400 .resource = rcar_i2c2_res, 401 .num_resources = ARRAY_SIZE(rcar_i2c2_res), 402 }; 403 404 static struct resource rcar_i2c3_res[] = { 405 { 406 .start = 0xffc73000, 407 .end = 0xffc73fff, 408 .flags = IORESOURCE_MEM, 409 }, { 410 .start = gic_iid(0x71), 411 .flags = IORESOURCE_IRQ, 412 }, 413 }; 414 415 static struct platform_device i2c3_device = { 416 .name = "i2c-rcar", 417 .id = 3, 418 .resource = rcar_i2c3_res, 419 .num_resources = ARRAY_SIZE(rcar_i2c3_res), 420 }; 421 422 static struct resource sata_resources[] = { 423 [0] = { 424 .name = "rcar-sata", 425 .start = 0xfc600000, 426 .end = 0xfc601fff, 427 .flags = IORESOURCE_MEM, 428 }, 429 [1] = { 430 .start = gic_iid(0x84), 431 .flags = IORESOURCE_IRQ, 432 }, 433 }; 434 435 static struct platform_device sata_device = { 436 .name = "sata_rcar", 437 .id = -1, 438 .resource = sata_resources, 439 .num_resources = ARRAY_SIZE(sata_resources), 440 .dev = { 441 .dma_mask = &sata_device.dev.coherent_dma_mask, 442 .coherent_dma_mask = DMA_BIT_MASK(32), 443 }, 444 }; 445 446 /* USB */ 447 static struct usb_phy *phy; 448 449 static int usb_power_on(struct platform_device *pdev) 450 { 451 if (IS_ERR(phy)) 452 return PTR_ERR(phy); 453 454 pm_runtime_enable(&pdev->dev); 455 pm_runtime_get_sync(&pdev->dev); 456 457 usb_phy_init(phy); 458 459 return 0; 460 } 461 462 static void usb_power_off(struct platform_device *pdev) 463 { 464 if (IS_ERR(phy)) 465 return; 466 467 usb_phy_shutdown(phy); 468 469 pm_runtime_put_sync(&pdev->dev); 470 pm_runtime_disable(&pdev->dev); 471 } 472 473 static int ehci_init_internal_buffer(struct usb_hcd *hcd) 474 { 475 /* 476 * Below are recommended values from the datasheet; 477 * see [USB :: Setting of EHCI Internal Buffer]. 478 */ 479 /* EHCI IP internal buffer setting */ 480 iowrite32(0x00ff0040, hcd->regs + 0x0094); 481 /* EHCI IP internal buffer enable */ 482 iowrite32(0x00000001, hcd->regs + 0x009C); 483 484 return 0; 485 } 486 487 static struct usb_ehci_pdata ehcix_pdata = { 488 .power_on = usb_power_on, 489 .power_off = usb_power_off, 490 .power_suspend = usb_power_off, 491 .pre_setup = ehci_init_internal_buffer, 492 }; 493 494 static struct resource ehci0_resources[] = { 495 [0] = { 496 .start = 0xffe70000, 497 .end = 0xffe70400 - 1, 498 .flags = IORESOURCE_MEM, 499 }, 500 [1] = { 501 .start = gic_iid(0x4c), 502 .flags = IORESOURCE_IRQ, 503 }, 504 }; 505 506 static struct platform_device ehci0_device = { 507 .name = "ehci-platform", 508 .id = 0, 509 .dev = { 510 .dma_mask = &ehci0_device.dev.coherent_dma_mask, 511 .coherent_dma_mask = 0xffffffff, 512 .platform_data = &ehcix_pdata, 513 }, 514 .num_resources = ARRAY_SIZE(ehci0_resources), 515 .resource = ehci0_resources, 516 }; 517 518 static struct resource ehci1_resources[] = { 519 [0] = { 520 .start = 0xfff70000, 521 .end = 0xfff70400 - 1, 522 .flags = IORESOURCE_MEM, 523 }, 524 [1] = { 525 .start = gic_iid(0x4d), 526 .flags = IORESOURCE_IRQ, 527 }, 528 }; 529 530 static struct platform_device ehci1_device = { 531 .name = "ehci-platform", 532 .id = 1, 533 .dev = { 534 .dma_mask = &ehci1_device.dev.coherent_dma_mask, 535 .coherent_dma_mask = 0xffffffff, 536 .platform_data = &ehcix_pdata, 537 }, 538 .num_resources = ARRAY_SIZE(ehci1_resources), 539 .resource = ehci1_resources, 540 }; 541 542 static struct usb_ohci_pdata ohcix_pdata = { 543 .power_on = usb_power_on, 544 .power_off = usb_power_off, 545 .power_suspend = usb_power_off, 546 }; 547 548 static struct resource ohci0_resources[] = { 549 [0] = { 550 .start = 0xffe70400, 551 .end = 0xffe70800 - 1, 552 .flags = IORESOURCE_MEM, 553 }, 554 [1] = { 555 .start = gic_iid(0x4c), 556 .flags = IORESOURCE_IRQ, 557 }, 558 }; 559 560 static struct platform_device ohci0_device = { 561 .name = "ohci-platform", 562 .id = 0, 563 .dev = { 564 .dma_mask = &ohci0_device.dev.coherent_dma_mask, 565 .coherent_dma_mask = 0xffffffff, 566 .platform_data = &ohcix_pdata, 567 }, 568 .num_resources = ARRAY_SIZE(ohci0_resources), 569 .resource = ohci0_resources, 570 }; 571 572 static struct resource ohci1_resources[] = { 573 [0] = { 574 .start = 0xfff70400, 575 .end = 0xfff70800 - 1, 576 .flags = IORESOURCE_MEM, 577 }, 578 [1] = { 579 .start = gic_iid(0x4d), 580 .flags = IORESOURCE_IRQ, 581 }, 582 }; 583 584 static struct platform_device ohci1_device = { 585 .name = "ohci-platform", 586 .id = 1, 587 .dev = { 588 .dma_mask = &ohci1_device.dev.coherent_dma_mask, 589 .coherent_dma_mask = 0xffffffff, 590 .platform_data = &ohcix_pdata, 591 }, 592 .num_resources = ARRAY_SIZE(ohci1_resources), 593 .resource = ohci1_resources, 594 }; 595 596 /* Ether */ 597 static struct resource ether_resources[] __initdata = { 598 { 599 .start = 0xfde00000, 600 .end = 0xfde003ff, 601 .flags = IORESOURCE_MEM, 602 }, { 603 .start = gic_iid(0xb4), 604 .flags = IORESOURCE_IRQ, 605 }, 606 }; 607 608 #define R8A7779_VIN(idx) \ 609 static struct resource vin##idx##_resources[] __initdata = { \ 610 DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ 611 DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ 612 }; \ 613 \ 614 static struct platform_device_info vin##idx##_info __initdata = { \ 615 .parent = &platform_bus, \ 616 .name = "r8a7779-vin", \ 617 .id = idx, \ 618 .res = vin##idx##_resources, \ 619 .num_res = ARRAY_SIZE(vin##idx##_resources), \ 620 .dma_mask = DMA_BIT_MASK(32), \ 621 } 622 623 R8A7779_VIN(0); 624 R8A7779_VIN(1); 625 R8A7779_VIN(2); 626 R8A7779_VIN(3); 627 628 static struct platform_device_info *vin_info_table[] __initdata = { 629 &vin0_info, 630 &vin1_info, 631 &vin2_info, 632 &vin3_info, 633 }; 634 635 static struct platform_device *r8a7779_devices_dt[] __initdata = { 636 &scif0_device, 637 &scif1_device, 638 &scif2_device, 639 &scif3_device, 640 &scif4_device, 641 &scif5_device, 642 &tmu00_device, 643 &tmu01_device, 644 }; 645 646 static struct platform_device *r8a7779_standard_devices[] __initdata = { 647 &i2c0_device, 648 &i2c1_device, 649 &i2c2_device, 650 &i2c3_device, 651 &sata_device, 652 }; 653 654 void __init r8a7779_add_standard_devices(void) 655 { 656 #ifdef CONFIG_CACHE_L2X0 657 /* Early BRESP enable, Shared attribute override enable, 64K*16way */ 658 l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff); 659 #endif 660 r8a7779_pm_init(); 661 662 r8a7779_init_pm_domains(); 663 664 platform_add_devices(r8a7779_devices_dt, 665 ARRAY_SIZE(r8a7779_devices_dt)); 666 platform_add_devices(r8a7779_standard_devices, 667 ARRAY_SIZE(r8a7779_standard_devices)); 668 } 669 670 void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) 671 { 672 platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, 673 ether_resources, 674 ARRAY_SIZE(ether_resources), 675 pdata, sizeof(*pdata)); 676 } 677 678 void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata) 679 { 680 BUG_ON(id < 0 || id > 3); 681 682 vin_info_table[id]->data = pdata; 683 vin_info_table[id]->size_data = sizeof(*pdata); 684 685 platform_device_register_full(vin_info_table[id]); 686 } 687 688 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 689 void __init __weak r8a7779_register_twd(void) { } 690 691 void __init r8a7779_earlytimer_init(void) 692 { 693 r8a7779_clock_init(); 694 r8a7779_register_twd(); 695 shmobile_earlytimer_init(); 696 } 697 698 void __init r8a7779_add_early_devices(void) 699 { 700 early_platform_add_devices(r8a7779_devices_dt, 701 ARRAY_SIZE(r8a7779_devices_dt)); 702 703 /* Early serial console setup is not included here due to 704 * memory map collisions. The SCIF serial ports in r8a7779 705 * are difficult to entity map 1:1 due to collision with the 706 * virtual memory range used by the coherent DMA code on ARM. 707 * 708 * Anyone wanting to debug early can remove UPF_IOREMAP from 709 * the sh-sci serial console platform data, adjust mapbase 710 * to a static M:N virt:phys mapping that needs to be added to 711 * the mappings passed with iotable_init() above. 712 * 713 * Then add a call to shmobile_setup_console() from this function. 714 * 715 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel 716 * command line in case of the marzen board. 717 */ 718 } 719 720 static struct platform_device *r8a7779_late_devices[] __initdata = { 721 &ehci0_device, 722 &ehci1_device, 723 &ohci0_device, 724 &ohci1_device, 725 }; 726 727 void __init r8a7779_init_late(void) 728 { 729 /* get USB PHY */ 730 phy = usb_get_phy(USB_PHY_TYPE_USB2); 731 732 shmobile_init_late(); 733 platform_add_devices(r8a7779_late_devices, 734 ARRAY_SIZE(r8a7779_late_devices)); 735 } 736 737 #ifdef CONFIG_USE_OF 738 static int r8a7779_set_wake(struct irq_data *data, unsigned int on) 739 { 740 return 0; /* always allow wakeup */ 741 } 742 743 void __init r8a7779_init_irq_dt(void) 744 { 745 gic_arch_extn.irq_set_wake = r8a7779_set_wake; 746 747 irqchip_init(); 748 749 /* route all interrupts to ARM */ 750 __raw_writel(0xffffffff, INT2NTSR0); 751 __raw_writel(0x3fffffff, INT2NTSR1); 752 753 /* unmask all known interrupts in INTCS2 */ 754 __raw_writel(0xfffffff0, INT2SMSKCR0); 755 __raw_writel(0xfff7ffff, INT2SMSKCR1); 756 __raw_writel(0xfffbffdf, INT2SMSKCR2); 757 __raw_writel(0xbffffffc, INT2SMSKCR3); 758 __raw_writel(0x003fee3f, INT2SMSKCR4); 759 } 760 761 void __init r8a7779_init_delay(void) 762 { 763 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ 764 } 765 766 void __init r8a7779_add_standard_devices_dt(void) 767 { 768 /* clocks are setup late during boot in the case of DT */ 769 r8a7779_clock_init(); 770 771 platform_add_devices(r8a7779_devices_dt, 772 ARRAY_SIZE(r8a7779_devices_dt)); 773 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 774 } 775 776 static const char *r8a7779_compat_dt[] __initdata = { 777 "renesas,r8a7779", 778 NULL, 779 }; 780 781 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") 782 .map_io = r8a7779_map_io, 783 .init_early = r8a7779_init_delay, 784 .nr_irqs = NR_IRQS_LEGACY, 785 .init_irq = r8a7779_init_irq_dt, 786 .init_machine = r8a7779_add_standard_devices_dt, 787 .init_late = r8a7779_init_late, 788 .dt_compat = r8a7779_compat_dt, 789 MACHINE_END 790 #endif /* CONFIG_USE_OF */ 791