1f411fadeSMagnus Damm /* 2f411fadeSMagnus Damm * r8a7779 processor support 3f411fadeSMagnus Damm * 4dace48d0SSergei Shtylyov * Copyright (C) 2011, 2013 Renesas Solutions Corp. 5f411fadeSMagnus Damm * Copyright (C) 2011 Magnus Damm 6dace48d0SSergei Shtylyov * Copyright (C) 2013 Cogent Embedded, Inc. 7f411fadeSMagnus Damm * 8f411fadeSMagnus Damm * This program is free software; you can redistribute it and/or modify 9f411fadeSMagnus Damm * it under the terms of the GNU General Public License as published by 10f411fadeSMagnus Damm * the Free Software Foundation; version 2 of the License. 11f411fadeSMagnus Damm * 12f411fadeSMagnus Damm * This program is distributed in the hope that it will be useful, 13f411fadeSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 14f411fadeSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15f411fadeSMagnus Damm * GNU General Public License for more details. 16f411fadeSMagnus Damm * 17f411fadeSMagnus Damm * You should have received a copy of the GNU General Public License 18f411fadeSMagnus Damm * along with this program; if not, write to the Free Software 19f411fadeSMagnus Damm * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20f411fadeSMagnus Damm */ 21f411fadeSMagnus Damm #include <linux/kernel.h> 22f411fadeSMagnus Damm #include <linux/init.h> 23f411fadeSMagnus Damm #include <linux/interrupt.h> 24f411fadeSMagnus Damm #include <linux/irq.h> 255b3859d7SKuninori Morimoto #include <linux/irqchip.h> 265b3859d7SKuninori Morimoto #include <linux/irqchip/arm-gic.h> 2710e8d4f6SSimon Horman #include <linux/of_platform.h> 28441f7502SMax Filippov #include <linux/platform_data/dma-rcar-hpbdma.h> 2937a72d07SLaurent Pinchart #include <linux/platform_data/gpio-rcar.h> 305b3859d7SKuninori Morimoto #include <linux/platform_data/irq-renesas-intc-irqpin.h> 31f411fadeSMagnus Damm #include <linux/platform_device.h> 32f411fadeSMagnus Damm #include <linux/delay.h> 33f411fadeSMagnus Damm #include <linux/input.h> 34f411fadeSMagnus Damm #include <linux/io.h> 35f411fadeSMagnus Damm #include <linux/serial_sci.h> 36f411fadeSMagnus Damm #include <linux/sh_timer.h> 37a7b9837cSVladimir Barinov #include <linux/dma-mapping.h> 382c8788bfSSergei Shtylyov #include <linux/usb/otg.h> 3984a812daSSergei Shtylyov #include <linux/usb/hcd.h> 402c8788bfSSergei Shtylyov #include <linux/usb/ehci_pdriver.h> 412c8788bfSSergei Shtylyov #include <linux/usb/ohci_pdriver.h> 422c8788bfSSergei Shtylyov #include <linux/pm_runtime.h> 43250a2723SRob Herring #include <mach/irqs.h> 44f411fadeSMagnus Damm #include <mach/r8a7779.h> 45a662c082SMagnus Damm #include <mach/common.h> 46f411fadeSMagnus Damm #include <asm/mach-types.h> 47f411fadeSMagnus Damm #include <asm/mach/arch.h> 48df27a2d8SMagnus Damm #include <asm/mach/time.h> 493e353b87SMagnus Damm #include <asm/mach/map.h> 508bac13f5SMagnus Damm #include <asm/hardware/cache-l2x0.h> 513e353b87SMagnus Damm 523e353b87SMagnus Damm static struct map_desc r8a7779_io_desc[] __initdata = { 533e353b87SMagnus Damm /* 2M entity map for 0xf0000000 (MPCORE) */ 543e353b87SMagnus Damm { 553e353b87SMagnus Damm .virtual = 0xf0000000, 563e353b87SMagnus Damm .pfn = __phys_to_pfn(0xf0000000), 573e353b87SMagnus Damm .length = SZ_2M, 583e353b87SMagnus Damm .type = MT_DEVICE_NONSHARED 593e353b87SMagnus Damm }, 603e353b87SMagnus Damm /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ 613e353b87SMagnus Damm { 623e353b87SMagnus Damm .virtual = 0xfe000000, 633e353b87SMagnus Damm .pfn = __phys_to_pfn(0xfe000000), 643e353b87SMagnus Damm .length = SZ_16M, 653e353b87SMagnus Damm .type = MT_DEVICE_NONSHARED 663e353b87SMagnus Damm }, 673e353b87SMagnus Damm }; 683e353b87SMagnus Damm 693e353b87SMagnus Damm void __init r8a7779_map_io(void) 703e353b87SMagnus Damm { 713e353b87SMagnus Damm iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); 723e353b87SMagnus Damm } 73f411fadeSMagnus Damm 745b3859d7SKuninori Morimoto /* IRQ */ 755b3859d7SKuninori Morimoto #define INT2SMSKCR0 IOMEM(0xfe7822a0) 765b3859d7SKuninori Morimoto #define INT2SMSKCR1 IOMEM(0xfe7822a4) 775b3859d7SKuninori Morimoto #define INT2SMSKCR2 IOMEM(0xfe7822a8) 785b3859d7SKuninori Morimoto #define INT2SMSKCR3 IOMEM(0xfe7822ac) 795b3859d7SKuninori Morimoto #define INT2SMSKCR4 IOMEM(0xfe7822b0) 805b3859d7SKuninori Morimoto 815b3859d7SKuninori Morimoto #define INT2NTSR0 IOMEM(0xfe700060) 825b3859d7SKuninori Morimoto #define INT2NTSR1 IOMEM(0xfe700064) 835b3859d7SKuninori Morimoto 845b3859d7SKuninori Morimoto static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = { 855b3859d7SKuninori Morimoto .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 865b3859d7SKuninori Morimoto .sense_bitfield_width = 2, 875b3859d7SKuninori Morimoto }; 885b3859d7SKuninori Morimoto 895b3859d7SKuninori Morimoto static struct resource irqpin0_resources[] __initdata = { 905b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 915b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 925b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 935b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 945b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 955b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ 965b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ 975b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ 985b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ 995b3859d7SKuninori Morimoto }; 1005b3859d7SKuninori Morimoto 10131e4e292SKuninori Morimoto void __init r8a7779_init_irq_extpin_dt(int irlm) 1025b3859d7SKuninori Morimoto { 1035b3859d7SKuninori Morimoto void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 1045b3859d7SKuninori Morimoto u32 tmp; 1055b3859d7SKuninori Morimoto 1065b3859d7SKuninori Morimoto if (!icr0) { 1075b3859d7SKuninori Morimoto pr_warn("r8a7779: unable to setup external irq pin mode\n"); 1085b3859d7SKuninori Morimoto return; 1095b3859d7SKuninori Morimoto } 1105b3859d7SKuninori Morimoto 1115b3859d7SKuninori Morimoto tmp = ioread32(icr0); 1125b3859d7SKuninori Morimoto if (irlm) 1135b3859d7SKuninori Morimoto tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 1145b3859d7SKuninori Morimoto else 1155b3859d7SKuninori Morimoto tmp &= ~(1 << 23); /* IRL mode - not supported */ 1165b3859d7SKuninori Morimoto tmp |= (1 << 21); /* LVLMODE = 1 */ 1175b3859d7SKuninori Morimoto iowrite32(tmp, icr0); 1185b3859d7SKuninori Morimoto iounmap(icr0); 11931e4e292SKuninori Morimoto } 1205b3859d7SKuninori Morimoto 12131e4e292SKuninori Morimoto void __init r8a7779_init_irq_extpin(int irlm) 12231e4e292SKuninori Morimoto { 12331e4e292SKuninori Morimoto r8a7779_init_irq_extpin_dt(irlm); 1245b3859d7SKuninori Morimoto if (irlm) 1255b3859d7SKuninori Morimoto platform_device_register_resndata( 1265b3859d7SKuninori Morimoto &platform_bus, "renesas_intc_irqpin", -1, 1275b3859d7SKuninori Morimoto irqpin0_resources, ARRAY_SIZE(irqpin0_resources), 1285b3859d7SKuninori Morimoto &irqpin0_platform_data, sizeof(irqpin0_platform_data)); 1295b3859d7SKuninori Morimoto } 1305b3859d7SKuninori Morimoto 1315b3859d7SKuninori Morimoto /* PFC/GPIO */ 1328b6edf36SLaurent Pinchart static struct resource r8a7779_pfc_resources[] = { 1330ccaf5bbSMagnus Damm DEFINE_RES_MEM(0xfffc0000, 0x023c), 1348b6edf36SLaurent Pinchart }; 1358b6edf36SLaurent Pinchart 1368b6edf36SLaurent Pinchart static struct platform_device r8a7779_pfc_device = { 1378b6edf36SLaurent Pinchart .name = "pfc-r8a7779", 1388b6edf36SLaurent Pinchart .id = -1, 1398b6edf36SLaurent Pinchart .resource = r8a7779_pfc_resources, 1408b6edf36SLaurent Pinchart .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), 1418b6edf36SLaurent Pinchart }; 1428b6edf36SLaurent Pinchart 14337a72d07SLaurent Pinchart #define R8A7779_GPIO(idx, npins) \ 14437a72d07SLaurent Pinchart static struct resource r8a7779_gpio##idx##_resources[] = { \ 1450ccaf5bbSMagnus Damm DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \ 1460ccaf5bbSMagnus Damm DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \ 14737a72d07SLaurent Pinchart }; \ 14837a72d07SLaurent Pinchart \ 14937a72d07SLaurent Pinchart static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ 15037a72d07SLaurent Pinchart .gpio_base = 32 * (idx), \ 15137a72d07SLaurent Pinchart .irq_base = 0, \ 15237a72d07SLaurent Pinchart .number_of_pins = npins, \ 15337a72d07SLaurent Pinchart .pctl_name = "pfc-r8a7779", \ 15437a72d07SLaurent Pinchart }; \ 15537a72d07SLaurent Pinchart \ 15637a72d07SLaurent Pinchart static struct platform_device r8a7779_gpio##idx##_device = { \ 15737a72d07SLaurent Pinchart .name = "gpio_rcar", \ 15837a72d07SLaurent Pinchart .id = idx, \ 15937a72d07SLaurent Pinchart .resource = r8a7779_gpio##idx##_resources, \ 16037a72d07SLaurent Pinchart .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \ 16137a72d07SLaurent Pinchart .dev = { \ 16237a72d07SLaurent Pinchart .platform_data = &r8a7779_gpio##idx##_platform_data, \ 16337a72d07SLaurent Pinchart }, \ 16437a72d07SLaurent Pinchart } 16537a72d07SLaurent Pinchart 16637a72d07SLaurent Pinchart R8A7779_GPIO(0, 32); 16737a72d07SLaurent Pinchart R8A7779_GPIO(1, 32); 16837a72d07SLaurent Pinchart R8A7779_GPIO(2, 32); 16937a72d07SLaurent Pinchart R8A7779_GPIO(3, 32); 17037a72d07SLaurent Pinchart R8A7779_GPIO(4, 32); 17137a72d07SLaurent Pinchart R8A7779_GPIO(5, 32); 17237a72d07SLaurent Pinchart R8A7779_GPIO(6, 9); 17337a72d07SLaurent Pinchart 17437a72d07SLaurent Pinchart static struct platform_device *r8a7779_pinctrl_devices[] __initdata = { 17537a72d07SLaurent Pinchart &r8a7779_pfc_device, 17637a72d07SLaurent Pinchart &r8a7779_gpio0_device, 17737a72d07SLaurent Pinchart &r8a7779_gpio1_device, 17837a72d07SLaurent Pinchart &r8a7779_gpio2_device, 17937a72d07SLaurent Pinchart &r8a7779_gpio3_device, 18037a72d07SLaurent Pinchart &r8a7779_gpio4_device, 18137a72d07SLaurent Pinchart &r8a7779_gpio5_device, 18237a72d07SLaurent Pinchart &r8a7779_gpio6_device, 18337a72d07SLaurent Pinchart }; 18437a72d07SLaurent Pinchart 1858b6edf36SLaurent Pinchart void __init r8a7779_pinmux_init(void) 1868b6edf36SLaurent Pinchart { 18737a72d07SLaurent Pinchart platform_add_devices(r8a7779_pinctrl_devices, 18837a72d07SLaurent Pinchart ARRAY_SIZE(r8a7779_pinctrl_devices)); 1898b6edf36SLaurent Pinchart } 1908b6edf36SLaurent Pinchart 191efced000SLaurent Pinchart /* SCIF */ 192efced000SLaurent Pinchart #define R8A7779_SCIF(index, baseaddr, irq) \ 193efced000SLaurent Pinchart static struct plat_sci_port scif##index##_platform_data = { \ 194efced000SLaurent Pinchart .type = PORT_SCIF, \ 195efced000SLaurent Pinchart .mapbase = baseaddr, \ 196efced000SLaurent Pinchart .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 197efced000SLaurent Pinchart .irqs = SCIx_IRQ_MUXED(irq), \ 198efced000SLaurent Pinchart .scbrr_algo_id = SCBRR_ALGO_2, \ 199efced000SLaurent Pinchart .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 200efced000SLaurent Pinchart }; \ 201efced000SLaurent Pinchart \ 202efced000SLaurent Pinchart static struct platform_device scif##index##_device = { \ 203efced000SLaurent Pinchart .name = "sh-sci", \ 204efced000SLaurent Pinchart .id = index, \ 205efced000SLaurent Pinchart .dev = { \ 206efced000SLaurent Pinchart .platform_data = &scif##index##_platform_data, \ 207efced000SLaurent Pinchart }, \ 208efced000SLaurent Pinchart } 209f411fadeSMagnus Damm 210efced000SLaurent Pinchart R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78)); 211efced000SLaurent Pinchart R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79)); 212efced000SLaurent Pinchart R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a)); 213efced000SLaurent Pinchart R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b)); 214efced000SLaurent Pinchart R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c)); 215efced000SLaurent Pinchart R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d)); 216f411fadeSMagnus Damm 217f411fadeSMagnus Damm /* TMU */ 218f411fadeSMagnus Damm static struct sh_timer_config tmu00_platform_data = { 219f411fadeSMagnus Damm .name = "TMU00", 220f411fadeSMagnus Damm .channel_offset = 0x4, 221f411fadeSMagnus Damm .timer_bit = 0, 222f411fadeSMagnus Damm .clockevent_rating = 200, 223f411fadeSMagnus Damm }; 224f411fadeSMagnus Damm 225f411fadeSMagnus Damm static struct resource tmu00_resources[] = { 226f411fadeSMagnus Damm [0] = { 227f411fadeSMagnus Damm .name = "TMU00", 228f411fadeSMagnus Damm .start = 0xffd80008, 229f411fadeSMagnus Damm .end = 0xffd80013, 230f411fadeSMagnus Damm .flags = IORESOURCE_MEM, 231f411fadeSMagnus Damm }, 232f411fadeSMagnus Damm [1] = { 233dbe95ad0SKuninori Morimoto .start = gic_iid(0x40), 234f411fadeSMagnus Damm .flags = IORESOURCE_IRQ, 235f411fadeSMagnus Damm }, 236f411fadeSMagnus Damm }; 237f411fadeSMagnus Damm 238f411fadeSMagnus Damm static struct platform_device tmu00_device = { 239f411fadeSMagnus Damm .name = "sh_tmu", 240f411fadeSMagnus Damm .id = 0, 241f411fadeSMagnus Damm .dev = { 242f411fadeSMagnus Damm .platform_data = &tmu00_platform_data, 243f411fadeSMagnus Damm }, 244f411fadeSMagnus Damm .resource = tmu00_resources, 245f411fadeSMagnus Damm .num_resources = ARRAY_SIZE(tmu00_resources), 246f411fadeSMagnus Damm }; 247f411fadeSMagnus Damm 248f411fadeSMagnus Damm static struct sh_timer_config tmu01_platform_data = { 249f411fadeSMagnus Damm .name = "TMU01", 250f411fadeSMagnus Damm .channel_offset = 0x10, 251f411fadeSMagnus Damm .timer_bit = 1, 252f411fadeSMagnus Damm .clocksource_rating = 200, 253f411fadeSMagnus Damm }; 254f411fadeSMagnus Damm 255f411fadeSMagnus Damm static struct resource tmu01_resources[] = { 256f411fadeSMagnus Damm [0] = { 257f411fadeSMagnus Damm .name = "TMU01", 258f411fadeSMagnus Damm .start = 0xffd80014, 259f411fadeSMagnus Damm .end = 0xffd8001f, 260f411fadeSMagnus Damm .flags = IORESOURCE_MEM, 261f411fadeSMagnus Damm }, 262f411fadeSMagnus Damm [1] = { 263dbe95ad0SKuninori Morimoto .start = gic_iid(0x41), 264f411fadeSMagnus Damm .flags = IORESOURCE_IRQ, 265f411fadeSMagnus Damm }, 266f411fadeSMagnus Damm }; 267f411fadeSMagnus Damm 268f411fadeSMagnus Damm static struct platform_device tmu01_device = { 269f411fadeSMagnus Damm .name = "sh_tmu", 270f411fadeSMagnus Damm .id = 1, 271f411fadeSMagnus Damm .dev = { 272f411fadeSMagnus Damm .platform_data = &tmu01_platform_data, 273f411fadeSMagnus Damm }, 274f411fadeSMagnus Damm .resource = tmu01_resources, 275f411fadeSMagnus Damm .num_resources = ARRAY_SIZE(tmu01_resources), 276f411fadeSMagnus Damm }; 277f411fadeSMagnus Damm 278ccc2a27bSKuninori Morimoto /* I2C */ 279ccc2a27bSKuninori Morimoto static struct resource rcar_i2c0_res[] = { 280ccc2a27bSKuninori Morimoto { 281ccc2a27bSKuninori Morimoto .start = 0xffc70000, 282ccc2a27bSKuninori Morimoto .end = 0xffc70fff, 283ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 284ccc2a27bSKuninori Morimoto }, { 285dbe95ad0SKuninori Morimoto .start = gic_iid(0x6f), 286ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 287ccc2a27bSKuninori Morimoto }, 288ccc2a27bSKuninori Morimoto }; 289ccc2a27bSKuninori Morimoto 290ccc2a27bSKuninori Morimoto static struct platform_device i2c0_device = { 291ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 292ccc2a27bSKuninori Morimoto .id = 0, 293ccc2a27bSKuninori Morimoto .resource = rcar_i2c0_res, 294ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c0_res), 295ccc2a27bSKuninori Morimoto }; 296ccc2a27bSKuninori Morimoto 297ccc2a27bSKuninori Morimoto static struct resource rcar_i2c1_res[] = { 298ccc2a27bSKuninori Morimoto { 299ccc2a27bSKuninori Morimoto .start = 0xffc71000, 300ccc2a27bSKuninori Morimoto .end = 0xffc71fff, 301ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 302ccc2a27bSKuninori Morimoto }, { 303dbe95ad0SKuninori Morimoto .start = gic_iid(0x72), 304ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 305ccc2a27bSKuninori Morimoto }, 306ccc2a27bSKuninori Morimoto }; 307ccc2a27bSKuninori Morimoto 308ccc2a27bSKuninori Morimoto static struct platform_device i2c1_device = { 309ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 310ccc2a27bSKuninori Morimoto .id = 1, 311ccc2a27bSKuninori Morimoto .resource = rcar_i2c1_res, 312ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c1_res), 313ccc2a27bSKuninori Morimoto }; 314ccc2a27bSKuninori Morimoto 315ccc2a27bSKuninori Morimoto static struct resource rcar_i2c2_res[] = { 316ccc2a27bSKuninori Morimoto { 317ccc2a27bSKuninori Morimoto .start = 0xffc72000, 318ccc2a27bSKuninori Morimoto .end = 0xffc72fff, 319ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 320ccc2a27bSKuninori Morimoto }, { 321dbe95ad0SKuninori Morimoto .start = gic_iid(0x70), 322ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 323ccc2a27bSKuninori Morimoto }, 324ccc2a27bSKuninori Morimoto }; 325ccc2a27bSKuninori Morimoto 326ccc2a27bSKuninori Morimoto static struct platform_device i2c2_device = { 327ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 328ccc2a27bSKuninori Morimoto .id = 2, 329ccc2a27bSKuninori Morimoto .resource = rcar_i2c2_res, 330ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c2_res), 331ccc2a27bSKuninori Morimoto }; 332ccc2a27bSKuninori Morimoto 333ccc2a27bSKuninori Morimoto static struct resource rcar_i2c3_res[] = { 334ccc2a27bSKuninori Morimoto { 335ccc2a27bSKuninori Morimoto .start = 0xffc73000, 336ccc2a27bSKuninori Morimoto .end = 0xffc73fff, 337ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 338ccc2a27bSKuninori Morimoto }, { 339dbe95ad0SKuninori Morimoto .start = gic_iid(0x71), 340ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 341ccc2a27bSKuninori Morimoto }, 342ccc2a27bSKuninori Morimoto }; 343ccc2a27bSKuninori Morimoto 344ccc2a27bSKuninori Morimoto static struct platform_device i2c3_device = { 345ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 346ccc2a27bSKuninori Morimoto .id = 3, 347ccc2a27bSKuninori Morimoto .resource = rcar_i2c3_res, 348ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c3_res), 349ccc2a27bSKuninori Morimoto }; 350ccc2a27bSKuninori Morimoto 351a7b9837cSVladimir Barinov static struct resource sata_resources[] = { 352a7b9837cSVladimir Barinov [0] = { 353a7b9837cSVladimir Barinov .name = "rcar-sata", 354a7b9837cSVladimir Barinov .start = 0xfc600000, 355a7b9837cSVladimir Barinov .end = 0xfc601fff, 356a7b9837cSVladimir Barinov .flags = IORESOURCE_MEM, 357a7b9837cSVladimir Barinov }, 358a7b9837cSVladimir Barinov [1] = { 359d60cd5f1SSergei Shtylyov .start = gic_iid(0x84), 360a7b9837cSVladimir Barinov .flags = IORESOURCE_IRQ, 361a7b9837cSVladimir Barinov }, 362a7b9837cSVladimir Barinov }; 363a7b9837cSVladimir Barinov 364a7b9837cSVladimir Barinov static struct platform_device sata_device = { 365a7b9837cSVladimir Barinov .name = "sata_rcar", 366a7b9837cSVladimir Barinov .id = -1, 367a7b9837cSVladimir Barinov .resource = sata_resources, 368a7b9837cSVladimir Barinov .num_resources = ARRAY_SIZE(sata_resources), 369a7b9837cSVladimir Barinov .dev = { 370a7b9837cSVladimir Barinov .dma_mask = &sata_device.dev.coherent_dma_mask, 371a7b9837cSVladimir Barinov .coherent_dma_mask = DMA_BIT_MASK(32), 372a7b9837cSVladimir Barinov }, 373a7b9837cSVladimir Barinov }; 374a7b9837cSVladimir Barinov 3752c8788bfSSergei Shtylyov /* USB */ 3762c8788bfSSergei Shtylyov static struct usb_phy *phy; 3772c8788bfSSergei Shtylyov 3782c8788bfSSergei Shtylyov static int usb_power_on(struct platform_device *pdev) 3792c8788bfSSergei Shtylyov { 3802c8788bfSSergei Shtylyov if (IS_ERR(phy)) 3812c8788bfSSergei Shtylyov return PTR_ERR(phy); 3822c8788bfSSergei Shtylyov 3832c8788bfSSergei Shtylyov pm_runtime_enable(&pdev->dev); 3842c8788bfSSergei Shtylyov pm_runtime_get_sync(&pdev->dev); 3852c8788bfSSergei Shtylyov 3862c8788bfSSergei Shtylyov usb_phy_init(phy); 3872c8788bfSSergei Shtylyov 3882c8788bfSSergei Shtylyov return 0; 3892c8788bfSSergei Shtylyov } 3902c8788bfSSergei Shtylyov 3912c8788bfSSergei Shtylyov static void usb_power_off(struct platform_device *pdev) 3922c8788bfSSergei Shtylyov { 3932c8788bfSSergei Shtylyov if (IS_ERR(phy)) 3942c8788bfSSergei Shtylyov return; 3952c8788bfSSergei Shtylyov 3962c8788bfSSergei Shtylyov usb_phy_shutdown(phy); 3972c8788bfSSergei Shtylyov 3982c8788bfSSergei Shtylyov pm_runtime_put_sync(&pdev->dev); 3992c8788bfSSergei Shtylyov pm_runtime_disable(&pdev->dev); 4002c8788bfSSergei Shtylyov } 4012c8788bfSSergei Shtylyov 40284a812daSSergei Shtylyov static int ehci_init_internal_buffer(struct usb_hcd *hcd) 40384a812daSSergei Shtylyov { 40484a812daSSergei Shtylyov /* 40584a812daSSergei Shtylyov * Below are recommended values from the datasheet; 40684a812daSSergei Shtylyov * see [USB :: Setting of EHCI Internal Buffer]. 40784a812daSSergei Shtylyov */ 40884a812daSSergei Shtylyov /* EHCI IP internal buffer setting */ 40984a812daSSergei Shtylyov iowrite32(0x00ff0040, hcd->regs + 0x0094); 41084a812daSSergei Shtylyov /* EHCI IP internal buffer enable */ 41184a812daSSergei Shtylyov iowrite32(0x00000001, hcd->regs + 0x009C); 41284a812daSSergei Shtylyov 41384a812daSSergei Shtylyov return 0; 41484a812daSSergei Shtylyov } 41584a812daSSergei Shtylyov 4162c8788bfSSergei Shtylyov static struct usb_ehci_pdata ehcix_pdata = { 4172c8788bfSSergei Shtylyov .power_on = usb_power_on, 4182c8788bfSSergei Shtylyov .power_off = usb_power_off, 4192c8788bfSSergei Shtylyov .power_suspend = usb_power_off, 42084a812daSSergei Shtylyov .pre_setup = ehci_init_internal_buffer, 4212c8788bfSSergei Shtylyov }; 4222c8788bfSSergei Shtylyov 4232c8788bfSSergei Shtylyov static struct resource ehci0_resources[] = { 4242c8788bfSSergei Shtylyov [0] = { 4252c8788bfSSergei Shtylyov .start = 0xffe70000, 4262c8788bfSSergei Shtylyov .end = 0xffe70400 - 1, 4272c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 4282c8788bfSSergei Shtylyov }, 4292c8788bfSSergei Shtylyov [1] = { 4302c8788bfSSergei Shtylyov .start = gic_iid(0x4c), 4312c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 4322c8788bfSSergei Shtylyov }, 4332c8788bfSSergei Shtylyov }; 4342c8788bfSSergei Shtylyov 4352c8788bfSSergei Shtylyov static struct platform_device ehci0_device = { 4362c8788bfSSergei Shtylyov .name = "ehci-platform", 4372c8788bfSSergei Shtylyov .id = 0, 4382c8788bfSSergei Shtylyov .dev = { 4392c8788bfSSergei Shtylyov .dma_mask = &ehci0_device.dev.coherent_dma_mask, 4402c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 4412c8788bfSSergei Shtylyov .platform_data = &ehcix_pdata, 4422c8788bfSSergei Shtylyov }, 4432c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ehci0_resources), 4442c8788bfSSergei Shtylyov .resource = ehci0_resources, 4452c8788bfSSergei Shtylyov }; 4462c8788bfSSergei Shtylyov 4472c8788bfSSergei Shtylyov static struct resource ehci1_resources[] = { 4482c8788bfSSergei Shtylyov [0] = { 4492c8788bfSSergei Shtylyov .start = 0xfff70000, 4502c8788bfSSergei Shtylyov .end = 0xfff70400 - 1, 4512c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 4522c8788bfSSergei Shtylyov }, 4532c8788bfSSergei Shtylyov [1] = { 4542c8788bfSSergei Shtylyov .start = gic_iid(0x4d), 4552c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 4562c8788bfSSergei Shtylyov }, 4572c8788bfSSergei Shtylyov }; 4582c8788bfSSergei Shtylyov 4592c8788bfSSergei Shtylyov static struct platform_device ehci1_device = { 4602c8788bfSSergei Shtylyov .name = "ehci-platform", 4612c8788bfSSergei Shtylyov .id = 1, 4622c8788bfSSergei Shtylyov .dev = { 4632c8788bfSSergei Shtylyov .dma_mask = &ehci1_device.dev.coherent_dma_mask, 4642c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 4652c8788bfSSergei Shtylyov .platform_data = &ehcix_pdata, 4662c8788bfSSergei Shtylyov }, 4672c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ehci1_resources), 4682c8788bfSSergei Shtylyov .resource = ehci1_resources, 4692c8788bfSSergei Shtylyov }; 4702c8788bfSSergei Shtylyov 4712c8788bfSSergei Shtylyov static struct usb_ohci_pdata ohcix_pdata = { 4722c8788bfSSergei Shtylyov .power_on = usb_power_on, 4732c8788bfSSergei Shtylyov .power_off = usb_power_off, 4742c8788bfSSergei Shtylyov .power_suspend = usb_power_off, 4752c8788bfSSergei Shtylyov }; 4762c8788bfSSergei Shtylyov 4772c8788bfSSergei Shtylyov static struct resource ohci0_resources[] = { 4782c8788bfSSergei Shtylyov [0] = { 4792c8788bfSSergei Shtylyov .start = 0xffe70400, 4802c8788bfSSergei Shtylyov .end = 0xffe70800 - 1, 4812c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 4822c8788bfSSergei Shtylyov }, 4832c8788bfSSergei Shtylyov [1] = { 4842c8788bfSSergei Shtylyov .start = gic_iid(0x4c), 4852c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 4862c8788bfSSergei Shtylyov }, 4872c8788bfSSergei Shtylyov }; 4882c8788bfSSergei Shtylyov 4892c8788bfSSergei Shtylyov static struct platform_device ohci0_device = { 4902c8788bfSSergei Shtylyov .name = "ohci-platform", 4912c8788bfSSergei Shtylyov .id = 0, 4922c8788bfSSergei Shtylyov .dev = { 4932c8788bfSSergei Shtylyov .dma_mask = &ohci0_device.dev.coherent_dma_mask, 4942c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 4952c8788bfSSergei Shtylyov .platform_data = &ohcix_pdata, 4962c8788bfSSergei Shtylyov }, 4972c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ohci0_resources), 4982c8788bfSSergei Shtylyov .resource = ohci0_resources, 4992c8788bfSSergei Shtylyov }; 5002c8788bfSSergei Shtylyov 5012c8788bfSSergei Shtylyov static struct resource ohci1_resources[] = { 5022c8788bfSSergei Shtylyov [0] = { 5032c8788bfSSergei Shtylyov .start = 0xfff70400, 5042c8788bfSSergei Shtylyov .end = 0xfff70800 - 1, 5052c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 5062c8788bfSSergei Shtylyov }, 5072c8788bfSSergei Shtylyov [1] = { 5082c8788bfSSergei Shtylyov .start = gic_iid(0x4d), 5092c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 5102c8788bfSSergei Shtylyov }, 5112c8788bfSSergei Shtylyov }; 5122c8788bfSSergei Shtylyov 5132c8788bfSSergei Shtylyov static struct platform_device ohci1_device = { 5142c8788bfSSergei Shtylyov .name = "ohci-platform", 5152c8788bfSSergei Shtylyov .id = 1, 5162c8788bfSSergei Shtylyov .dev = { 5172c8788bfSSergei Shtylyov .dma_mask = &ohci1_device.dev.coherent_dma_mask, 5182c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 5192c8788bfSSergei Shtylyov .platform_data = &ohcix_pdata, 5202c8788bfSSergei Shtylyov }, 5212c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ohci1_resources), 5222c8788bfSSergei Shtylyov .resource = ohci1_resources, 5232c8788bfSSergei Shtylyov }; 5242c8788bfSSergei Shtylyov 525dace48d0SSergei Shtylyov /* Ether */ 526c7537655SKuninori Morimoto static struct resource ether_resources[] __initdata = { 527dace48d0SSergei Shtylyov { 528dace48d0SSergei Shtylyov .start = 0xfde00000, 529dace48d0SSergei Shtylyov .end = 0xfde003ff, 530dace48d0SSergei Shtylyov .flags = IORESOURCE_MEM, 531dace48d0SSergei Shtylyov }, { 532dace48d0SSergei Shtylyov .start = gic_iid(0xb4), 533dace48d0SSergei Shtylyov .flags = IORESOURCE_IRQ, 534dace48d0SSergei Shtylyov }, 535dace48d0SSergei Shtylyov }; 536dace48d0SSergei Shtylyov 5374714a025SVladimir Barinov #define R8A7779_VIN(idx) \ 5384714a025SVladimir Barinov static struct resource vin##idx##_resources[] __initdata = { \ 5394714a025SVladimir Barinov DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ 5404714a025SVladimir Barinov DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ 5414714a025SVladimir Barinov }; \ 5424714a025SVladimir Barinov \ 5434714a025SVladimir Barinov static struct platform_device_info vin##idx##_info __initdata = { \ 5444714a025SVladimir Barinov .parent = &platform_bus, \ 5454714a025SVladimir Barinov .name = "r8a7779-vin", \ 5464714a025SVladimir Barinov .id = idx, \ 5474714a025SVladimir Barinov .res = vin##idx##_resources, \ 5484714a025SVladimir Barinov .num_res = ARRAY_SIZE(vin##idx##_resources), \ 5494714a025SVladimir Barinov .dma_mask = DMA_BIT_MASK(32), \ 5504714a025SVladimir Barinov } 5514714a025SVladimir Barinov 5524714a025SVladimir Barinov R8A7779_VIN(0); 5534714a025SVladimir Barinov R8A7779_VIN(1); 5544714a025SVladimir Barinov R8A7779_VIN(2); 5554714a025SVladimir Barinov R8A7779_VIN(3); 5564714a025SVladimir Barinov 5574714a025SVladimir Barinov static struct platform_device_info *vin_info_table[] __initdata = { 5584714a025SVladimir Barinov &vin0_info, 5594714a025SVladimir Barinov &vin1_info, 5604714a025SVladimir Barinov &vin2_info, 5614714a025SVladimir Barinov &vin3_info, 5624714a025SVladimir Barinov }; 5634714a025SVladimir Barinov 564441f7502SMax Filippov /* HPB-DMA */ 565441f7502SMax Filippov 566441f7502SMax Filippov /* Asynchronous mode register bits */ 567441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */ 568441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */ 569441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */ 570441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */ 571441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */ 572441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */ 573441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */ 574441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */ 575441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */ 576441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */ 577441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */ 578441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */ 579441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */ 580441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */ 581441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */ 582441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */ 583441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */ 584441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */ 585441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */ 586441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */ 587441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */ 588441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */ 589441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */ 590441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */ 591441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */ 592441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */ 593441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */ 594441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */ 595441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */ 596441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */ 597441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */ 598441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */ 599441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */ 600441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */ 601441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */ 602441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */ 603441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */ 604441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */ 605441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */ 606441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */ 607441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */ 608441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */ 609441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */ 610441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */ 611441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */ 612441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */ 613441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */ 614441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */ 615441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */ 616441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */ 617441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */ 618441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */ 619441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */ 620441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */ 621441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */ 622441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */ 623441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ 624441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */ 625441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */ 626441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */ 627441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */ 628441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */ 629441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 630441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */ 631441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */ 632441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */ 633441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */ 634441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */ 635441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */ 636441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */ 637441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */ 638441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */ 639441f7502SMax Filippov 640441f7502SMax Filippov static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 641441f7502SMax Filippov { 642441f7502SMax Filippov .id = HPBDMA_SLAVE_SDHI0_TX, 643441f7502SMax Filippov .addr = 0xffe4c000 + 0x30, 644441f7502SMax Filippov .dcr = HPB_DMAE_DCR_SPDS_16BIT | 645441f7502SMax Filippov HPB_DMAE_DCR_DMDL | 646441f7502SMax Filippov HPB_DMAE_DCR_DPDS_16BIT, 647441f7502SMax Filippov .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 648441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST22 | 649441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST23, 650441f7502SMax Filippov .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE | 651441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST, 652441f7502SMax Filippov .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK | 653441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD21_MASK, 654441f7502SMax Filippov .port = 0x0D0C, 655441f7502SMax Filippov .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 656441f7502SMax Filippov .dma_ch = 21, 657441f7502SMax Filippov }, { 658441f7502SMax Filippov .id = HPBDMA_SLAVE_SDHI0_RX, 659441f7502SMax Filippov .addr = 0xffe4c000 + 0x30, 660441f7502SMax Filippov .dcr = HPB_DMAE_DCR_SMDL | 661441f7502SMax Filippov HPB_DMAE_DCR_SPDS_16BIT | 662441f7502SMax Filippov HPB_DMAE_DCR_DPDS_16BIT, 663441f7502SMax Filippov .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 664441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST22 | 665441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST23, 666441f7502SMax Filippov .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE | 667441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST, 668441f7502SMax Filippov .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK | 669441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD22_MASK, 670441f7502SMax Filippov .port = 0x0D0C, 671441f7502SMax Filippov .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 672441f7502SMax Filippov .dma_ch = 22, 673441f7502SMax Filippov }, 674441f7502SMax Filippov }; 675441f7502SMax Filippov 676441f7502SMax Filippov static const struct hpb_dmae_channel hpb_dmae_channels[] = { 677441f7502SMax Filippov HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 678441f7502SMax Filippov HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 679441f7502SMax Filippov }; 680441f7502SMax Filippov 681441f7502SMax Filippov static struct hpb_dmae_pdata dma_platform_data __initdata = { 682441f7502SMax Filippov .slaves = hpb_dmae_slaves, 683441f7502SMax Filippov .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), 684441f7502SMax Filippov .channels = hpb_dmae_channels, 685441f7502SMax Filippov .num_channels = ARRAY_SIZE(hpb_dmae_channels), 686441f7502SMax Filippov .ts_shift = { 687441f7502SMax Filippov [XMIT_SZ_8BIT] = 0, 688441f7502SMax Filippov [XMIT_SZ_16BIT] = 1, 689441f7502SMax Filippov [XMIT_SZ_32BIT] = 2, 690441f7502SMax Filippov }, 691441f7502SMax Filippov .num_hw_channels = 44, 692441f7502SMax Filippov }; 693441f7502SMax Filippov 694441f7502SMax Filippov static struct resource hpb_dmae_resources[] __initdata = { 695441f7502SMax Filippov /* Channel registers */ 696441f7502SMax Filippov DEFINE_RES_MEM(0xffc08000, 0x1000), 697441f7502SMax Filippov /* Common registers */ 698441f7502SMax Filippov DEFINE_RES_MEM(0xffc09000, 0x170), 699441f7502SMax Filippov /* Asynchronous reset registers */ 700441f7502SMax Filippov DEFINE_RES_MEM(0xffc00300, 4), 701441f7502SMax Filippov /* Asynchronous mode registers */ 702441f7502SMax Filippov DEFINE_RES_MEM(0xffc00400, 4), 703441f7502SMax Filippov /* IRQ for DMA channels */ 704441f7502SMax Filippov DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ), 705441f7502SMax Filippov }; 706441f7502SMax Filippov 707441f7502SMax Filippov static void __init r8a7779_register_hpb_dmae(void) 708441f7502SMax Filippov { 709441f7502SMax Filippov platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, 710441f7502SMax Filippov hpb_dmae_resources, 711441f7502SMax Filippov ARRAY_SIZE(hpb_dmae_resources), 712441f7502SMax Filippov &dma_platform_data, 713441f7502SMax Filippov sizeof(dma_platform_data)); 714441f7502SMax Filippov } 715441f7502SMax Filippov 716916ddc35SSimon Horman static struct platform_device *r8a7779_devices_dt[] __initdata = { 717f411fadeSMagnus Damm &scif0_device, 718f411fadeSMagnus Damm &scif1_device, 719f411fadeSMagnus Damm &scif2_device, 720f411fadeSMagnus Damm &scif3_device, 721f411fadeSMagnus Damm &scif4_device, 722f411fadeSMagnus Damm &scif5_device, 723f411fadeSMagnus Damm &tmu00_device, 724f411fadeSMagnus Damm &tmu01_device, 72510e8d4f6SSimon Horman }; 72610e8d4f6SSimon Horman 7272c8788bfSSergei Shtylyov static struct platform_device *r8a7779_standard_devices[] __initdata = { 728ccc2a27bSKuninori Morimoto &i2c0_device, 729ccc2a27bSKuninori Morimoto &i2c1_device, 730ccc2a27bSKuninori Morimoto &i2c2_device, 731ccc2a27bSKuninori Morimoto &i2c3_device, 732a7b9837cSVladimir Barinov &sata_device, 733f411fadeSMagnus Damm }; 734f411fadeSMagnus Damm 735f411fadeSMagnus Damm void __init r8a7779_add_standard_devices(void) 736f411fadeSMagnus Damm { 7378bac13f5SMagnus Damm #ifdef CONFIG_CACHE_L2X0 7388bac13f5SMagnus Damm /* Early BRESP enable, Shared attribute override enable, 64K*16way */ 739ed7d132aSKuninori Morimoto l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff); 7408bac13f5SMagnus Damm #endif 741a662c082SMagnus Damm r8a7779_pm_init(); 742a662c082SMagnus Damm 74345e5ca57SRafael J. Wysocki r8a7779_init_pm_domains(); 744a662c082SMagnus Damm 745916ddc35SSimon Horman platform_add_devices(r8a7779_devices_dt, 746916ddc35SSimon Horman ARRAY_SIZE(r8a7779_devices_dt)); 7472c8788bfSSergei Shtylyov platform_add_devices(r8a7779_standard_devices, 7482c8788bfSSergei Shtylyov ARRAY_SIZE(r8a7779_standard_devices)); 749441f7502SMax Filippov r8a7779_register_hpb_dmae(); 750f411fadeSMagnus Damm } 751f411fadeSMagnus Damm 752dace48d0SSergei Shtylyov void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) 753dace48d0SSergei Shtylyov { 7544c370abbSSergei Shtylyov platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, 755dace48d0SSergei Shtylyov ether_resources, 756dace48d0SSergei Shtylyov ARRAY_SIZE(ether_resources), 757dace48d0SSergei Shtylyov pdata, sizeof(*pdata)); 758dace48d0SSergei Shtylyov } 759dace48d0SSergei Shtylyov 7604714a025SVladimir Barinov void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata) 7614714a025SVladimir Barinov { 7624714a025SVladimir Barinov BUG_ON(id < 0 || id > 3); 7634714a025SVladimir Barinov 7644714a025SVladimir Barinov vin_info_table[id]->data = pdata; 7654714a025SVladimir Barinov vin_info_table[id]->size_data = sizeof(*pdata); 7664714a025SVladimir Barinov 7674714a025SVladimir Barinov platform_device_register_full(vin_info_table[id]); 7684714a025SVladimir Barinov } 7694714a025SVladimir Barinov 770b759bd11SMagnus Damm /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 771b759bd11SMagnus Damm void __init __weak r8a7779_register_twd(void) { } 772b759bd11SMagnus Damm 7736bb27d73SStephen Warren void __init r8a7779_earlytimer_init(void) 774df27a2d8SMagnus Damm { 775df27a2d8SMagnus Damm r8a7779_clock_init(); 776b759bd11SMagnus Damm r8a7779_register_twd(); 7777658ea2fSSimon Horman shmobile_earlytimer_init(); 778df27a2d8SMagnus Damm } 779df27a2d8SMagnus Damm 780f411fadeSMagnus Damm void __init r8a7779_add_early_devices(void) 781f411fadeSMagnus Damm { 782916ddc35SSimon Horman early_platform_add_devices(r8a7779_devices_dt, 783916ddc35SSimon Horman ARRAY_SIZE(r8a7779_devices_dt)); 7843e353b87SMagnus Damm 7853e353b87SMagnus Damm /* Early serial console setup is not included here due to 7863e353b87SMagnus Damm * memory map collisions. The SCIF serial ports in r8a7779 7873e353b87SMagnus Damm * are difficult to entity map 1:1 due to collision with the 7883e353b87SMagnus Damm * virtual memory range used by the coherent DMA code on ARM. 7893e353b87SMagnus Damm * 7903e353b87SMagnus Damm * Anyone wanting to debug early can remove UPF_IOREMAP from 7913e353b87SMagnus Damm * the sh-sci serial console platform data, adjust mapbase 7923e353b87SMagnus Damm * to a static M:N virt:phys mapping that needs to be added to 7933e353b87SMagnus Damm * the mappings passed with iotable_init() above. 7943e353b87SMagnus Damm * 7953e353b87SMagnus Damm * Then add a call to shmobile_setup_console() from this function. 7963e353b87SMagnus Damm * 7973e353b87SMagnus Damm * As a final step pass earlyprint=sh-sci.2,115200 on the kernel 7983e353b87SMagnus Damm * command line in case of the marzen board. 7993e353b87SMagnus Damm */ 800f411fadeSMagnus Damm } 80110e8d4f6SSimon Horman 8022c8788bfSSergei Shtylyov static struct platform_device *r8a7779_late_devices[] __initdata = { 8032c8788bfSSergei Shtylyov &ehci0_device, 8042c8788bfSSergei Shtylyov &ehci1_device, 8052c8788bfSSergei Shtylyov &ohci0_device, 8062c8788bfSSergei Shtylyov &ohci1_device, 8072c8788bfSSergei Shtylyov }; 8082c8788bfSSergei Shtylyov 8092c8788bfSSergei Shtylyov void __init r8a7779_init_late(void) 8102c8788bfSSergei Shtylyov { 8112c8788bfSSergei Shtylyov /* get USB PHY */ 8122c8788bfSSergei Shtylyov phy = usb_get_phy(USB_PHY_TYPE_USB2); 8132c8788bfSSergei Shtylyov 8142c8788bfSSergei Shtylyov shmobile_init_late(); 8152c8788bfSSergei Shtylyov platform_add_devices(r8a7779_late_devices, 8162c8788bfSSergei Shtylyov ARRAY_SIZE(r8a7779_late_devices)); 8172c8788bfSSergei Shtylyov } 8182c8788bfSSergei Shtylyov 81910e8d4f6SSimon Horman #ifdef CONFIG_USE_OF 8205b3859d7SKuninori Morimoto static int r8a7779_set_wake(struct irq_data *data, unsigned int on) 8215b3859d7SKuninori Morimoto { 8225b3859d7SKuninori Morimoto return 0; /* always allow wakeup */ 8235b3859d7SKuninori Morimoto } 8245b3859d7SKuninori Morimoto 8255b3859d7SKuninori Morimoto void __init r8a7779_init_irq_dt(void) 8265b3859d7SKuninori Morimoto { 8275b3859d7SKuninori Morimoto gic_arch_extn.irq_set_wake = r8a7779_set_wake; 8285b3859d7SKuninori Morimoto 8295b3859d7SKuninori Morimoto irqchip_init(); 8305b3859d7SKuninori Morimoto 8315b3859d7SKuninori Morimoto /* route all interrupts to ARM */ 8325b3859d7SKuninori Morimoto __raw_writel(0xffffffff, INT2NTSR0); 8335b3859d7SKuninori Morimoto __raw_writel(0x3fffffff, INT2NTSR1); 8345b3859d7SKuninori Morimoto 8355b3859d7SKuninori Morimoto /* unmask all known interrupts in INTCS2 */ 8365b3859d7SKuninori Morimoto __raw_writel(0xfffffff0, INT2SMSKCR0); 8375b3859d7SKuninori Morimoto __raw_writel(0xfff7ffff, INT2SMSKCR1); 8385b3859d7SKuninori Morimoto __raw_writel(0xfffbffdf, INT2SMSKCR2); 8395b3859d7SKuninori Morimoto __raw_writel(0xbffffffc, INT2SMSKCR3); 8405b3859d7SKuninori Morimoto __raw_writel(0x003fee3f, INT2SMSKCR4); 8415b3859d7SKuninori Morimoto } 8425b3859d7SKuninori Morimoto 843916ddc35SSimon Horman void __init r8a7779_init_delay(void) 84410e8d4f6SSimon Horman { 84510e8d4f6SSimon Horman shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ 84610e8d4f6SSimon Horman } 84710e8d4f6SSimon Horman 84810e8d4f6SSimon Horman void __init r8a7779_add_standard_devices_dt(void) 84910e8d4f6SSimon Horman { 85010e8d4f6SSimon Horman /* clocks are setup late during boot in the case of DT */ 85110e8d4f6SSimon Horman r8a7779_clock_init(); 85210e8d4f6SSimon Horman 853916ddc35SSimon Horman platform_add_devices(r8a7779_devices_dt, 854916ddc35SSimon Horman ARRAY_SIZE(r8a7779_devices_dt)); 85541b0156cSMagnus Damm of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 85610e8d4f6SSimon Horman } 85710e8d4f6SSimon Horman 85810e8d4f6SSimon Horman static const char *r8a7779_compat_dt[] __initdata = { 85910e8d4f6SSimon Horman "renesas,r8a7779", 86010e8d4f6SSimon Horman NULL, 86110e8d4f6SSimon Horman }; 86210e8d4f6SSimon Horman 863abe0e14bSKuninori Morimoto DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") 86410e8d4f6SSimon Horman .map_io = r8a7779_map_io, 865916ddc35SSimon Horman .init_early = r8a7779_init_delay, 86610e8d4f6SSimon Horman .nr_irqs = NR_IRQS_LEGACY, 86710e8d4f6SSimon Horman .init_irq = r8a7779_init_irq_dt, 86810e8d4f6SSimon Horman .init_machine = r8a7779_add_standard_devices_dt, 8692c8788bfSSergei Shtylyov .init_late = r8a7779_init_late, 87010e8d4f6SSimon Horman .dt_compat = r8a7779_compat_dt, 87110e8d4f6SSimon Horman MACHINE_END 87210e8d4f6SSimon Horman #endif /* CONFIG_USE_OF */ 873