1f411fadeSMagnus Damm /* 2f411fadeSMagnus Damm * r8a7779 processor support 3f411fadeSMagnus Damm * 4dace48d0SSergei Shtylyov * Copyright (C) 2011, 2013 Renesas Solutions Corp. 5f411fadeSMagnus Damm * Copyright (C) 2011 Magnus Damm 6dace48d0SSergei Shtylyov * Copyright (C) 2013 Cogent Embedded, Inc. 7f411fadeSMagnus Damm * 8f411fadeSMagnus Damm * This program is free software; you can redistribute it and/or modify 9f411fadeSMagnus Damm * it under the terms of the GNU General Public License as published by 10f411fadeSMagnus Damm * the Free Software Foundation; version 2 of the License. 11f411fadeSMagnus Damm * 12f411fadeSMagnus Damm * This program is distributed in the hope that it will be useful, 13f411fadeSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 14f411fadeSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15f411fadeSMagnus Damm * GNU General Public License for more details. 16f411fadeSMagnus Damm * 17f411fadeSMagnus Damm * You should have received a copy of the GNU General Public License 18f411fadeSMagnus Damm * along with this program; if not, write to the Free Software 19f411fadeSMagnus Damm * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20f411fadeSMagnus Damm */ 21f411fadeSMagnus Damm #include <linux/kernel.h> 22f411fadeSMagnus Damm #include <linux/init.h> 23f411fadeSMagnus Damm #include <linux/interrupt.h> 24f411fadeSMagnus Damm #include <linux/irq.h> 255b3859d7SKuninori Morimoto #include <linux/irqchip.h> 265b3859d7SKuninori Morimoto #include <linux/irqchip/arm-gic.h> 2710e8d4f6SSimon Horman #include <linux/of_platform.h> 28441f7502SMax Filippov #include <linux/platform_data/dma-rcar-hpbdma.h> 2937a72d07SLaurent Pinchart #include <linux/platform_data/gpio-rcar.h> 305b3859d7SKuninori Morimoto #include <linux/platform_data/irq-renesas-intc-irqpin.h> 31f411fadeSMagnus Damm #include <linux/platform_device.h> 32f411fadeSMagnus Damm #include <linux/delay.h> 33f411fadeSMagnus Damm #include <linux/input.h> 34f411fadeSMagnus Damm #include <linux/io.h> 35f411fadeSMagnus Damm #include <linux/serial_sci.h> 36f411fadeSMagnus Damm #include <linux/sh_timer.h> 37a7b9837cSVladimir Barinov #include <linux/dma-mapping.h> 382c8788bfSSergei Shtylyov #include <linux/usb/otg.h> 3984a812daSSergei Shtylyov #include <linux/usb/hcd.h> 402c8788bfSSergei Shtylyov #include <linux/usb/ehci_pdriver.h> 412c8788bfSSergei Shtylyov #include <linux/usb/ohci_pdriver.h> 422c8788bfSSergei Shtylyov #include <linux/pm_runtime.h> 431b55353cSGeert Uytterhoeven 44f411fadeSMagnus Damm #include <asm/mach-types.h> 45f411fadeSMagnus Damm #include <asm/mach/arch.h> 46df27a2d8SMagnus Damm #include <asm/mach/time.h> 473e353b87SMagnus Damm #include <asm/mach/map.h> 488bac13f5SMagnus Damm #include <asm/hardware/cache-l2x0.h> 491b55353cSGeert Uytterhoeven 50fd44aa5eSMagnus Damm #include "common.h" 51b6bab126SMagnus Damm #include "irqs.h" 521b55353cSGeert Uytterhoeven #include "r8a7779.h" 533e353b87SMagnus Damm 543e353b87SMagnus Damm static struct map_desc r8a7779_io_desc[] __initdata = { 553e353b87SMagnus Damm /* 2M entity map for 0xf0000000 (MPCORE) */ 563e353b87SMagnus Damm { 573e353b87SMagnus Damm .virtual = 0xf0000000, 583e353b87SMagnus Damm .pfn = __phys_to_pfn(0xf0000000), 593e353b87SMagnus Damm .length = SZ_2M, 603e353b87SMagnus Damm .type = MT_DEVICE_NONSHARED 613e353b87SMagnus Damm }, 623e353b87SMagnus Damm /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ 633e353b87SMagnus Damm { 643e353b87SMagnus Damm .virtual = 0xfe000000, 653e353b87SMagnus Damm .pfn = __phys_to_pfn(0xfe000000), 663e353b87SMagnus Damm .length = SZ_16M, 673e353b87SMagnus Damm .type = MT_DEVICE_NONSHARED 683e353b87SMagnus Damm }, 693e353b87SMagnus Damm }; 703e353b87SMagnus Damm 713e353b87SMagnus Damm void __init r8a7779_map_io(void) 723e353b87SMagnus Damm { 737a2071c5SGeert Uytterhoeven debug_ll_io_init(); 743e353b87SMagnus Damm iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); 753e353b87SMagnus Damm } 76f411fadeSMagnus Damm 775b3859d7SKuninori Morimoto /* IRQ */ 785b3859d7SKuninori Morimoto #define INT2SMSKCR0 IOMEM(0xfe7822a0) 795b3859d7SKuninori Morimoto #define INT2SMSKCR1 IOMEM(0xfe7822a4) 805b3859d7SKuninori Morimoto #define INT2SMSKCR2 IOMEM(0xfe7822a8) 815b3859d7SKuninori Morimoto #define INT2SMSKCR3 IOMEM(0xfe7822ac) 825b3859d7SKuninori Morimoto #define INT2SMSKCR4 IOMEM(0xfe7822b0) 835b3859d7SKuninori Morimoto 845b3859d7SKuninori Morimoto #define INT2NTSR0 IOMEM(0xfe700060) 855b3859d7SKuninori Morimoto #define INT2NTSR1 IOMEM(0xfe700064) 865b3859d7SKuninori Morimoto 875b3859d7SKuninori Morimoto static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = { 885b3859d7SKuninori Morimoto .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 895b3859d7SKuninori Morimoto .sense_bitfield_width = 2, 905b3859d7SKuninori Morimoto }; 915b3859d7SKuninori Morimoto 925b3859d7SKuninori Morimoto static struct resource irqpin0_resources[] __initdata = { 935b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 945b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 955b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 965b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 975b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 985b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ 995b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ 1005b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ 1015b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ 1025b3859d7SKuninori Morimoto }; 1035b3859d7SKuninori Morimoto 10431e4e292SKuninori Morimoto void __init r8a7779_init_irq_extpin_dt(int irlm) 1055b3859d7SKuninori Morimoto { 1065b3859d7SKuninori Morimoto void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 1075b3859d7SKuninori Morimoto u32 tmp; 1085b3859d7SKuninori Morimoto 1095b3859d7SKuninori Morimoto if (!icr0) { 1105b3859d7SKuninori Morimoto pr_warn("r8a7779: unable to setup external irq pin mode\n"); 1115b3859d7SKuninori Morimoto return; 1125b3859d7SKuninori Morimoto } 1135b3859d7SKuninori Morimoto 1145b3859d7SKuninori Morimoto tmp = ioread32(icr0); 1155b3859d7SKuninori Morimoto if (irlm) 1165b3859d7SKuninori Morimoto tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 1175b3859d7SKuninori Morimoto else 1185b3859d7SKuninori Morimoto tmp &= ~(1 << 23); /* IRL mode - not supported */ 1195b3859d7SKuninori Morimoto tmp |= (1 << 21); /* LVLMODE = 1 */ 1205b3859d7SKuninori Morimoto iowrite32(tmp, icr0); 1215b3859d7SKuninori Morimoto iounmap(icr0); 12231e4e292SKuninori Morimoto } 1235b3859d7SKuninori Morimoto 12431e4e292SKuninori Morimoto void __init r8a7779_init_irq_extpin(int irlm) 12531e4e292SKuninori Morimoto { 12631e4e292SKuninori Morimoto r8a7779_init_irq_extpin_dt(irlm); 1275b3859d7SKuninori Morimoto if (irlm) 1285b3859d7SKuninori Morimoto platform_device_register_resndata( 129d2168146SPawel Moll NULL, "renesas_intc_irqpin", -1, 1305b3859d7SKuninori Morimoto irqpin0_resources, ARRAY_SIZE(irqpin0_resources), 1315b3859d7SKuninori Morimoto &irqpin0_platform_data, sizeof(irqpin0_platform_data)); 1325b3859d7SKuninori Morimoto } 1335b3859d7SKuninori Morimoto 1345b3859d7SKuninori Morimoto /* PFC/GPIO */ 1358b6edf36SLaurent Pinchart static struct resource r8a7779_pfc_resources[] = { 1360ccaf5bbSMagnus Damm DEFINE_RES_MEM(0xfffc0000, 0x023c), 1378b6edf36SLaurent Pinchart }; 1388b6edf36SLaurent Pinchart 1398b6edf36SLaurent Pinchart static struct platform_device r8a7779_pfc_device = { 1408b6edf36SLaurent Pinchart .name = "pfc-r8a7779", 1418b6edf36SLaurent Pinchart .id = -1, 1428b6edf36SLaurent Pinchart .resource = r8a7779_pfc_resources, 1438b6edf36SLaurent Pinchart .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), 1448b6edf36SLaurent Pinchart }; 1458b6edf36SLaurent Pinchart 14637a72d07SLaurent Pinchart #define R8A7779_GPIO(idx, npins) \ 14737a72d07SLaurent Pinchart static struct resource r8a7779_gpio##idx##_resources[] = { \ 1480ccaf5bbSMagnus Damm DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \ 1490ccaf5bbSMagnus Damm DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \ 15037a72d07SLaurent Pinchart }; \ 15137a72d07SLaurent Pinchart \ 15237a72d07SLaurent Pinchart static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ 15337a72d07SLaurent Pinchart .gpio_base = 32 * (idx), \ 15437a72d07SLaurent Pinchart .irq_base = 0, \ 15537a72d07SLaurent Pinchart .number_of_pins = npins, \ 15637a72d07SLaurent Pinchart .pctl_name = "pfc-r8a7779", \ 15737a72d07SLaurent Pinchart }; \ 15837a72d07SLaurent Pinchart \ 15937a72d07SLaurent Pinchart static struct platform_device r8a7779_gpio##idx##_device = { \ 16037a72d07SLaurent Pinchart .name = "gpio_rcar", \ 16137a72d07SLaurent Pinchart .id = idx, \ 16237a72d07SLaurent Pinchart .resource = r8a7779_gpio##idx##_resources, \ 16337a72d07SLaurent Pinchart .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \ 16437a72d07SLaurent Pinchart .dev = { \ 16537a72d07SLaurent Pinchart .platform_data = &r8a7779_gpio##idx##_platform_data, \ 16637a72d07SLaurent Pinchart }, \ 16737a72d07SLaurent Pinchart } 16837a72d07SLaurent Pinchart 16937a72d07SLaurent Pinchart R8A7779_GPIO(0, 32); 17037a72d07SLaurent Pinchart R8A7779_GPIO(1, 32); 17137a72d07SLaurent Pinchart R8A7779_GPIO(2, 32); 17237a72d07SLaurent Pinchart R8A7779_GPIO(3, 32); 17337a72d07SLaurent Pinchart R8A7779_GPIO(4, 32); 17437a72d07SLaurent Pinchart R8A7779_GPIO(5, 32); 17537a72d07SLaurent Pinchart R8A7779_GPIO(6, 9); 17637a72d07SLaurent Pinchart 17737a72d07SLaurent Pinchart static struct platform_device *r8a7779_pinctrl_devices[] __initdata = { 17837a72d07SLaurent Pinchart &r8a7779_pfc_device, 17937a72d07SLaurent Pinchart &r8a7779_gpio0_device, 18037a72d07SLaurent Pinchart &r8a7779_gpio1_device, 18137a72d07SLaurent Pinchart &r8a7779_gpio2_device, 18237a72d07SLaurent Pinchart &r8a7779_gpio3_device, 18337a72d07SLaurent Pinchart &r8a7779_gpio4_device, 18437a72d07SLaurent Pinchart &r8a7779_gpio5_device, 18537a72d07SLaurent Pinchart &r8a7779_gpio6_device, 18637a72d07SLaurent Pinchart }; 18737a72d07SLaurent Pinchart 1888b6edf36SLaurent Pinchart void __init r8a7779_pinmux_init(void) 1898b6edf36SLaurent Pinchart { 19037a72d07SLaurent Pinchart platform_add_devices(r8a7779_pinctrl_devices, 19137a72d07SLaurent Pinchart ARRAY_SIZE(r8a7779_pinctrl_devices)); 1928b6edf36SLaurent Pinchart } 1938b6edf36SLaurent Pinchart 194efced000SLaurent Pinchart /* SCIF */ 195efced000SLaurent Pinchart #define R8A7779_SCIF(index, baseaddr, irq) \ 196efced000SLaurent Pinchart static struct plat_sci_port scif##index##_platform_data = { \ 197efced000SLaurent Pinchart .type = PORT_SCIF, \ 198efced000SLaurent Pinchart .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 199efced000SLaurent Pinchart .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 200efced000SLaurent Pinchart }; \ 201efced000SLaurent Pinchart \ 202aa61ee2eSLaurent Pinchart static struct resource scif##index##_resources[] = { \ 203aa61ee2eSLaurent Pinchart DEFINE_RES_MEM(baseaddr, 0x100), \ 204aa61ee2eSLaurent Pinchart DEFINE_RES_IRQ(irq), \ 205aa61ee2eSLaurent Pinchart }; \ 206aa61ee2eSLaurent Pinchart \ 207efced000SLaurent Pinchart static struct platform_device scif##index##_device = { \ 208efced000SLaurent Pinchart .name = "sh-sci", \ 209efced000SLaurent Pinchart .id = index, \ 210aa61ee2eSLaurent Pinchart .resource = scif##index##_resources, \ 211aa61ee2eSLaurent Pinchart .num_resources = ARRAY_SIZE(scif##index##_resources), \ 212efced000SLaurent Pinchart .dev = { \ 213efced000SLaurent Pinchart .platform_data = &scif##index##_platform_data, \ 214efced000SLaurent Pinchart }, \ 215efced000SLaurent Pinchart } 216f411fadeSMagnus Damm 217efced000SLaurent Pinchart R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78)); 218efced000SLaurent Pinchart R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79)); 219efced000SLaurent Pinchart R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a)); 220efced000SLaurent Pinchart R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b)); 221efced000SLaurent Pinchart R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c)); 222efced000SLaurent Pinchart R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d)); 223f411fadeSMagnus Damm 224f411fadeSMagnus Damm /* TMU */ 225e4ae34e2SLaurent Pinchart static struct sh_timer_config tmu0_platform_data = { 226e4ae34e2SLaurent Pinchart .channels_mask = 7, 227f411fadeSMagnus Damm }; 228f411fadeSMagnus Damm 229e4ae34e2SLaurent Pinchart static struct resource tmu0_resources[] = { 230e4ae34e2SLaurent Pinchart DEFINE_RES_MEM(0xffd80000, 0x30), 231e4ae34e2SLaurent Pinchart DEFINE_RES_IRQ(gic_iid(0x40)), 232e4ae34e2SLaurent Pinchart DEFINE_RES_IRQ(gic_iid(0x41)), 233e4ae34e2SLaurent Pinchart DEFINE_RES_IRQ(gic_iid(0x42)), 234f411fadeSMagnus Damm }; 235f411fadeSMagnus Damm 236e4ae34e2SLaurent Pinchart static struct platform_device tmu0_device = { 237e4ae34e2SLaurent Pinchart .name = "sh-tmu", 238f411fadeSMagnus Damm .id = 0, 239f411fadeSMagnus Damm .dev = { 240e4ae34e2SLaurent Pinchart .platform_data = &tmu0_platform_data, 241f411fadeSMagnus Damm }, 242e4ae34e2SLaurent Pinchart .resource = tmu0_resources, 243e4ae34e2SLaurent Pinchart .num_resources = ARRAY_SIZE(tmu0_resources), 244f411fadeSMagnus Damm }; 245f411fadeSMagnus Damm 246ccc2a27bSKuninori Morimoto /* I2C */ 247ccc2a27bSKuninori Morimoto static struct resource rcar_i2c0_res[] = { 248ccc2a27bSKuninori Morimoto { 249ccc2a27bSKuninori Morimoto .start = 0xffc70000, 250ccc2a27bSKuninori Morimoto .end = 0xffc70fff, 251ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 252ccc2a27bSKuninori Morimoto }, { 253dbe95ad0SKuninori Morimoto .start = gic_iid(0x6f), 254ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 255ccc2a27bSKuninori Morimoto }, 256ccc2a27bSKuninori Morimoto }; 257ccc2a27bSKuninori Morimoto 258ccc2a27bSKuninori Morimoto static struct platform_device i2c0_device = { 259ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 260ccc2a27bSKuninori Morimoto .id = 0, 261ccc2a27bSKuninori Morimoto .resource = rcar_i2c0_res, 262ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c0_res), 263ccc2a27bSKuninori Morimoto }; 264ccc2a27bSKuninori Morimoto 265ccc2a27bSKuninori Morimoto static struct resource rcar_i2c1_res[] = { 266ccc2a27bSKuninori Morimoto { 267ccc2a27bSKuninori Morimoto .start = 0xffc71000, 268ccc2a27bSKuninori Morimoto .end = 0xffc71fff, 269ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 270ccc2a27bSKuninori Morimoto }, { 271dbe95ad0SKuninori Morimoto .start = gic_iid(0x72), 272ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 273ccc2a27bSKuninori Morimoto }, 274ccc2a27bSKuninori Morimoto }; 275ccc2a27bSKuninori Morimoto 276ccc2a27bSKuninori Morimoto static struct platform_device i2c1_device = { 277ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 278ccc2a27bSKuninori Morimoto .id = 1, 279ccc2a27bSKuninori Morimoto .resource = rcar_i2c1_res, 280ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c1_res), 281ccc2a27bSKuninori Morimoto }; 282ccc2a27bSKuninori Morimoto 283ccc2a27bSKuninori Morimoto static struct resource rcar_i2c2_res[] = { 284ccc2a27bSKuninori Morimoto { 285ccc2a27bSKuninori Morimoto .start = 0xffc72000, 286ccc2a27bSKuninori Morimoto .end = 0xffc72fff, 287ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 288ccc2a27bSKuninori Morimoto }, { 289dbe95ad0SKuninori Morimoto .start = gic_iid(0x70), 290ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 291ccc2a27bSKuninori Morimoto }, 292ccc2a27bSKuninori Morimoto }; 293ccc2a27bSKuninori Morimoto 294ccc2a27bSKuninori Morimoto static struct platform_device i2c2_device = { 295ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 296ccc2a27bSKuninori Morimoto .id = 2, 297ccc2a27bSKuninori Morimoto .resource = rcar_i2c2_res, 298ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c2_res), 299ccc2a27bSKuninori Morimoto }; 300ccc2a27bSKuninori Morimoto 301ccc2a27bSKuninori Morimoto static struct resource rcar_i2c3_res[] = { 302ccc2a27bSKuninori Morimoto { 303ccc2a27bSKuninori Morimoto .start = 0xffc73000, 304ccc2a27bSKuninori Morimoto .end = 0xffc73fff, 305ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 306ccc2a27bSKuninori Morimoto }, { 307dbe95ad0SKuninori Morimoto .start = gic_iid(0x71), 308ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 309ccc2a27bSKuninori Morimoto }, 310ccc2a27bSKuninori Morimoto }; 311ccc2a27bSKuninori Morimoto 312ccc2a27bSKuninori Morimoto static struct platform_device i2c3_device = { 313ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 314ccc2a27bSKuninori Morimoto .id = 3, 315ccc2a27bSKuninori Morimoto .resource = rcar_i2c3_res, 316ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c3_res), 317ccc2a27bSKuninori Morimoto }; 318ccc2a27bSKuninori Morimoto 319a7b9837cSVladimir Barinov static struct resource sata_resources[] = { 320a7b9837cSVladimir Barinov [0] = { 321a7b9837cSVladimir Barinov .name = "rcar-sata", 322a7b9837cSVladimir Barinov .start = 0xfc600000, 323a7b9837cSVladimir Barinov .end = 0xfc601fff, 324a7b9837cSVladimir Barinov .flags = IORESOURCE_MEM, 325a7b9837cSVladimir Barinov }, 326a7b9837cSVladimir Barinov [1] = { 327d60cd5f1SSergei Shtylyov .start = gic_iid(0x84), 328a7b9837cSVladimir Barinov .flags = IORESOURCE_IRQ, 329a7b9837cSVladimir Barinov }, 330a7b9837cSVladimir Barinov }; 331a7b9837cSVladimir Barinov 332a7b9837cSVladimir Barinov static struct platform_device sata_device = { 333a7b9837cSVladimir Barinov .name = "sata_rcar", 334a7b9837cSVladimir Barinov .id = -1, 335a7b9837cSVladimir Barinov .resource = sata_resources, 336a7b9837cSVladimir Barinov .num_resources = ARRAY_SIZE(sata_resources), 337a7b9837cSVladimir Barinov .dev = { 338a7b9837cSVladimir Barinov .dma_mask = &sata_device.dev.coherent_dma_mask, 339a7b9837cSVladimir Barinov .coherent_dma_mask = DMA_BIT_MASK(32), 340a7b9837cSVladimir Barinov }, 341a7b9837cSVladimir Barinov }; 342a7b9837cSVladimir Barinov 3432c8788bfSSergei Shtylyov /* USB */ 3442c8788bfSSergei Shtylyov static struct usb_phy *phy; 3452c8788bfSSergei Shtylyov 3462c8788bfSSergei Shtylyov static int usb_power_on(struct platform_device *pdev) 3472c8788bfSSergei Shtylyov { 3482c8788bfSSergei Shtylyov if (IS_ERR(phy)) 3492c8788bfSSergei Shtylyov return PTR_ERR(phy); 3502c8788bfSSergei Shtylyov 3512c8788bfSSergei Shtylyov pm_runtime_enable(&pdev->dev); 3522c8788bfSSergei Shtylyov pm_runtime_get_sync(&pdev->dev); 3532c8788bfSSergei Shtylyov 3542c8788bfSSergei Shtylyov usb_phy_init(phy); 3552c8788bfSSergei Shtylyov 3562c8788bfSSergei Shtylyov return 0; 3572c8788bfSSergei Shtylyov } 3582c8788bfSSergei Shtylyov 3592c8788bfSSergei Shtylyov static void usb_power_off(struct platform_device *pdev) 3602c8788bfSSergei Shtylyov { 3612c8788bfSSergei Shtylyov if (IS_ERR(phy)) 3622c8788bfSSergei Shtylyov return; 3632c8788bfSSergei Shtylyov 3642c8788bfSSergei Shtylyov usb_phy_shutdown(phy); 3652c8788bfSSergei Shtylyov 3662c8788bfSSergei Shtylyov pm_runtime_put_sync(&pdev->dev); 3672c8788bfSSergei Shtylyov pm_runtime_disable(&pdev->dev); 3682c8788bfSSergei Shtylyov } 3692c8788bfSSergei Shtylyov 37084a812daSSergei Shtylyov static int ehci_init_internal_buffer(struct usb_hcd *hcd) 37184a812daSSergei Shtylyov { 37284a812daSSergei Shtylyov /* 37384a812daSSergei Shtylyov * Below are recommended values from the datasheet; 37484a812daSSergei Shtylyov * see [USB :: Setting of EHCI Internal Buffer]. 37584a812daSSergei Shtylyov */ 37684a812daSSergei Shtylyov /* EHCI IP internal buffer setting */ 37784a812daSSergei Shtylyov iowrite32(0x00ff0040, hcd->regs + 0x0094); 37884a812daSSergei Shtylyov /* EHCI IP internal buffer enable */ 37984a812daSSergei Shtylyov iowrite32(0x00000001, hcd->regs + 0x009C); 38084a812daSSergei Shtylyov 38184a812daSSergei Shtylyov return 0; 38284a812daSSergei Shtylyov } 38384a812daSSergei Shtylyov 3842c8788bfSSergei Shtylyov static struct usb_ehci_pdata ehcix_pdata = { 3852c8788bfSSergei Shtylyov .power_on = usb_power_on, 3862c8788bfSSergei Shtylyov .power_off = usb_power_off, 3872c8788bfSSergei Shtylyov .power_suspend = usb_power_off, 38884a812daSSergei Shtylyov .pre_setup = ehci_init_internal_buffer, 3892c8788bfSSergei Shtylyov }; 3902c8788bfSSergei Shtylyov 3912c8788bfSSergei Shtylyov static struct resource ehci0_resources[] = { 3922c8788bfSSergei Shtylyov [0] = { 3932c8788bfSSergei Shtylyov .start = 0xffe70000, 3942c8788bfSSergei Shtylyov .end = 0xffe70400 - 1, 3952c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 3962c8788bfSSergei Shtylyov }, 3972c8788bfSSergei Shtylyov [1] = { 3982c8788bfSSergei Shtylyov .start = gic_iid(0x4c), 3992c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 4002c8788bfSSergei Shtylyov }, 4012c8788bfSSergei Shtylyov }; 4022c8788bfSSergei Shtylyov 4032c8788bfSSergei Shtylyov static struct platform_device ehci0_device = { 4042c8788bfSSergei Shtylyov .name = "ehci-platform", 4052c8788bfSSergei Shtylyov .id = 0, 4062c8788bfSSergei Shtylyov .dev = { 4072c8788bfSSergei Shtylyov .dma_mask = &ehci0_device.dev.coherent_dma_mask, 4082c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 4092c8788bfSSergei Shtylyov .platform_data = &ehcix_pdata, 4102c8788bfSSergei Shtylyov }, 4112c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ehci0_resources), 4122c8788bfSSergei Shtylyov .resource = ehci0_resources, 4132c8788bfSSergei Shtylyov }; 4142c8788bfSSergei Shtylyov 4152c8788bfSSergei Shtylyov static struct resource ehci1_resources[] = { 4162c8788bfSSergei Shtylyov [0] = { 4172c8788bfSSergei Shtylyov .start = 0xfff70000, 4182c8788bfSSergei Shtylyov .end = 0xfff70400 - 1, 4192c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 4202c8788bfSSergei Shtylyov }, 4212c8788bfSSergei Shtylyov [1] = { 4222c8788bfSSergei Shtylyov .start = gic_iid(0x4d), 4232c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 4242c8788bfSSergei Shtylyov }, 4252c8788bfSSergei Shtylyov }; 4262c8788bfSSergei Shtylyov 4272c8788bfSSergei Shtylyov static struct platform_device ehci1_device = { 4282c8788bfSSergei Shtylyov .name = "ehci-platform", 4292c8788bfSSergei Shtylyov .id = 1, 4302c8788bfSSergei Shtylyov .dev = { 4312c8788bfSSergei Shtylyov .dma_mask = &ehci1_device.dev.coherent_dma_mask, 4322c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 4332c8788bfSSergei Shtylyov .platform_data = &ehcix_pdata, 4342c8788bfSSergei Shtylyov }, 4352c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ehci1_resources), 4362c8788bfSSergei Shtylyov .resource = ehci1_resources, 4372c8788bfSSergei Shtylyov }; 4382c8788bfSSergei Shtylyov 4392c8788bfSSergei Shtylyov static struct usb_ohci_pdata ohcix_pdata = { 4402c8788bfSSergei Shtylyov .power_on = usb_power_on, 4412c8788bfSSergei Shtylyov .power_off = usb_power_off, 4422c8788bfSSergei Shtylyov .power_suspend = usb_power_off, 4432c8788bfSSergei Shtylyov }; 4442c8788bfSSergei Shtylyov 4452c8788bfSSergei Shtylyov static struct resource ohci0_resources[] = { 4462c8788bfSSergei Shtylyov [0] = { 4472c8788bfSSergei Shtylyov .start = 0xffe70400, 4482c8788bfSSergei Shtylyov .end = 0xffe70800 - 1, 4492c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 4502c8788bfSSergei Shtylyov }, 4512c8788bfSSergei Shtylyov [1] = { 4522c8788bfSSergei Shtylyov .start = gic_iid(0x4c), 4532c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 4542c8788bfSSergei Shtylyov }, 4552c8788bfSSergei Shtylyov }; 4562c8788bfSSergei Shtylyov 4572c8788bfSSergei Shtylyov static struct platform_device ohci0_device = { 4582c8788bfSSergei Shtylyov .name = "ohci-platform", 4592c8788bfSSergei Shtylyov .id = 0, 4602c8788bfSSergei Shtylyov .dev = { 4612c8788bfSSergei Shtylyov .dma_mask = &ohci0_device.dev.coherent_dma_mask, 4622c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 4632c8788bfSSergei Shtylyov .platform_data = &ohcix_pdata, 4642c8788bfSSergei Shtylyov }, 4652c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ohci0_resources), 4662c8788bfSSergei Shtylyov .resource = ohci0_resources, 4672c8788bfSSergei Shtylyov }; 4682c8788bfSSergei Shtylyov 4692c8788bfSSergei Shtylyov static struct resource ohci1_resources[] = { 4702c8788bfSSergei Shtylyov [0] = { 4712c8788bfSSergei Shtylyov .start = 0xfff70400, 4722c8788bfSSergei Shtylyov .end = 0xfff70800 - 1, 4732c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 4742c8788bfSSergei Shtylyov }, 4752c8788bfSSergei Shtylyov [1] = { 4762c8788bfSSergei Shtylyov .start = gic_iid(0x4d), 4772c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 4782c8788bfSSergei Shtylyov }, 4792c8788bfSSergei Shtylyov }; 4802c8788bfSSergei Shtylyov 4812c8788bfSSergei Shtylyov static struct platform_device ohci1_device = { 4822c8788bfSSergei Shtylyov .name = "ohci-platform", 4832c8788bfSSergei Shtylyov .id = 1, 4842c8788bfSSergei Shtylyov .dev = { 4852c8788bfSSergei Shtylyov .dma_mask = &ohci1_device.dev.coherent_dma_mask, 4862c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 4872c8788bfSSergei Shtylyov .platform_data = &ohcix_pdata, 4882c8788bfSSergei Shtylyov }, 4892c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ohci1_resources), 4902c8788bfSSergei Shtylyov .resource = ohci1_resources, 4912c8788bfSSergei Shtylyov }; 4922c8788bfSSergei Shtylyov 493441f7502SMax Filippov /* HPB-DMA */ 494441f7502SMax Filippov 495441f7502SMax Filippov /* Asynchronous mode register bits */ 496441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */ 497441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */ 498441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */ 499441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */ 500441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */ 501441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */ 502441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */ 503441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */ 504441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */ 505441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */ 506441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */ 507441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */ 508441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */ 509441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */ 510441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */ 511441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */ 512441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */ 513441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */ 514441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */ 515441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */ 516441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */ 517441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */ 518441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */ 519441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */ 520441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */ 521441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */ 522441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */ 523441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */ 524441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */ 525441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */ 526441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */ 527441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */ 528441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */ 529441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */ 530441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */ 531441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */ 532441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */ 533441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */ 534441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */ 535441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */ 536441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */ 537441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */ 538441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */ 539441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */ 540441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */ 541441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */ 542441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */ 543441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */ 544441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */ 545441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */ 546441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */ 547441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */ 548441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */ 549441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */ 550441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */ 551441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */ 552441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ 553441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */ 554441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */ 555441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */ 556441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */ 557441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */ 558441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 559441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */ 560441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */ 561441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */ 562441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */ 563441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */ 564441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */ 565441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */ 566441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */ 567441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */ 568441f7502SMax Filippov 569441f7502SMax Filippov static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 570441f7502SMax Filippov { 571441f7502SMax Filippov .id = HPBDMA_SLAVE_SDHI0_TX, 572441f7502SMax Filippov .addr = 0xffe4c000 + 0x30, 573441f7502SMax Filippov .dcr = HPB_DMAE_DCR_SPDS_16BIT | 574441f7502SMax Filippov HPB_DMAE_DCR_DMDL | 575441f7502SMax Filippov HPB_DMAE_DCR_DPDS_16BIT, 576441f7502SMax Filippov .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 577441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST22 | 578441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST23, 579441f7502SMax Filippov .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE | 580441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST, 581441f7502SMax Filippov .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK | 582441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD21_MASK, 583441f7502SMax Filippov .port = 0x0D0C, 584441f7502SMax Filippov .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 585441f7502SMax Filippov .dma_ch = 21, 586441f7502SMax Filippov }, { 587441f7502SMax Filippov .id = HPBDMA_SLAVE_SDHI0_RX, 588441f7502SMax Filippov .addr = 0xffe4c000 + 0x30, 589441f7502SMax Filippov .dcr = HPB_DMAE_DCR_SMDL | 590441f7502SMax Filippov HPB_DMAE_DCR_SPDS_16BIT | 591441f7502SMax Filippov HPB_DMAE_DCR_DPDS_16BIT, 592441f7502SMax Filippov .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 593441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST22 | 594441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST23, 595441f7502SMax Filippov .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE | 596441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST, 597441f7502SMax Filippov .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK | 598441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD22_MASK, 599441f7502SMax Filippov .port = 0x0D0C, 600441f7502SMax Filippov .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 601441f7502SMax Filippov .dma_ch = 22, 602441f7502SMax Filippov }, 603441f7502SMax Filippov }; 604441f7502SMax Filippov 605441f7502SMax Filippov static const struct hpb_dmae_channel hpb_dmae_channels[] = { 606441f7502SMax Filippov HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 607441f7502SMax Filippov HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 608441f7502SMax Filippov }; 609441f7502SMax Filippov 610441f7502SMax Filippov static struct hpb_dmae_pdata dma_platform_data __initdata = { 611441f7502SMax Filippov .slaves = hpb_dmae_slaves, 612441f7502SMax Filippov .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), 613441f7502SMax Filippov .channels = hpb_dmae_channels, 614441f7502SMax Filippov .num_channels = ARRAY_SIZE(hpb_dmae_channels), 615441f7502SMax Filippov .ts_shift = { 616441f7502SMax Filippov [XMIT_SZ_8BIT] = 0, 617441f7502SMax Filippov [XMIT_SZ_16BIT] = 1, 618441f7502SMax Filippov [XMIT_SZ_32BIT] = 2, 619441f7502SMax Filippov }, 620441f7502SMax Filippov .num_hw_channels = 44, 621441f7502SMax Filippov }; 622441f7502SMax Filippov 623441f7502SMax Filippov static struct resource hpb_dmae_resources[] __initdata = { 624441f7502SMax Filippov /* Channel registers */ 625441f7502SMax Filippov DEFINE_RES_MEM(0xffc08000, 0x1000), 626441f7502SMax Filippov /* Common registers */ 627441f7502SMax Filippov DEFINE_RES_MEM(0xffc09000, 0x170), 628441f7502SMax Filippov /* Asynchronous reset registers */ 629441f7502SMax Filippov DEFINE_RES_MEM(0xffc00300, 4), 630441f7502SMax Filippov /* Asynchronous mode registers */ 631441f7502SMax Filippov DEFINE_RES_MEM(0xffc00400, 4), 632441f7502SMax Filippov /* IRQ for DMA channels */ 633441f7502SMax Filippov DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ), 634441f7502SMax Filippov }; 635441f7502SMax Filippov 636441f7502SMax Filippov static void __init r8a7779_register_hpb_dmae(void) 637441f7502SMax Filippov { 638d2168146SPawel Moll platform_device_register_resndata(NULL, "hpb-dma-engine", 639d2168146SPawel Moll -1, hpb_dmae_resources, 640441f7502SMax Filippov ARRAY_SIZE(hpb_dmae_resources), 641441f7502SMax Filippov &dma_platform_data, 642441f7502SMax Filippov sizeof(dma_platform_data)); 643441f7502SMax Filippov } 644441f7502SMax Filippov 6455ecd7a51SLaurent Pinchart static struct platform_device *r8a7779_early_devices[] __initdata = { 6466d4abd79SSimon Horman &tmu0_device, 6476d4abd79SSimon Horman }; 6486d4abd79SSimon Horman 6496d4abd79SSimon Horman static struct platform_device *r8a7779_standard_devices[] __initdata = { 650f411fadeSMagnus Damm &scif0_device, 651f411fadeSMagnus Damm &scif1_device, 652f411fadeSMagnus Damm &scif2_device, 653f411fadeSMagnus Damm &scif3_device, 654f411fadeSMagnus Damm &scif4_device, 655f411fadeSMagnus Damm &scif5_device, 656ccc2a27bSKuninori Morimoto &i2c0_device, 657ccc2a27bSKuninori Morimoto &i2c1_device, 658ccc2a27bSKuninori Morimoto &i2c2_device, 659ccc2a27bSKuninori Morimoto &i2c3_device, 660a7b9837cSVladimir Barinov &sata_device, 661f411fadeSMagnus Damm }; 662f411fadeSMagnus Damm 663f411fadeSMagnus Damm void __init r8a7779_add_standard_devices(void) 664f411fadeSMagnus Damm { 6658bac13f5SMagnus Damm #ifdef CONFIG_CACHE_L2X0 66636bccb11SRussell King /* Shared attribute override enable, 64K*16way */ 6672edb89cdSRussell King l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); 6688bac13f5SMagnus Damm #endif 669a662c082SMagnus Damm r8a7779_pm_init(); 670a662c082SMagnus Damm 67145e5ca57SRafael J. Wysocki r8a7779_init_pm_domains(); 672a662c082SMagnus Damm 6735ecd7a51SLaurent Pinchart platform_add_devices(r8a7779_early_devices, 6745ecd7a51SLaurent Pinchart ARRAY_SIZE(r8a7779_early_devices)); 6752c8788bfSSergei Shtylyov platform_add_devices(r8a7779_standard_devices, 6762c8788bfSSergei Shtylyov ARRAY_SIZE(r8a7779_standard_devices)); 677441f7502SMax Filippov r8a7779_register_hpb_dmae(); 678f411fadeSMagnus Damm } 679f411fadeSMagnus Damm 680f411fadeSMagnus Damm void __init r8a7779_add_early_devices(void) 681f411fadeSMagnus Damm { 6825ecd7a51SLaurent Pinchart early_platform_add_devices(r8a7779_early_devices, 6835ecd7a51SLaurent Pinchart ARRAY_SIZE(r8a7779_early_devices)); 6843e353b87SMagnus Damm 6853e353b87SMagnus Damm /* Early serial console setup is not included here due to 6863e353b87SMagnus Damm * memory map collisions. The SCIF serial ports in r8a7779 6873e353b87SMagnus Damm * are difficult to entity map 1:1 due to collision with the 6883e353b87SMagnus Damm * virtual memory range used by the coherent DMA code on ARM. 6893e353b87SMagnus Damm * 6903e353b87SMagnus Damm * Anyone wanting to debug early can remove UPF_IOREMAP from 6913e353b87SMagnus Damm * the sh-sci serial console platform data, adjust mapbase 6923e353b87SMagnus Damm * to a static M:N virt:phys mapping that needs to be added to 6933e353b87SMagnus Damm * the mappings passed with iotable_init() above. 6943e353b87SMagnus Damm * 6953e353b87SMagnus Damm * Then add a call to shmobile_setup_console() from this function. 6963e353b87SMagnus Damm * 6973e353b87SMagnus Damm * As a final step pass earlyprint=sh-sci.2,115200 on the kernel 6983e353b87SMagnus Damm * command line in case of the marzen board. 6993e353b87SMagnus Damm */ 700f411fadeSMagnus Damm } 70110e8d4f6SSimon Horman 7022c8788bfSSergei Shtylyov static struct platform_device *r8a7779_late_devices[] __initdata = { 7032c8788bfSSergei Shtylyov &ehci0_device, 7042c8788bfSSergei Shtylyov &ehci1_device, 7052c8788bfSSergei Shtylyov &ohci0_device, 7062c8788bfSSergei Shtylyov &ohci1_device, 7072c8788bfSSergei Shtylyov }; 7082c8788bfSSergei Shtylyov 7092c8788bfSSergei Shtylyov void __init r8a7779_init_late(void) 7102c8788bfSSergei Shtylyov { 7112c8788bfSSergei Shtylyov /* get USB PHY */ 7122c8788bfSSergei Shtylyov phy = usb_get_phy(USB_PHY_TYPE_USB2); 7132c8788bfSSergei Shtylyov 7142c8788bfSSergei Shtylyov shmobile_init_late(); 7152c8788bfSSergei Shtylyov platform_add_devices(r8a7779_late_devices, 7162c8788bfSSergei Shtylyov ARRAY_SIZE(r8a7779_late_devices)); 7172c8788bfSSergei Shtylyov } 7182c8788bfSSergei Shtylyov 71910e8d4f6SSimon Horman #ifdef CONFIG_USE_OF 7205b3859d7SKuninori Morimoto static int r8a7779_set_wake(struct irq_data *data, unsigned int on) 7215b3859d7SKuninori Morimoto { 7225b3859d7SKuninori Morimoto return 0; /* always allow wakeup */ 7235b3859d7SKuninori Morimoto } 7245b3859d7SKuninori Morimoto 7255b3859d7SKuninori Morimoto void __init r8a7779_init_irq_dt(void) 7265b3859d7SKuninori Morimoto { 7275b3859d7SKuninori Morimoto gic_arch_extn.irq_set_wake = r8a7779_set_wake; 7285b3859d7SKuninori Morimoto 7295b3859d7SKuninori Morimoto irqchip_init(); 7305b3859d7SKuninori Morimoto 7315b3859d7SKuninori Morimoto /* route all interrupts to ARM */ 7325b3859d7SKuninori Morimoto __raw_writel(0xffffffff, INT2NTSR0); 7335b3859d7SKuninori Morimoto __raw_writel(0x3fffffff, INT2NTSR1); 7345b3859d7SKuninori Morimoto 7355b3859d7SKuninori Morimoto /* unmask all known interrupts in INTCS2 */ 7365b3859d7SKuninori Morimoto __raw_writel(0xfffffff0, INT2SMSKCR0); 7375b3859d7SKuninori Morimoto __raw_writel(0xfff7ffff, INT2SMSKCR1); 7385b3859d7SKuninori Morimoto __raw_writel(0xfffbffdf, INT2SMSKCR2); 7395b3859d7SKuninori Morimoto __raw_writel(0xbffffffc, INT2SMSKCR3); 7405b3859d7SKuninori Morimoto __raw_writel(0x003fee3f, INT2SMSKCR4); 7415b3859d7SKuninori Morimoto } 7425b3859d7SKuninori Morimoto 7433e05f24aSSimon Horman #define MODEMR 0xffcc0020 7443e05f24aSSimon Horman 7453e05f24aSSimon Horman u32 __init r8a7779_read_mode_pins(void) 7463e05f24aSSimon Horman { 7473e05f24aSSimon Horman static u32 mode; 7483e05f24aSSimon Horman static bool mode_valid; 7493e05f24aSSimon Horman 7503e05f24aSSimon Horman if (!mode_valid) { 7513e05f24aSSimon Horman void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); 7523e05f24aSSimon Horman BUG_ON(!modemr); 7533e05f24aSSimon Horman mode = ioread32(modemr); 7543e05f24aSSimon Horman iounmap(modemr); 7553e05f24aSSimon Horman mode_valid = true; 7563e05f24aSSimon Horman } 7573e05f24aSSimon Horman 7583e05f24aSSimon Horman return mode; 75910e8d4f6SSimon Horman } 76010e8d4f6SSimon Horman 76110e8d4f6SSimon Horman static const char *r8a7779_compat_dt[] __initdata = { 76210e8d4f6SSimon Horman "renesas,r8a7779", 76310e8d4f6SSimon Horman NULL, 76410e8d4f6SSimon Horman }; 76510e8d4f6SSimon Horman 766abe0e14bSKuninori Morimoto DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") 76710e8d4f6SSimon Horman .map_io = r8a7779_map_io, 7680157b626SSimon Horman .init_early = shmobile_init_delay, 76910e8d4f6SSimon Horman .init_irq = r8a7779_init_irq_dt, 770d5b00b90SMagnus Damm .init_late = shmobile_init_late, 77110e8d4f6SSimon Horman .dt_compat = r8a7779_compat_dt, 77210e8d4f6SSimon Horman MACHINE_END 77310e8d4f6SSimon Horman #endif /* CONFIG_USE_OF */ 774