1f411fadeSMagnus Damm /* 2f411fadeSMagnus Damm * r8a7779 processor support 3f411fadeSMagnus Damm * 4dace48d0SSergei Shtylyov * Copyright (C) 2011, 2013 Renesas Solutions Corp. 5f411fadeSMagnus Damm * Copyright (C) 2011 Magnus Damm 6dace48d0SSergei Shtylyov * Copyright (C) 2013 Cogent Embedded, Inc. 7f411fadeSMagnus Damm * 8f411fadeSMagnus Damm * This program is free software; you can redistribute it and/or modify 9f411fadeSMagnus Damm * it under the terms of the GNU General Public License as published by 10f411fadeSMagnus Damm * the Free Software Foundation; version 2 of the License. 11f411fadeSMagnus Damm * 12f411fadeSMagnus Damm * This program is distributed in the hope that it will be useful, 13f411fadeSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 14f411fadeSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15f411fadeSMagnus Damm * GNU General Public License for more details. 16f411fadeSMagnus Damm * 17f411fadeSMagnus Damm * You should have received a copy of the GNU General Public License 18f411fadeSMagnus Damm * along with this program; if not, write to the Free Software 19f411fadeSMagnus Damm * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20f411fadeSMagnus Damm */ 21f411fadeSMagnus Damm #include <linux/kernel.h> 22f411fadeSMagnus Damm #include <linux/init.h> 23f411fadeSMagnus Damm #include <linux/interrupt.h> 24f411fadeSMagnus Damm #include <linux/irq.h> 255b3859d7SKuninori Morimoto #include <linux/irqchip.h> 265b3859d7SKuninori Morimoto #include <linux/irqchip/arm-gic.h> 2710e8d4f6SSimon Horman #include <linux/of_platform.h> 28441f7502SMax Filippov #include <linux/platform_data/dma-rcar-hpbdma.h> 2937a72d07SLaurent Pinchart #include <linux/platform_data/gpio-rcar.h> 305b3859d7SKuninori Morimoto #include <linux/platform_data/irq-renesas-intc-irqpin.h> 31f411fadeSMagnus Damm #include <linux/platform_device.h> 32f411fadeSMagnus Damm #include <linux/delay.h> 33f411fadeSMagnus Damm #include <linux/input.h> 34f411fadeSMagnus Damm #include <linux/io.h> 35f411fadeSMagnus Damm #include <linux/serial_sci.h> 36f411fadeSMagnus Damm #include <linux/sh_timer.h> 37a7b9837cSVladimir Barinov #include <linux/dma-mapping.h> 382c8788bfSSergei Shtylyov #include <linux/usb/otg.h> 3984a812daSSergei Shtylyov #include <linux/usb/hcd.h> 402c8788bfSSergei Shtylyov #include <linux/usb/ehci_pdriver.h> 412c8788bfSSergei Shtylyov #include <linux/usb/ohci_pdriver.h> 422c8788bfSSergei Shtylyov #include <linux/pm_runtime.h> 43250a2723SRob Herring #include <mach/irqs.h> 44f411fadeSMagnus Damm #include <mach/r8a7779.h> 45a662c082SMagnus Damm #include <mach/common.h> 46f411fadeSMagnus Damm #include <asm/mach-types.h> 47f411fadeSMagnus Damm #include <asm/mach/arch.h> 48df27a2d8SMagnus Damm #include <asm/mach/time.h> 493e353b87SMagnus Damm #include <asm/mach/map.h> 508bac13f5SMagnus Damm #include <asm/hardware/cache-l2x0.h> 513e353b87SMagnus Damm 523e353b87SMagnus Damm static struct map_desc r8a7779_io_desc[] __initdata = { 533e353b87SMagnus Damm /* 2M entity map for 0xf0000000 (MPCORE) */ 543e353b87SMagnus Damm { 553e353b87SMagnus Damm .virtual = 0xf0000000, 563e353b87SMagnus Damm .pfn = __phys_to_pfn(0xf0000000), 573e353b87SMagnus Damm .length = SZ_2M, 583e353b87SMagnus Damm .type = MT_DEVICE_NONSHARED 593e353b87SMagnus Damm }, 603e353b87SMagnus Damm /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ 613e353b87SMagnus Damm { 623e353b87SMagnus Damm .virtual = 0xfe000000, 633e353b87SMagnus Damm .pfn = __phys_to_pfn(0xfe000000), 643e353b87SMagnus Damm .length = SZ_16M, 653e353b87SMagnus Damm .type = MT_DEVICE_NONSHARED 663e353b87SMagnus Damm }, 673e353b87SMagnus Damm }; 683e353b87SMagnus Damm 693e353b87SMagnus Damm void __init r8a7779_map_io(void) 703e353b87SMagnus Damm { 713e353b87SMagnus Damm iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); 723e353b87SMagnus Damm } 73f411fadeSMagnus Damm 745b3859d7SKuninori Morimoto /* IRQ */ 755b3859d7SKuninori Morimoto #define INT2SMSKCR0 IOMEM(0xfe7822a0) 765b3859d7SKuninori Morimoto #define INT2SMSKCR1 IOMEM(0xfe7822a4) 775b3859d7SKuninori Morimoto #define INT2SMSKCR2 IOMEM(0xfe7822a8) 785b3859d7SKuninori Morimoto #define INT2SMSKCR3 IOMEM(0xfe7822ac) 795b3859d7SKuninori Morimoto #define INT2SMSKCR4 IOMEM(0xfe7822b0) 805b3859d7SKuninori Morimoto 815b3859d7SKuninori Morimoto #define INT2NTSR0 IOMEM(0xfe700060) 825b3859d7SKuninori Morimoto #define INT2NTSR1 IOMEM(0xfe700064) 835b3859d7SKuninori Morimoto 845b3859d7SKuninori Morimoto static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = { 855b3859d7SKuninori Morimoto .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 865b3859d7SKuninori Morimoto .sense_bitfield_width = 2, 875b3859d7SKuninori Morimoto }; 885b3859d7SKuninori Morimoto 895b3859d7SKuninori Morimoto static struct resource irqpin0_resources[] __initdata = { 905b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 915b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 925b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 935b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 945b3859d7SKuninori Morimoto DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 955b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */ 965b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */ 975b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */ 985b3859d7SKuninori Morimoto DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */ 995b3859d7SKuninori Morimoto }; 1005b3859d7SKuninori Morimoto 1015b3859d7SKuninori Morimoto void __init r8a7779_init_irq_extpin(int irlm) 1025b3859d7SKuninori Morimoto { 1035b3859d7SKuninori Morimoto void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 1045b3859d7SKuninori Morimoto u32 tmp; 1055b3859d7SKuninori Morimoto 1065b3859d7SKuninori Morimoto if (!icr0) { 1075b3859d7SKuninori Morimoto pr_warn("r8a7779: unable to setup external irq pin mode\n"); 1085b3859d7SKuninori Morimoto return; 1095b3859d7SKuninori Morimoto } 1105b3859d7SKuninori Morimoto 1115b3859d7SKuninori Morimoto tmp = ioread32(icr0); 1125b3859d7SKuninori Morimoto if (irlm) 1135b3859d7SKuninori Morimoto tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 1145b3859d7SKuninori Morimoto else 1155b3859d7SKuninori Morimoto tmp &= ~(1 << 23); /* IRL mode - not supported */ 1165b3859d7SKuninori Morimoto tmp |= (1 << 21); /* LVLMODE = 1 */ 1175b3859d7SKuninori Morimoto iowrite32(tmp, icr0); 1185b3859d7SKuninori Morimoto iounmap(icr0); 1195b3859d7SKuninori Morimoto 1205b3859d7SKuninori Morimoto if (irlm) 1215b3859d7SKuninori Morimoto platform_device_register_resndata( 1225b3859d7SKuninori Morimoto &platform_bus, "renesas_intc_irqpin", -1, 1235b3859d7SKuninori Morimoto irqpin0_resources, ARRAY_SIZE(irqpin0_resources), 1245b3859d7SKuninori Morimoto &irqpin0_platform_data, sizeof(irqpin0_platform_data)); 1255b3859d7SKuninori Morimoto } 1265b3859d7SKuninori Morimoto 1275b3859d7SKuninori Morimoto /* PFC/GPIO */ 1288b6edf36SLaurent Pinchart static struct resource r8a7779_pfc_resources[] = { 1290ccaf5bbSMagnus Damm DEFINE_RES_MEM(0xfffc0000, 0x023c), 1308b6edf36SLaurent Pinchart }; 1318b6edf36SLaurent Pinchart 1328b6edf36SLaurent Pinchart static struct platform_device r8a7779_pfc_device = { 1338b6edf36SLaurent Pinchart .name = "pfc-r8a7779", 1348b6edf36SLaurent Pinchart .id = -1, 1358b6edf36SLaurent Pinchart .resource = r8a7779_pfc_resources, 1368b6edf36SLaurent Pinchart .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), 1378b6edf36SLaurent Pinchart }; 1388b6edf36SLaurent Pinchart 13937a72d07SLaurent Pinchart #define R8A7779_GPIO(idx, npins) \ 14037a72d07SLaurent Pinchart static struct resource r8a7779_gpio##idx##_resources[] = { \ 1410ccaf5bbSMagnus Damm DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \ 1420ccaf5bbSMagnus Damm DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \ 14337a72d07SLaurent Pinchart }; \ 14437a72d07SLaurent Pinchart \ 14537a72d07SLaurent Pinchart static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \ 14637a72d07SLaurent Pinchart .gpio_base = 32 * (idx), \ 14737a72d07SLaurent Pinchart .irq_base = 0, \ 14837a72d07SLaurent Pinchart .number_of_pins = npins, \ 14937a72d07SLaurent Pinchart .pctl_name = "pfc-r8a7779", \ 15037a72d07SLaurent Pinchart }; \ 15137a72d07SLaurent Pinchart \ 15237a72d07SLaurent Pinchart static struct platform_device r8a7779_gpio##idx##_device = { \ 15337a72d07SLaurent Pinchart .name = "gpio_rcar", \ 15437a72d07SLaurent Pinchart .id = idx, \ 15537a72d07SLaurent Pinchart .resource = r8a7779_gpio##idx##_resources, \ 15637a72d07SLaurent Pinchart .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \ 15737a72d07SLaurent Pinchart .dev = { \ 15837a72d07SLaurent Pinchart .platform_data = &r8a7779_gpio##idx##_platform_data, \ 15937a72d07SLaurent Pinchart }, \ 16037a72d07SLaurent Pinchart } 16137a72d07SLaurent Pinchart 16237a72d07SLaurent Pinchart R8A7779_GPIO(0, 32); 16337a72d07SLaurent Pinchart R8A7779_GPIO(1, 32); 16437a72d07SLaurent Pinchart R8A7779_GPIO(2, 32); 16537a72d07SLaurent Pinchart R8A7779_GPIO(3, 32); 16637a72d07SLaurent Pinchart R8A7779_GPIO(4, 32); 16737a72d07SLaurent Pinchart R8A7779_GPIO(5, 32); 16837a72d07SLaurent Pinchart R8A7779_GPIO(6, 9); 16937a72d07SLaurent Pinchart 17037a72d07SLaurent Pinchart static struct platform_device *r8a7779_pinctrl_devices[] __initdata = { 17137a72d07SLaurent Pinchart &r8a7779_pfc_device, 17237a72d07SLaurent Pinchart &r8a7779_gpio0_device, 17337a72d07SLaurent Pinchart &r8a7779_gpio1_device, 17437a72d07SLaurent Pinchart &r8a7779_gpio2_device, 17537a72d07SLaurent Pinchart &r8a7779_gpio3_device, 17637a72d07SLaurent Pinchart &r8a7779_gpio4_device, 17737a72d07SLaurent Pinchart &r8a7779_gpio5_device, 17837a72d07SLaurent Pinchart &r8a7779_gpio6_device, 17937a72d07SLaurent Pinchart }; 18037a72d07SLaurent Pinchart 1818b6edf36SLaurent Pinchart void __init r8a7779_pinmux_init(void) 1828b6edf36SLaurent Pinchart { 18337a72d07SLaurent Pinchart platform_add_devices(r8a7779_pinctrl_devices, 18437a72d07SLaurent Pinchart ARRAY_SIZE(r8a7779_pinctrl_devices)); 1858b6edf36SLaurent Pinchart } 1868b6edf36SLaurent Pinchart 187f411fadeSMagnus Damm static struct plat_sci_port scif0_platform_data = { 188f411fadeSMagnus Damm .mapbase = 0xffe40000, 189f411fadeSMagnus Damm .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 190f411fadeSMagnus Damm .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 191f411fadeSMagnus Damm .scbrr_algo_id = SCBRR_ALGO_2, 192f411fadeSMagnus Damm .type = PORT_SCIF, 193dbe95ad0SKuninori Morimoto .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), 194f411fadeSMagnus Damm }; 195f411fadeSMagnus Damm 196f411fadeSMagnus Damm static struct platform_device scif0_device = { 197f411fadeSMagnus Damm .name = "sh-sci", 198f411fadeSMagnus Damm .id = 0, 199f411fadeSMagnus Damm .dev = { 200f411fadeSMagnus Damm .platform_data = &scif0_platform_data, 201f411fadeSMagnus Damm }, 202f411fadeSMagnus Damm }; 203f411fadeSMagnus Damm 204f411fadeSMagnus Damm static struct plat_sci_port scif1_platform_data = { 205f411fadeSMagnus Damm .mapbase = 0xffe41000, 206f411fadeSMagnus Damm .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 207f411fadeSMagnus Damm .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 208f411fadeSMagnus Damm .scbrr_algo_id = SCBRR_ALGO_2, 209f411fadeSMagnus Damm .type = PORT_SCIF, 210dbe95ad0SKuninori Morimoto .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)), 211f411fadeSMagnus Damm }; 212f411fadeSMagnus Damm 213f411fadeSMagnus Damm static struct platform_device scif1_device = { 214f411fadeSMagnus Damm .name = "sh-sci", 215f411fadeSMagnus Damm .id = 1, 216f411fadeSMagnus Damm .dev = { 217f411fadeSMagnus Damm .platform_data = &scif1_platform_data, 218f411fadeSMagnus Damm }, 219f411fadeSMagnus Damm }; 220f411fadeSMagnus Damm 221f411fadeSMagnus Damm static struct plat_sci_port scif2_platform_data = { 222f411fadeSMagnus Damm .mapbase = 0xffe42000, 223f411fadeSMagnus Damm .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 224f411fadeSMagnus Damm .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 225f411fadeSMagnus Damm .scbrr_algo_id = SCBRR_ALGO_2, 226f411fadeSMagnus Damm .type = PORT_SCIF, 227dbe95ad0SKuninori Morimoto .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)), 228f411fadeSMagnus Damm }; 229f411fadeSMagnus Damm 230f411fadeSMagnus Damm static struct platform_device scif2_device = { 231f411fadeSMagnus Damm .name = "sh-sci", 232f411fadeSMagnus Damm .id = 2, 233f411fadeSMagnus Damm .dev = { 234f411fadeSMagnus Damm .platform_data = &scif2_platform_data, 235f411fadeSMagnus Damm }, 236f411fadeSMagnus Damm }; 237f411fadeSMagnus Damm 238f411fadeSMagnus Damm static struct plat_sci_port scif3_platform_data = { 239f411fadeSMagnus Damm .mapbase = 0xffe43000, 240f411fadeSMagnus Damm .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 241f411fadeSMagnus Damm .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 242f411fadeSMagnus Damm .scbrr_algo_id = SCBRR_ALGO_2, 243f411fadeSMagnus Damm .type = PORT_SCIF, 244dbe95ad0SKuninori Morimoto .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)), 245f411fadeSMagnus Damm }; 246f411fadeSMagnus Damm 247f411fadeSMagnus Damm static struct platform_device scif3_device = { 248f411fadeSMagnus Damm .name = "sh-sci", 249f411fadeSMagnus Damm .id = 3, 250f411fadeSMagnus Damm .dev = { 251f411fadeSMagnus Damm .platform_data = &scif3_platform_data, 252f411fadeSMagnus Damm }, 253f411fadeSMagnus Damm }; 254f411fadeSMagnus Damm 255f411fadeSMagnus Damm static struct plat_sci_port scif4_platform_data = { 256f411fadeSMagnus Damm .mapbase = 0xffe44000, 257f411fadeSMagnus Damm .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 258f411fadeSMagnus Damm .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 259f411fadeSMagnus Damm .scbrr_algo_id = SCBRR_ALGO_2, 260f411fadeSMagnus Damm .type = PORT_SCIF, 261dbe95ad0SKuninori Morimoto .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)), 262f411fadeSMagnus Damm }; 263f411fadeSMagnus Damm 264f411fadeSMagnus Damm static struct platform_device scif4_device = { 265f411fadeSMagnus Damm .name = "sh-sci", 266f411fadeSMagnus Damm .id = 4, 267f411fadeSMagnus Damm .dev = { 268f411fadeSMagnus Damm .platform_data = &scif4_platform_data, 269f411fadeSMagnus Damm }, 270f411fadeSMagnus Damm }; 271f411fadeSMagnus Damm 272f411fadeSMagnus Damm static struct plat_sci_port scif5_platform_data = { 273f411fadeSMagnus Damm .mapbase = 0xffe45000, 274f411fadeSMagnus Damm .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 275f411fadeSMagnus Damm .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 276f411fadeSMagnus Damm .scbrr_algo_id = SCBRR_ALGO_2, 277f411fadeSMagnus Damm .type = PORT_SCIF, 278dbe95ad0SKuninori Morimoto .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)), 279f411fadeSMagnus Damm }; 280f411fadeSMagnus Damm 281f411fadeSMagnus Damm static struct platform_device scif5_device = { 282f411fadeSMagnus Damm .name = "sh-sci", 283f411fadeSMagnus Damm .id = 5, 284f411fadeSMagnus Damm .dev = { 285f411fadeSMagnus Damm .platform_data = &scif5_platform_data, 286f411fadeSMagnus Damm }, 287f411fadeSMagnus Damm }; 288f411fadeSMagnus Damm 289f411fadeSMagnus Damm /* TMU */ 290f411fadeSMagnus Damm static struct sh_timer_config tmu00_platform_data = { 291f411fadeSMagnus Damm .name = "TMU00", 292f411fadeSMagnus Damm .channel_offset = 0x4, 293f411fadeSMagnus Damm .timer_bit = 0, 294f411fadeSMagnus Damm .clockevent_rating = 200, 295f411fadeSMagnus Damm }; 296f411fadeSMagnus Damm 297f411fadeSMagnus Damm static struct resource tmu00_resources[] = { 298f411fadeSMagnus Damm [0] = { 299f411fadeSMagnus Damm .name = "TMU00", 300f411fadeSMagnus Damm .start = 0xffd80008, 301f411fadeSMagnus Damm .end = 0xffd80013, 302f411fadeSMagnus Damm .flags = IORESOURCE_MEM, 303f411fadeSMagnus Damm }, 304f411fadeSMagnus Damm [1] = { 305dbe95ad0SKuninori Morimoto .start = gic_iid(0x40), 306f411fadeSMagnus Damm .flags = IORESOURCE_IRQ, 307f411fadeSMagnus Damm }, 308f411fadeSMagnus Damm }; 309f411fadeSMagnus Damm 310f411fadeSMagnus Damm static struct platform_device tmu00_device = { 311f411fadeSMagnus Damm .name = "sh_tmu", 312f411fadeSMagnus Damm .id = 0, 313f411fadeSMagnus Damm .dev = { 314f411fadeSMagnus Damm .platform_data = &tmu00_platform_data, 315f411fadeSMagnus Damm }, 316f411fadeSMagnus Damm .resource = tmu00_resources, 317f411fadeSMagnus Damm .num_resources = ARRAY_SIZE(tmu00_resources), 318f411fadeSMagnus Damm }; 319f411fadeSMagnus Damm 320f411fadeSMagnus Damm static struct sh_timer_config tmu01_platform_data = { 321f411fadeSMagnus Damm .name = "TMU01", 322f411fadeSMagnus Damm .channel_offset = 0x10, 323f411fadeSMagnus Damm .timer_bit = 1, 324f411fadeSMagnus Damm .clocksource_rating = 200, 325f411fadeSMagnus Damm }; 326f411fadeSMagnus Damm 327f411fadeSMagnus Damm static struct resource tmu01_resources[] = { 328f411fadeSMagnus Damm [0] = { 329f411fadeSMagnus Damm .name = "TMU01", 330f411fadeSMagnus Damm .start = 0xffd80014, 331f411fadeSMagnus Damm .end = 0xffd8001f, 332f411fadeSMagnus Damm .flags = IORESOURCE_MEM, 333f411fadeSMagnus Damm }, 334f411fadeSMagnus Damm [1] = { 335dbe95ad0SKuninori Morimoto .start = gic_iid(0x41), 336f411fadeSMagnus Damm .flags = IORESOURCE_IRQ, 337f411fadeSMagnus Damm }, 338f411fadeSMagnus Damm }; 339f411fadeSMagnus Damm 340f411fadeSMagnus Damm static struct platform_device tmu01_device = { 341f411fadeSMagnus Damm .name = "sh_tmu", 342f411fadeSMagnus Damm .id = 1, 343f411fadeSMagnus Damm .dev = { 344f411fadeSMagnus Damm .platform_data = &tmu01_platform_data, 345f411fadeSMagnus Damm }, 346f411fadeSMagnus Damm .resource = tmu01_resources, 347f411fadeSMagnus Damm .num_resources = ARRAY_SIZE(tmu01_resources), 348f411fadeSMagnus Damm }; 349f411fadeSMagnus Damm 350ccc2a27bSKuninori Morimoto /* I2C */ 351ccc2a27bSKuninori Morimoto static struct resource rcar_i2c0_res[] = { 352ccc2a27bSKuninori Morimoto { 353ccc2a27bSKuninori Morimoto .start = 0xffc70000, 354ccc2a27bSKuninori Morimoto .end = 0xffc70fff, 355ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 356ccc2a27bSKuninori Morimoto }, { 357dbe95ad0SKuninori Morimoto .start = gic_iid(0x6f), 358ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 359ccc2a27bSKuninori Morimoto }, 360ccc2a27bSKuninori Morimoto }; 361ccc2a27bSKuninori Morimoto 362ccc2a27bSKuninori Morimoto static struct platform_device i2c0_device = { 363ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 364ccc2a27bSKuninori Morimoto .id = 0, 365ccc2a27bSKuninori Morimoto .resource = rcar_i2c0_res, 366ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c0_res), 367ccc2a27bSKuninori Morimoto }; 368ccc2a27bSKuninori Morimoto 369ccc2a27bSKuninori Morimoto static struct resource rcar_i2c1_res[] = { 370ccc2a27bSKuninori Morimoto { 371ccc2a27bSKuninori Morimoto .start = 0xffc71000, 372ccc2a27bSKuninori Morimoto .end = 0xffc71fff, 373ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 374ccc2a27bSKuninori Morimoto }, { 375dbe95ad0SKuninori Morimoto .start = gic_iid(0x72), 376ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 377ccc2a27bSKuninori Morimoto }, 378ccc2a27bSKuninori Morimoto }; 379ccc2a27bSKuninori Morimoto 380ccc2a27bSKuninori Morimoto static struct platform_device i2c1_device = { 381ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 382ccc2a27bSKuninori Morimoto .id = 1, 383ccc2a27bSKuninori Morimoto .resource = rcar_i2c1_res, 384ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c1_res), 385ccc2a27bSKuninori Morimoto }; 386ccc2a27bSKuninori Morimoto 387ccc2a27bSKuninori Morimoto static struct resource rcar_i2c2_res[] = { 388ccc2a27bSKuninori Morimoto { 389ccc2a27bSKuninori Morimoto .start = 0xffc72000, 390ccc2a27bSKuninori Morimoto .end = 0xffc72fff, 391ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 392ccc2a27bSKuninori Morimoto }, { 393dbe95ad0SKuninori Morimoto .start = gic_iid(0x70), 394ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 395ccc2a27bSKuninori Morimoto }, 396ccc2a27bSKuninori Morimoto }; 397ccc2a27bSKuninori Morimoto 398ccc2a27bSKuninori Morimoto static struct platform_device i2c2_device = { 399ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 400ccc2a27bSKuninori Morimoto .id = 2, 401ccc2a27bSKuninori Morimoto .resource = rcar_i2c2_res, 402ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c2_res), 403ccc2a27bSKuninori Morimoto }; 404ccc2a27bSKuninori Morimoto 405ccc2a27bSKuninori Morimoto static struct resource rcar_i2c3_res[] = { 406ccc2a27bSKuninori Morimoto { 407ccc2a27bSKuninori Morimoto .start = 0xffc73000, 408ccc2a27bSKuninori Morimoto .end = 0xffc73fff, 409ccc2a27bSKuninori Morimoto .flags = IORESOURCE_MEM, 410ccc2a27bSKuninori Morimoto }, { 411dbe95ad0SKuninori Morimoto .start = gic_iid(0x71), 412ccc2a27bSKuninori Morimoto .flags = IORESOURCE_IRQ, 413ccc2a27bSKuninori Morimoto }, 414ccc2a27bSKuninori Morimoto }; 415ccc2a27bSKuninori Morimoto 416ccc2a27bSKuninori Morimoto static struct platform_device i2c3_device = { 417ccc2a27bSKuninori Morimoto .name = "i2c-rcar", 418ccc2a27bSKuninori Morimoto .id = 3, 419ccc2a27bSKuninori Morimoto .resource = rcar_i2c3_res, 420ccc2a27bSKuninori Morimoto .num_resources = ARRAY_SIZE(rcar_i2c3_res), 421ccc2a27bSKuninori Morimoto }; 422ccc2a27bSKuninori Morimoto 423a7b9837cSVladimir Barinov static struct resource sata_resources[] = { 424a7b9837cSVladimir Barinov [0] = { 425a7b9837cSVladimir Barinov .name = "rcar-sata", 426a7b9837cSVladimir Barinov .start = 0xfc600000, 427a7b9837cSVladimir Barinov .end = 0xfc601fff, 428a7b9837cSVladimir Barinov .flags = IORESOURCE_MEM, 429a7b9837cSVladimir Barinov }, 430a7b9837cSVladimir Barinov [1] = { 431d60cd5f1SSergei Shtylyov .start = gic_iid(0x84), 432a7b9837cSVladimir Barinov .flags = IORESOURCE_IRQ, 433a7b9837cSVladimir Barinov }, 434a7b9837cSVladimir Barinov }; 435a7b9837cSVladimir Barinov 436a7b9837cSVladimir Barinov static struct platform_device sata_device = { 437a7b9837cSVladimir Barinov .name = "sata_rcar", 438a7b9837cSVladimir Barinov .id = -1, 439a7b9837cSVladimir Barinov .resource = sata_resources, 440a7b9837cSVladimir Barinov .num_resources = ARRAY_SIZE(sata_resources), 441a7b9837cSVladimir Barinov .dev = { 442a7b9837cSVladimir Barinov .dma_mask = &sata_device.dev.coherent_dma_mask, 443a7b9837cSVladimir Barinov .coherent_dma_mask = DMA_BIT_MASK(32), 444a7b9837cSVladimir Barinov }, 445a7b9837cSVladimir Barinov }; 446a7b9837cSVladimir Barinov 4472c8788bfSSergei Shtylyov /* USB */ 4482c8788bfSSergei Shtylyov static struct usb_phy *phy; 4492c8788bfSSergei Shtylyov 4502c8788bfSSergei Shtylyov static int usb_power_on(struct platform_device *pdev) 4512c8788bfSSergei Shtylyov { 4522c8788bfSSergei Shtylyov if (IS_ERR(phy)) 4532c8788bfSSergei Shtylyov return PTR_ERR(phy); 4542c8788bfSSergei Shtylyov 4552c8788bfSSergei Shtylyov pm_runtime_enable(&pdev->dev); 4562c8788bfSSergei Shtylyov pm_runtime_get_sync(&pdev->dev); 4572c8788bfSSergei Shtylyov 4582c8788bfSSergei Shtylyov usb_phy_init(phy); 4592c8788bfSSergei Shtylyov 4602c8788bfSSergei Shtylyov return 0; 4612c8788bfSSergei Shtylyov } 4622c8788bfSSergei Shtylyov 4632c8788bfSSergei Shtylyov static void usb_power_off(struct platform_device *pdev) 4642c8788bfSSergei Shtylyov { 4652c8788bfSSergei Shtylyov if (IS_ERR(phy)) 4662c8788bfSSergei Shtylyov return; 4672c8788bfSSergei Shtylyov 4682c8788bfSSergei Shtylyov usb_phy_shutdown(phy); 4692c8788bfSSergei Shtylyov 4702c8788bfSSergei Shtylyov pm_runtime_put_sync(&pdev->dev); 4712c8788bfSSergei Shtylyov pm_runtime_disable(&pdev->dev); 4722c8788bfSSergei Shtylyov } 4732c8788bfSSergei Shtylyov 47484a812daSSergei Shtylyov static int ehci_init_internal_buffer(struct usb_hcd *hcd) 47584a812daSSergei Shtylyov { 47684a812daSSergei Shtylyov /* 47784a812daSSergei Shtylyov * Below are recommended values from the datasheet; 47884a812daSSergei Shtylyov * see [USB :: Setting of EHCI Internal Buffer]. 47984a812daSSergei Shtylyov */ 48084a812daSSergei Shtylyov /* EHCI IP internal buffer setting */ 48184a812daSSergei Shtylyov iowrite32(0x00ff0040, hcd->regs + 0x0094); 48284a812daSSergei Shtylyov /* EHCI IP internal buffer enable */ 48384a812daSSergei Shtylyov iowrite32(0x00000001, hcd->regs + 0x009C); 48484a812daSSergei Shtylyov 48584a812daSSergei Shtylyov return 0; 48684a812daSSergei Shtylyov } 48784a812daSSergei Shtylyov 4882c8788bfSSergei Shtylyov static struct usb_ehci_pdata ehcix_pdata = { 4892c8788bfSSergei Shtylyov .power_on = usb_power_on, 4902c8788bfSSergei Shtylyov .power_off = usb_power_off, 4912c8788bfSSergei Shtylyov .power_suspend = usb_power_off, 49284a812daSSergei Shtylyov .pre_setup = ehci_init_internal_buffer, 4932c8788bfSSergei Shtylyov }; 4942c8788bfSSergei Shtylyov 4952c8788bfSSergei Shtylyov static struct resource ehci0_resources[] = { 4962c8788bfSSergei Shtylyov [0] = { 4972c8788bfSSergei Shtylyov .start = 0xffe70000, 4982c8788bfSSergei Shtylyov .end = 0xffe70400 - 1, 4992c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 5002c8788bfSSergei Shtylyov }, 5012c8788bfSSergei Shtylyov [1] = { 5022c8788bfSSergei Shtylyov .start = gic_iid(0x4c), 5032c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 5042c8788bfSSergei Shtylyov }, 5052c8788bfSSergei Shtylyov }; 5062c8788bfSSergei Shtylyov 5072c8788bfSSergei Shtylyov static struct platform_device ehci0_device = { 5082c8788bfSSergei Shtylyov .name = "ehci-platform", 5092c8788bfSSergei Shtylyov .id = 0, 5102c8788bfSSergei Shtylyov .dev = { 5112c8788bfSSergei Shtylyov .dma_mask = &ehci0_device.dev.coherent_dma_mask, 5122c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 5132c8788bfSSergei Shtylyov .platform_data = &ehcix_pdata, 5142c8788bfSSergei Shtylyov }, 5152c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ehci0_resources), 5162c8788bfSSergei Shtylyov .resource = ehci0_resources, 5172c8788bfSSergei Shtylyov }; 5182c8788bfSSergei Shtylyov 5192c8788bfSSergei Shtylyov static struct resource ehci1_resources[] = { 5202c8788bfSSergei Shtylyov [0] = { 5212c8788bfSSergei Shtylyov .start = 0xfff70000, 5222c8788bfSSergei Shtylyov .end = 0xfff70400 - 1, 5232c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 5242c8788bfSSergei Shtylyov }, 5252c8788bfSSergei Shtylyov [1] = { 5262c8788bfSSergei Shtylyov .start = gic_iid(0x4d), 5272c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 5282c8788bfSSergei Shtylyov }, 5292c8788bfSSergei Shtylyov }; 5302c8788bfSSergei Shtylyov 5312c8788bfSSergei Shtylyov static struct platform_device ehci1_device = { 5322c8788bfSSergei Shtylyov .name = "ehci-platform", 5332c8788bfSSergei Shtylyov .id = 1, 5342c8788bfSSergei Shtylyov .dev = { 5352c8788bfSSergei Shtylyov .dma_mask = &ehci1_device.dev.coherent_dma_mask, 5362c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 5372c8788bfSSergei Shtylyov .platform_data = &ehcix_pdata, 5382c8788bfSSergei Shtylyov }, 5392c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ehci1_resources), 5402c8788bfSSergei Shtylyov .resource = ehci1_resources, 5412c8788bfSSergei Shtylyov }; 5422c8788bfSSergei Shtylyov 5432c8788bfSSergei Shtylyov static struct usb_ohci_pdata ohcix_pdata = { 5442c8788bfSSergei Shtylyov .power_on = usb_power_on, 5452c8788bfSSergei Shtylyov .power_off = usb_power_off, 5462c8788bfSSergei Shtylyov .power_suspend = usb_power_off, 5472c8788bfSSergei Shtylyov }; 5482c8788bfSSergei Shtylyov 5492c8788bfSSergei Shtylyov static struct resource ohci0_resources[] = { 5502c8788bfSSergei Shtylyov [0] = { 5512c8788bfSSergei Shtylyov .start = 0xffe70400, 5522c8788bfSSergei Shtylyov .end = 0xffe70800 - 1, 5532c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 5542c8788bfSSergei Shtylyov }, 5552c8788bfSSergei Shtylyov [1] = { 5562c8788bfSSergei Shtylyov .start = gic_iid(0x4c), 5572c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 5582c8788bfSSergei Shtylyov }, 5592c8788bfSSergei Shtylyov }; 5602c8788bfSSergei Shtylyov 5612c8788bfSSergei Shtylyov static struct platform_device ohci0_device = { 5622c8788bfSSergei Shtylyov .name = "ohci-platform", 5632c8788bfSSergei Shtylyov .id = 0, 5642c8788bfSSergei Shtylyov .dev = { 5652c8788bfSSergei Shtylyov .dma_mask = &ohci0_device.dev.coherent_dma_mask, 5662c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 5672c8788bfSSergei Shtylyov .platform_data = &ohcix_pdata, 5682c8788bfSSergei Shtylyov }, 5692c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ohci0_resources), 5702c8788bfSSergei Shtylyov .resource = ohci0_resources, 5712c8788bfSSergei Shtylyov }; 5722c8788bfSSergei Shtylyov 5732c8788bfSSergei Shtylyov static struct resource ohci1_resources[] = { 5742c8788bfSSergei Shtylyov [0] = { 5752c8788bfSSergei Shtylyov .start = 0xfff70400, 5762c8788bfSSergei Shtylyov .end = 0xfff70800 - 1, 5772c8788bfSSergei Shtylyov .flags = IORESOURCE_MEM, 5782c8788bfSSergei Shtylyov }, 5792c8788bfSSergei Shtylyov [1] = { 5802c8788bfSSergei Shtylyov .start = gic_iid(0x4d), 5812c8788bfSSergei Shtylyov .flags = IORESOURCE_IRQ, 5822c8788bfSSergei Shtylyov }, 5832c8788bfSSergei Shtylyov }; 5842c8788bfSSergei Shtylyov 5852c8788bfSSergei Shtylyov static struct platform_device ohci1_device = { 5862c8788bfSSergei Shtylyov .name = "ohci-platform", 5872c8788bfSSergei Shtylyov .id = 1, 5882c8788bfSSergei Shtylyov .dev = { 5892c8788bfSSergei Shtylyov .dma_mask = &ohci1_device.dev.coherent_dma_mask, 5902c8788bfSSergei Shtylyov .coherent_dma_mask = 0xffffffff, 5912c8788bfSSergei Shtylyov .platform_data = &ohcix_pdata, 5922c8788bfSSergei Shtylyov }, 5932c8788bfSSergei Shtylyov .num_resources = ARRAY_SIZE(ohci1_resources), 5942c8788bfSSergei Shtylyov .resource = ohci1_resources, 5952c8788bfSSergei Shtylyov }; 5962c8788bfSSergei Shtylyov 597dace48d0SSergei Shtylyov /* Ether */ 598c7537655SKuninori Morimoto static struct resource ether_resources[] __initdata = { 599dace48d0SSergei Shtylyov { 600dace48d0SSergei Shtylyov .start = 0xfde00000, 601dace48d0SSergei Shtylyov .end = 0xfde003ff, 602dace48d0SSergei Shtylyov .flags = IORESOURCE_MEM, 603dace48d0SSergei Shtylyov }, { 604dace48d0SSergei Shtylyov .start = gic_iid(0xb4), 605dace48d0SSergei Shtylyov .flags = IORESOURCE_IRQ, 606dace48d0SSergei Shtylyov }, 607dace48d0SSergei Shtylyov }; 608dace48d0SSergei Shtylyov 6094714a025SVladimir Barinov #define R8A7779_VIN(idx) \ 6104714a025SVladimir Barinov static struct resource vin##idx##_resources[] __initdata = { \ 6114714a025SVladimir Barinov DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ 6124714a025SVladimir Barinov DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ 6134714a025SVladimir Barinov }; \ 6144714a025SVladimir Barinov \ 6154714a025SVladimir Barinov static struct platform_device_info vin##idx##_info __initdata = { \ 6164714a025SVladimir Barinov .parent = &platform_bus, \ 6174714a025SVladimir Barinov .name = "r8a7779-vin", \ 6184714a025SVladimir Barinov .id = idx, \ 6194714a025SVladimir Barinov .res = vin##idx##_resources, \ 6204714a025SVladimir Barinov .num_res = ARRAY_SIZE(vin##idx##_resources), \ 6214714a025SVladimir Barinov .dma_mask = DMA_BIT_MASK(32), \ 6224714a025SVladimir Barinov } 6234714a025SVladimir Barinov 6244714a025SVladimir Barinov R8A7779_VIN(0); 6254714a025SVladimir Barinov R8A7779_VIN(1); 6264714a025SVladimir Barinov R8A7779_VIN(2); 6274714a025SVladimir Barinov R8A7779_VIN(3); 6284714a025SVladimir Barinov 6294714a025SVladimir Barinov static struct platform_device_info *vin_info_table[] __initdata = { 6304714a025SVladimir Barinov &vin0_info, 6314714a025SVladimir Barinov &vin1_info, 6324714a025SVladimir Barinov &vin2_info, 6334714a025SVladimir Barinov &vin3_info, 6344714a025SVladimir Barinov }; 6354714a025SVladimir Barinov 636441f7502SMax Filippov /* HPB-DMA */ 637441f7502SMax Filippov 638441f7502SMax Filippov /* Asynchronous mode register bits */ 639441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */ 640441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */ 641441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */ 642441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */ 643441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */ 644441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */ 645441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */ 646441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */ 647441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */ 648441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */ 649441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */ 650441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */ 651441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */ 652441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */ 653441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */ 654441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */ 655441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */ 656441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */ 657441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */ 658441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */ 659441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */ 660441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */ 661441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */ 662441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */ 663441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */ 664441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */ 665441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */ 666441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */ 667441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */ 668441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */ 669441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */ 670441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */ 671441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */ 672441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */ 673441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */ 674441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */ 675441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */ 676441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */ 677441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */ 678441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */ 679441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */ 680441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */ 681441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */ 682441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */ 683441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */ 684441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */ 685441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */ 686441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */ 687441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */ 688441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */ 689441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */ 690441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */ 691441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */ 692441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */ 693441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */ 694441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */ 695441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ 696441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */ 697441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */ 698441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */ 699441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */ 700441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */ 701441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 702441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */ 703441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */ 704441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */ 705441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */ 706441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */ 707441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */ 708441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */ 709441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */ 710441f7502SMax Filippov #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */ 711441f7502SMax Filippov 712441f7502SMax Filippov static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 713441f7502SMax Filippov { 714441f7502SMax Filippov .id = HPBDMA_SLAVE_SDHI0_TX, 715441f7502SMax Filippov .addr = 0xffe4c000 + 0x30, 716441f7502SMax Filippov .dcr = HPB_DMAE_DCR_SPDS_16BIT | 717441f7502SMax Filippov HPB_DMAE_DCR_DMDL | 718441f7502SMax Filippov HPB_DMAE_DCR_DPDS_16BIT, 719441f7502SMax Filippov .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 720441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST22 | 721441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST23, 722441f7502SMax Filippov .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE | 723441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST, 724441f7502SMax Filippov .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK | 725441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD21_MASK, 726441f7502SMax Filippov .port = 0x0D0C, 727441f7502SMax Filippov .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 728441f7502SMax Filippov .dma_ch = 21, 729441f7502SMax Filippov }, { 730441f7502SMax Filippov .id = HPBDMA_SLAVE_SDHI0_RX, 731441f7502SMax Filippov .addr = 0xffe4c000 + 0x30, 732441f7502SMax Filippov .dcr = HPB_DMAE_DCR_SMDL | 733441f7502SMax Filippov HPB_DMAE_DCR_SPDS_16BIT | 734441f7502SMax Filippov HPB_DMAE_DCR_DPDS_16BIT, 735441f7502SMax Filippov .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 736441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST22 | 737441f7502SMax Filippov HPB_DMAE_ASYNCRSTR_ASRST23, 738441f7502SMax Filippov .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE | 739441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST, 740441f7502SMax Filippov .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK | 741441f7502SMax Filippov HPB_DMAE_ASYNCMDR_ASBTMD22_MASK, 742441f7502SMax Filippov .port = 0x0D0C, 743441f7502SMax Filippov .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 744441f7502SMax Filippov .dma_ch = 22, 745441f7502SMax Filippov }, 746441f7502SMax Filippov }; 747441f7502SMax Filippov 748441f7502SMax Filippov static const struct hpb_dmae_channel hpb_dmae_channels[] = { 749441f7502SMax Filippov HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 750441f7502SMax Filippov HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 751441f7502SMax Filippov }; 752441f7502SMax Filippov 753441f7502SMax Filippov static struct hpb_dmae_pdata dma_platform_data __initdata = { 754441f7502SMax Filippov .slaves = hpb_dmae_slaves, 755441f7502SMax Filippov .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), 756441f7502SMax Filippov .channels = hpb_dmae_channels, 757441f7502SMax Filippov .num_channels = ARRAY_SIZE(hpb_dmae_channels), 758441f7502SMax Filippov .ts_shift = { 759441f7502SMax Filippov [XMIT_SZ_8BIT] = 0, 760441f7502SMax Filippov [XMIT_SZ_16BIT] = 1, 761441f7502SMax Filippov [XMIT_SZ_32BIT] = 2, 762441f7502SMax Filippov }, 763441f7502SMax Filippov .num_hw_channels = 44, 764441f7502SMax Filippov }; 765441f7502SMax Filippov 766441f7502SMax Filippov static struct resource hpb_dmae_resources[] __initdata = { 767441f7502SMax Filippov /* Channel registers */ 768441f7502SMax Filippov DEFINE_RES_MEM(0xffc08000, 0x1000), 769441f7502SMax Filippov /* Common registers */ 770441f7502SMax Filippov DEFINE_RES_MEM(0xffc09000, 0x170), 771441f7502SMax Filippov /* Asynchronous reset registers */ 772441f7502SMax Filippov DEFINE_RES_MEM(0xffc00300, 4), 773441f7502SMax Filippov /* Asynchronous mode registers */ 774441f7502SMax Filippov DEFINE_RES_MEM(0xffc00400, 4), 775441f7502SMax Filippov /* IRQ for DMA channels */ 776441f7502SMax Filippov DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ), 777441f7502SMax Filippov }; 778441f7502SMax Filippov 779441f7502SMax Filippov static void __init r8a7779_register_hpb_dmae(void) 780441f7502SMax Filippov { 781441f7502SMax Filippov platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, 782441f7502SMax Filippov hpb_dmae_resources, 783441f7502SMax Filippov ARRAY_SIZE(hpb_dmae_resources), 784441f7502SMax Filippov &dma_platform_data, 785441f7502SMax Filippov sizeof(dma_platform_data)); 786441f7502SMax Filippov } 787441f7502SMax Filippov 788916ddc35SSimon Horman static struct platform_device *r8a7779_devices_dt[] __initdata = { 789f411fadeSMagnus Damm &scif0_device, 790f411fadeSMagnus Damm &scif1_device, 791f411fadeSMagnus Damm &scif2_device, 792f411fadeSMagnus Damm &scif3_device, 793f411fadeSMagnus Damm &scif4_device, 794f411fadeSMagnus Damm &scif5_device, 795f411fadeSMagnus Damm &tmu00_device, 796f411fadeSMagnus Damm &tmu01_device, 79710e8d4f6SSimon Horman }; 79810e8d4f6SSimon Horman 7992c8788bfSSergei Shtylyov static struct platform_device *r8a7779_standard_devices[] __initdata = { 800ccc2a27bSKuninori Morimoto &i2c0_device, 801ccc2a27bSKuninori Morimoto &i2c1_device, 802ccc2a27bSKuninori Morimoto &i2c2_device, 803ccc2a27bSKuninori Morimoto &i2c3_device, 804a7b9837cSVladimir Barinov &sata_device, 805f411fadeSMagnus Damm }; 806f411fadeSMagnus Damm 807f411fadeSMagnus Damm void __init r8a7779_add_standard_devices(void) 808f411fadeSMagnus Damm { 8098bac13f5SMagnus Damm #ifdef CONFIG_CACHE_L2X0 8108bac13f5SMagnus Damm /* Early BRESP enable, Shared attribute override enable, 64K*16way */ 811ed7d132aSKuninori Morimoto l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff); 8128bac13f5SMagnus Damm #endif 813a662c082SMagnus Damm r8a7779_pm_init(); 814a662c082SMagnus Damm 81545e5ca57SRafael J. Wysocki r8a7779_init_pm_domains(); 816a662c082SMagnus Damm 817916ddc35SSimon Horman platform_add_devices(r8a7779_devices_dt, 818916ddc35SSimon Horman ARRAY_SIZE(r8a7779_devices_dt)); 8192c8788bfSSergei Shtylyov platform_add_devices(r8a7779_standard_devices, 8202c8788bfSSergei Shtylyov ARRAY_SIZE(r8a7779_standard_devices)); 821441f7502SMax Filippov r8a7779_register_hpb_dmae(); 822f411fadeSMagnus Damm } 823f411fadeSMagnus Damm 824dace48d0SSergei Shtylyov void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) 825dace48d0SSergei Shtylyov { 8264c370abbSSergei Shtylyov platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, 827dace48d0SSergei Shtylyov ether_resources, 828dace48d0SSergei Shtylyov ARRAY_SIZE(ether_resources), 829dace48d0SSergei Shtylyov pdata, sizeof(*pdata)); 830dace48d0SSergei Shtylyov } 831dace48d0SSergei Shtylyov 8324714a025SVladimir Barinov void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata) 8334714a025SVladimir Barinov { 8344714a025SVladimir Barinov BUG_ON(id < 0 || id > 3); 8354714a025SVladimir Barinov 8364714a025SVladimir Barinov vin_info_table[id]->data = pdata; 8374714a025SVladimir Barinov vin_info_table[id]->size_data = sizeof(*pdata); 8384714a025SVladimir Barinov 8394714a025SVladimir Barinov platform_device_register_full(vin_info_table[id]); 8404714a025SVladimir Barinov } 8414714a025SVladimir Barinov 842b759bd11SMagnus Damm /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 843b759bd11SMagnus Damm void __init __weak r8a7779_register_twd(void) { } 844b759bd11SMagnus Damm 8456bb27d73SStephen Warren void __init r8a7779_earlytimer_init(void) 846df27a2d8SMagnus Damm { 847df27a2d8SMagnus Damm r8a7779_clock_init(); 848b759bd11SMagnus Damm r8a7779_register_twd(); 8497658ea2fSSimon Horman shmobile_earlytimer_init(); 850df27a2d8SMagnus Damm } 851df27a2d8SMagnus Damm 852f411fadeSMagnus Damm void __init r8a7779_add_early_devices(void) 853f411fadeSMagnus Damm { 854916ddc35SSimon Horman early_platform_add_devices(r8a7779_devices_dt, 855916ddc35SSimon Horman ARRAY_SIZE(r8a7779_devices_dt)); 8563e353b87SMagnus Damm 8573e353b87SMagnus Damm /* Early serial console setup is not included here due to 8583e353b87SMagnus Damm * memory map collisions. The SCIF serial ports in r8a7779 8593e353b87SMagnus Damm * are difficult to entity map 1:1 due to collision with the 8603e353b87SMagnus Damm * virtual memory range used by the coherent DMA code on ARM. 8613e353b87SMagnus Damm * 8623e353b87SMagnus Damm * Anyone wanting to debug early can remove UPF_IOREMAP from 8633e353b87SMagnus Damm * the sh-sci serial console platform data, adjust mapbase 8643e353b87SMagnus Damm * to a static M:N virt:phys mapping that needs to be added to 8653e353b87SMagnus Damm * the mappings passed with iotable_init() above. 8663e353b87SMagnus Damm * 8673e353b87SMagnus Damm * Then add a call to shmobile_setup_console() from this function. 8683e353b87SMagnus Damm * 8693e353b87SMagnus Damm * As a final step pass earlyprint=sh-sci.2,115200 on the kernel 8703e353b87SMagnus Damm * command line in case of the marzen board. 8713e353b87SMagnus Damm */ 872f411fadeSMagnus Damm } 87310e8d4f6SSimon Horman 8742c8788bfSSergei Shtylyov static struct platform_device *r8a7779_late_devices[] __initdata = { 8752c8788bfSSergei Shtylyov &ehci0_device, 8762c8788bfSSergei Shtylyov &ehci1_device, 8772c8788bfSSergei Shtylyov &ohci0_device, 8782c8788bfSSergei Shtylyov &ohci1_device, 8792c8788bfSSergei Shtylyov }; 8802c8788bfSSergei Shtylyov 8812c8788bfSSergei Shtylyov void __init r8a7779_init_late(void) 8822c8788bfSSergei Shtylyov { 8832c8788bfSSergei Shtylyov /* get USB PHY */ 8842c8788bfSSergei Shtylyov phy = usb_get_phy(USB_PHY_TYPE_USB2); 8852c8788bfSSergei Shtylyov 8862c8788bfSSergei Shtylyov shmobile_init_late(); 8872c8788bfSSergei Shtylyov platform_add_devices(r8a7779_late_devices, 8882c8788bfSSergei Shtylyov ARRAY_SIZE(r8a7779_late_devices)); 8892c8788bfSSergei Shtylyov } 8902c8788bfSSergei Shtylyov 89110e8d4f6SSimon Horman #ifdef CONFIG_USE_OF 8925b3859d7SKuninori Morimoto static int r8a7779_set_wake(struct irq_data *data, unsigned int on) 8935b3859d7SKuninori Morimoto { 8945b3859d7SKuninori Morimoto return 0; /* always allow wakeup */ 8955b3859d7SKuninori Morimoto } 8965b3859d7SKuninori Morimoto 8975b3859d7SKuninori Morimoto void __init r8a7779_init_irq_dt(void) 8985b3859d7SKuninori Morimoto { 8995b3859d7SKuninori Morimoto gic_arch_extn.irq_set_wake = r8a7779_set_wake; 9005b3859d7SKuninori Morimoto 9015b3859d7SKuninori Morimoto irqchip_init(); 9025b3859d7SKuninori Morimoto 9035b3859d7SKuninori Morimoto /* route all interrupts to ARM */ 9045b3859d7SKuninori Morimoto __raw_writel(0xffffffff, INT2NTSR0); 9055b3859d7SKuninori Morimoto __raw_writel(0x3fffffff, INT2NTSR1); 9065b3859d7SKuninori Morimoto 9075b3859d7SKuninori Morimoto /* unmask all known interrupts in INTCS2 */ 9085b3859d7SKuninori Morimoto __raw_writel(0xfffffff0, INT2SMSKCR0); 9095b3859d7SKuninori Morimoto __raw_writel(0xfff7ffff, INT2SMSKCR1); 9105b3859d7SKuninori Morimoto __raw_writel(0xfffbffdf, INT2SMSKCR2); 9115b3859d7SKuninori Morimoto __raw_writel(0xbffffffc, INT2SMSKCR3); 9125b3859d7SKuninori Morimoto __raw_writel(0x003fee3f, INT2SMSKCR4); 9135b3859d7SKuninori Morimoto } 9145b3859d7SKuninori Morimoto 915916ddc35SSimon Horman void __init r8a7779_init_delay(void) 91610e8d4f6SSimon Horman { 91710e8d4f6SSimon Horman shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ 91810e8d4f6SSimon Horman } 91910e8d4f6SSimon Horman 92010e8d4f6SSimon Horman void __init r8a7779_add_standard_devices_dt(void) 92110e8d4f6SSimon Horman { 92210e8d4f6SSimon Horman /* clocks are setup late during boot in the case of DT */ 92310e8d4f6SSimon Horman r8a7779_clock_init(); 92410e8d4f6SSimon Horman 925916ddc35SSimon Horman platform_add_devices(r8a7779_devices_dt, 926916ddc35SSimon Horman ARRAY_SIZE(r8a7779_devices_dt)); 92741b0156cSMagnus Damm of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 92810e8d4f6SSimon Horman } 92910e8d4f6SSimon Horman 93010e8d4f6SSimon Horman static const char *r8a7779_compat_dt[] __initdata = { 93110e8d4f6SSimon Horman "renesas,r8a7779", 93210e8d4f6SSimon Horman NULL, 93310e8d4f6SSimon Horman }; 93410e8d4f6SSimon Horman 935abe0e14bSKuninori Morimoto DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") 93610e8d4f6SSimon Horman .map_io = r8a7779_map_io, 937916ddc35SSimon Horman .init_early = r8a7779_init_delay, 93810e8d4f6SSimon Horman .nr_irqs = NR_IRQS_LEGACY, 93910e8d4f6SSimon Horman .init_irq = r8a7779_init_irq_dt, 94010e8d4f6SSimon Horman .init_machine = r8a7779_add_standard_devices_dt, 9412c8788bfSSergei Shtylyov .init_late = r8a7779_init_late, 94210e8d4f6SSimon Horman .dt_compat = r8a7779_compat_dt, 94310e8d4f6SSimon Horman MACHINE_END 94410e8d4f6SSimon Horman #endif /* CONFIG_USE_OF */ 945