1 /*
2  * r8a7778 processor support
3  *
4  * Copyright (C) 2013  Renesas Solutions Corp.
5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6  * Copyright (C) 2013  Cogent Embedded, Inc.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; version 2 of the License.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
20  */
21 
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/irqchip/arm-gic.h>
25 #include <linux/of.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_data/gpio-rcar.h>
28 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
29 #include <linux/platform_device.h>
30 #include <linux/irqchip.h>
31 #include <linux/serial_sci.h>
32 #include <linux/sh_timer.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/usb/phy.h>
35 #include <linux/usb/hcd.h>
36 #include <linux/usb/ehci_pdriver.h>
37 #include <linux/usb/ohci_pdriver.h>
38 #include <linux/dma-mapping.h>
39 #include <mach/irqs.h>
40 #include <mach/r8a7778.h>
41 #include <mach/common.h>
42 #include <asm/mach/arch.h>
43 #include <asm/hardware/cache-l2x0.h>
44 
45 /* SCIF */
46 #define SCIF_INFO(baseaddr, irq)				\
47 {								\
48 	.mapbase	= baseaddr,				\
49 	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,	\
50 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,	\
51 	.scbrr_algo_id	= SCBRR_ALGO_2,				\
52 	.type		= PORT_SCIF,				\
53 	.irqs		= SCIx_IRQ_MUXED(irq),			\
54 }
55 
56 static struct plat_sci_port scif_platform_data[] __initdata = {
57 	SCIF_INFO(0xffe40000, gic_iid(0x66)),
58 	SCIF_INFO(0xffe41000, gic_iid(0x67)),
59 	SCIF_INFO(0xffe42000, gic_iid(0x68)),
60 	SCIF_INFO(0xffe43000, gic_iid(0x69)),
61 	SCIF_INFO(0xffe44000, gic_iid(0x6a)),
62 	SCIF_INFO(0xffe45000, gic_iid(0x6b)),
63 };
64 
65 /* TMU */
66 static struct resource sh_tmu0_resources[] __initdata = {
67 	DEFINE_RES_MEM(0xffd80008, 12),
68 	DEFINE_RES_IRQ(gic_iid(0x40)),
69 };
70 
71 static struct sh_timer_config sh_tmu0_platform_data __initdata = {
72 	.name			= "TMU00",
73 	.channel_offset		= 0x4,
74 	.timer_bit		= 0,
75 	.clockevent_rating	= 200,
76 };
77 
78 static struct resource sh_tmu1_resources[] __initdata = {
79 	DEFINE_RES_MEM(0xffd80014, 12),
80 	DEFINE_RES_IRQ(gic_iid(0x41)),
81 };
82 
83 static struct sh_timer_config sh_tmu1_platform_data __initdata = {
84 	.name			= "TMU01",
85 	.channel_offset		= 0x10,
86 	.timer_bit		= 1,
87 	.clocksource_rating	= 200,
88 };
89 
90 #define r8a7778_register_tmu(idx)			\
91 	platform_device_register_resndata(		\
92 		&platform_bus, "sh_tmu", idx,		\
93 		sh_tmu##idx##_resources,		\
94 		ARRAY_SIZE(sh_tmu##idx##_resources),	\
95 		&sh_tmu##idx##_platform_data,		\
96 		sizeof(sh_tmu##idx##_platform_data))
97 
98 /* USB */
99 static struct usb_phy *phy;
100 
101 static int usb_power_on(struct platform_device *pdev)
102 {
103 	if (IS_ERR(phy))
104 		return PTR_ERR(phy);
105 
106 	pm_runtime_enable(&pdev->dev);
107 	pm_runtime_get_sync(&pdev->dev);
108 
109 	usb_phy_init(phy);
110 
111 	return 0;
112 }
113 
114 static void usb_power_off(struct platform_device *pdev)
115 {
116 	if (IS_ERR(phy))
117 		return;
118 
119 	usb_phy_shutdown(phy);
120 
121 	pm_runtime_put_sync(&pdev->dev);
122 	pm_runtime_disable(&pdev->dev);
123 }
124 
125 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
126 {
127 	/*
128 	 * Below are recommended values from the datasheet;
129 	 * see [USB :: Setting of EHCI Internal Buffer].
130 	 */
131 	/* EHCI IP internal buffer setting */
132 	iowrite32(0x00ff0040, hcd->regs + 0x0094);
133 	/* EHCI IP internal buffer enable */
134 	iowrite32(0x00000001, hcd->regs + 0x009C);
135 
136 	return 0;
137 }
138 
139 static struct usb_ehci_pdata ehci_pdata __initdata = {
140 	.power_on	= usb_power_on,
141 	.power_off	= usb_power_off,
142 	.power_suspend	= usb_power_off,
143 	.pre_setup	= ehci_init_internal_buffer,
144 };
145 
146 static struct resource ehci_resources[] __initdata = {
147 	DEFINE_RES_MEM(0xffe70000, 0x400),
148 	DEFINE_RES_IRQ(gic_iid(0x4c)),
149 };
150 
151 static struct usb_ohci_pdata ohci_pdata __initdata = {
152 	.power_on	= usb_power_on,
153 	.power_off	= usb_power_off,
154 	.power_suspend	= usb_power_off,
155 };
156 
157 static struct resource ohci_resources[] __initdata = {
158 	DEFINE_RES_MEM(0xffe70400, 0x400),
159 	DEFINE_RES_IRQ(gic_iid(0x4c)),
160 };
161 
162 #define USB_PLATFORM_INFO(hci)					\
163 static struct platform_device_info hci##_info __initdata = {	\
164 	.parent		= &platform_bus,			\
165 	.name		= #hci "-platform",			\
166 	.id		= -1,					\
167 	.res		= hci##_resources,			\
168 	.num_res	= ARRAY_SIZE(hci##_resources),		\
169 	.data		= &hci##_pdata,				\
170 	.size_data	= sizeof(hci##_pdata),			\
171 	.dma_mask	= DMA_BIT_MASK(32),			\
172 }
173 
174 USB_PLATFORM_INFO(ehci);
175 USB_PLATFORM_INFO(ohci);
176 
177 /* Ether */
178 static struct resource ether_resources[] __initdata = {
179 	DEFINE_RES_MEM(0xfde00000, 0x400),
180 	DEFINE_RES_IRQ(gic_iid(0x89)),
181 };
182 
183 void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
184 {
185 	platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
186 					  ether_resources,
187 					  ARRAY_SIZE(ether_resources),
188 					  pdata, sizeof(*pdata));
189 }
190 
191 /* PFC/GPIO */
192 static struct resource pfc_resources[] __initdata = {
193 	DEFINE_RES_MEM(0xfffc0000, 0x118),
194 };
195 
196 #define R8A7778_GPIO(idx)						\
197 static struct resource r8a7778_gpio##idx##_resources[] __initdata = {	\
198 	DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),		\
199 	DEFINE_RES_IRQ(gic_iid(0x87)),					\
200 };									\
201 									\
202 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
203 	.gpio_base	= 32 * (idx),					\
204 	.irq_base	= GPIO_IRQ_BASE(idx),				\
205 	.number_of_pins	= 32,						\
206 	.pctl_name	= "pfc-r8a7778",				\
207 }
208 
209 R8A7778_GPIO(0);
210 R8A7778_GPIO(1);
211 R8A7778_GPIO(2);
212 R8A7778_GPIO(3);
213 R8A7778_GPIO(4);
214 
215 #define r8a7778_register_gpio(idx)				\
216 	platform_device_register_resndata(			\
217 		&platform_bus, "gpio_rcar", idx,		\
218 		r8a7778_gpio##idx##_resources,			\
219 		ARRAY_SIZE(r8a7778_gpio##idx##_resources),	\
220 		&r8a7778_gpio##idx##_platform_data,		\
221 		sizeof(r8a7778_gpio##idx##_platform_data))
222 
223 void __init r8a7778_pinmux_init(void)
224 {
225 	platform_device_register_simple(
226 		"pfc-r8a7778", -1,
227 		pfc_resources,
228 		ARRAY_SIZE(pfc_resources));
229 
230 	r8a7778_register_gpio(0);
231 	r8a7778_register_gpio(1);
232 	r8a7778_register_gpio(2);
233 	r8a7778_register_gpio(3);
234 	r8a7778_register_gpio(4);
235 };
236 
237 /* I2C */
238 static struct resource i2c_resources[] __initdata = {
239 	/* I2C0 */
240 	DEFINE_RES_MEM(0xffc70000, 0x1000),
241 	DEFINE_RES_IRQ(gic_iid(0x63)),
242 	/* I2C1 */
243 	DEFINE_RES_MEM(0xffc71000, 0x1000),
244 	DEFINE_RES_IRQ(gic_iid(0x6e)),
245 	/* I2C2 */
246 	DEFINE_RES_MEM(0xffc72000, 0x1000),
247 	DEFINE_RES_IRQ(gic_iid(0x6c)),
248 	/* I2C3 */
249 	DEFINE_RES_MEM(0xffc73000, 0x1000),
250 	DEFINE_RES_IRQ(gic_iid(0x6d)),
251 };
252 
253 static void __init r8a7778_register_i2c(int id)
254 {
255 	BUG_ON(id < 0 || id > 3);
256 
257 	platform_device_register_simple(
258 		"i2c-rcar", id,
259 		i2c_resources + (2 * id), 2);
260 }
261 
262 /* HSPI */
263 static struct resource hspi_resources[] __initdata = {
264 	/* HSPI0 */
265 	DEFINE_RES_MEM(0xfffc7000, 0x18),
266 	DEFINE_RES_IRQ(gic_iid(0x5f)),
267 	/* HSPI1 */
268 	DEFINE_RES_MEM(0xfffc8000, 0x18),
269 	DEFINE_RES_IRQ(gic_iid(0x74)),
270 	/* HSPI2 */
271 	DEFINE_RES_MEM(0xfffc6000, 0x18),
272 	DEFINE_RES_IRQ(gic_iid(0x75)),
273 };
274 
275 void __init r8a7778_register_hspi(int id)
276 {
277 	BUG_ON(id < 0 || id > 2);
278 
279 	platform_device_register_simple(
280 		"sh-hspi", id,
281 		hspi_resources + (2 * id), 2);
282 }
283 
284 /* VIN */
285 #define R8A7778_VIN(idx)						\
286 static struct resource vin##idx##_resources[] __initdata = {		\
287 	DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000),		\
288 	DEFINE_RES_IRQ(gic_iid(0x5a)),					\
289 };									\
290 									\
291 static struct platform_device_info vin##idx##_info __initdata = {	\
292 	.parent		= &platform_bus,				\
293 	.name		= "r8a7778-vin",				\
294 	.id		= idx,						\
295 	.res		= vin##idx##_resources,				\
296 	.num_res	= ARRAY_SIZE(vin##idx##_resources),		\
297 	.dma_mask	= DMA_BIT_MASK(32),				\
298 }
299 
300 R8A7778_VIN(0);
301 R8A7778_VIN(1);
302 
303 static struct platform_device_info *vin_info_table[] __initdata = {
304 	&vin0_info,
305 	&vin1_info,
306 };
307 
308 void __init r8a7778_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
309 {
310 	BUG_ON(id < 0 || id > 1);
311 
312 	vin_info_table[id]->data = pdata;
313 	vin_info_table[id]->size_data = sizeof(*pdata);
314 
315 	platform_device_register_full(vin_info_table[id]);
316 }
317 
318 void __init r8a7778_add_dt_devices(void)
319 {
320 	int i;
321 
322 #ifdef CONFIG_CACHE_L2X0
323 	void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
324 	if (base) {
325 		/*
326 		 * Early BRESP enable, Shared attribute override enable, 64K*16way
327 		 * don't call iounmap(base)
328 		 */
329 		l2x0_init(base, 0x40470000, 0x82000fff);
330 	}
331 #endif
332 
333 	for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
334 		platform_device_register_data(&platform_bus, "sh-sci", i,
335 					      &scif_platform_data[i],
336 					      sizeof(struct plat_sci_port));
337 
338 	r8a7778_register_tmu(0);
339 	r8a7778_register_tmu(1);
340 }
341 
342 void __init r8a7778_add_standard_devices(void)
343 {
344 	r8a7778_add_dt_devices();
345 	r8a7778_register_i2c(0);
346 	r8a7778_register_i2c(1);
347 	r8a7778_register_i2c(2);
348 	r8a7778_register_i2c(3);
349 	r8a7778_register_hspi(0);
350 	r8a7778_register_hspi(1);
351 	r8a7778_register_hspi(2);
352 }
353 
354 void __init r8a7778_init_late(void)
355 {
356 	phy = usb_get_phy(USB_PHY_TYPE_USB2);
357 
358 	platform_device_register_full(&ehci_info);
359 	platform_device_register_full(&ohci_info);
360 }
361 
362 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
363 	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
364 	.sense_bitfield_width = 2,
365 };
366 
367 static struct resource irqpin_resources[] __initdata = {
368 	DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
369 	DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
370 	DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
371 	DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
372 	DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
373 	DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
374 	DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
375 	DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
376 	DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
377 };
378 
379 void __init r8a7778_init_irq_extpin(int irlm)
380 {
381 	void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
382 	unsigned long tmp;
383 
384 	if (!icr0) {
385 		pr_warn("r8a7778: unable to setup external irq pin mode\n");
386 		return;
387 	}
388 
389 	tmp = ioread32(icr0);
390 	if (irlm)
391 		tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
392 	else
393 		tmp &= ~(1 << 23); /* IRL mode - not supported */
394 	tmp |= (1 << 21); /* LVLMODE = 1 */
395 	iowrite32(tmp, icr0);
396 	iounmap(icr0);
397 
398 	if (irlm)
399 		platform_device_register_resndata(
400 			&platform_bus, "renesas_intc_irqpin", -1,
401 			irqpin_resources, ARRAY_SIZE(irqpin_resources),
402 			&irqpin_platform_data, sizeof(irqpin_platform_data));
403 }
404 
405 void __init r8a7778_init_delay(void)
406 {
407 	shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
408 }
409 
410 #ifdef CONFIG_USE_OF
411 #define INT2SMSKCR0	0x82288 /* 0xfe782288 */
412 #define INT2SMSKCR1	0x8228c /* 0xfe78228c */
413 
414 #define INT2NTSR0	0x00018 /* 0xfe700018 */
415 #define INT2NTSR1	0x0002c /* 0xfe70002c */
416 void __init r8a7778_init_irq_dt(void)
417 {
418 	void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
419 
420 	BUG_ON(!base);
421 
422 	irqchip_init();
423 
424 	/* route all interrupts to ARM */
425 	__raw_writel(0x73ffffff, base + INT2NTSR0);
426 	__raw_writel(0xffffffff, base + INT2NTSR1);
427 
428 	/* unmask all known interrupts in INTCS2 */
429 	__raw_writel(0x08330773, base + INT2SMSKCR0);
430 	__raw_writel(0x00311110, base + INT2SMSKCR1);
431 
432 	iounmap(base);
433 }
434 
435 static const char *r8a7778_compat_dt[] __initdata = {
436 	"renesas,r8a7778",
437 	NULL,
438 };
439 
440 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
441 	.init_early	= r8a7778_init_delay,
442 	.init_irq	= r8a7778_init_irq_dt,
443 	.dt_compat	= r8a7778_compat_dt,
444 	.init_late      = r8a7778_init_late,
445 MACHINE_END
446 
447 #endif /* CONFIG_USE_OF */
448