1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/irqchip/arm-gic.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_data/gpio-rcar.h> 28 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 29 #include <linux/platform_device.h> 30 #include <linux/irqchip.h> 31 #include <linux/serial_sci.h> 32 #include <linux/sh_timer.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/usb/phy.h> 35 #include <linux/usb/hcd.h> 36 #include <linux/usb/ehci_pdriver.h> 37 #include <linux/usb/ohci_pdriver.h> 38 #include <linux/dma-mapping.h> 39 #include <mach/irqs.h> 40 #include <mach/r8a7778.h> 41 #include <mach/common.h> 42 #include <asm/mach/arch.h> 43 #include <asm/hardware/cache-l2x0.h> 44 45 /* SCIF */ 46 #define SCIF_INFO(baseaddr, irq) \ 47 { \ 48 .mapbase = baseaddr, \ 49 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 50 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 51 .scbrr_algo_id = SCBRR_ALGO_2, \ 52 .type = PORT_SCIF, \ 53 .irqs = SCIx_IRQ_MUXED(irq), \ 54 } 55 56 static struct plat_sci_port scif_platform_data[] __initdata = { 57 SCIF_INFO(0xffe40000, gic_iid(0x66)), 58 SCIF_INFO(0xffe41000, gic_iid(0x67)), 59 SCIF_INFO(0xffe42000, gic_iid(0x68)), 60 SCIF_INFO(0xffe43000, gic_iid(0x69)), 61 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 62 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 63 }; 64 65 /* TMU */ 66 static struct resource sh_tmu0_resources[] __initdata = { 67 DEFINE_RES_MEM(0xffd80008, 12), 68 DEFINE_RES_IRQ(gic_iid(0x40)), 69 }; 70 71 static struct sh_timer_config sh_tmu0_platform_data __initdata = { 72 .name = "TMU00", 73 .channel_offset = 0x4, 74 .timer_bit = 0, 75 .clockevent_rating = 200, 76 }; 77 78 static struct resource sh_tmu1_resources[] __initdata = { 79 DEFINE_RES_MEM(0xffd80014, 12), 80 DEFINE_RES_IRQ(gic_iid(0x41)), 81 }; 82 83 static struct sh_timer_config sh_tmu1_platform_data __initdata = { 84 .name = "TMU01", 85 .channel_offset = 0x10, 86 .timer_bit = 1, 87 .clocksource_rating = 200, 88 }; 89 90 #define r8a7778_register_tmu(idx) \ 91 platform_device_register_resndata( \ 92 &platform_bus, "sh_tmu", idx, \ 93 sh_tmu##idx##_resources, \ 94 ARRAY_SIZE(sh_tmu##idx##_resources), \ 95 &sh_tmu##idx##_platform_data, \ 96 sizeof(sh_tmu##idx##_platform_data)) 97 98 int r8a7778_usb_phy_power(bool enable) 99 { 100 static struct usb_phy *phy = NULL; 101 int ret = 0; 102 103 if (!phy) 104 phy = usb_get_phy(USB_PHY_TYPE_USB2); 105 106 if (IS_ERR(phy)) { 107 pr_err("kernel doesn't have usb phy driver\n"); 108 return PTR_ERR(phy); 109 } 110 111 if (enable) 112 ret = usb_phy_init(phy); 113 else 114 usb_phy_shutdown(phy); 115 116 return ret; 117 } 118 119 /* USB */ 120 static int usb_power_on(struct platform_device *pdev) 121 { 122 int ret = r8a7778_usb_phy_power(true); 123 124 if (ret) 125 return ret; 126 127 pm_runtime_enable(&pdev->dev); 128 pm_runtime_get_sync(&pdev->dev); 129 130 return 0; 131 } 132 133 static void usb_power_off(struct platform_device *pdev) 134 { 135 if (r8a7778_usb_phy_power(false)) 136 return; 137 138 pm_runtime_put_sync(&pdev->dev); 139 pm_runtime_disable(&pdev->dev); 140 } 141 142 static int ehci_init_internal_buffer(struct usb_hcd *hcd) 143 { 144 /* 145 * Below are recommended values from the datasheet; 146 * see [USB :: Setting of EHCI Internal Buffer]. 147 */ 148 /* EHCI IP internal buffer setting */ 149 iowrite32(0x00ff0040, hcd->regs + 0x0094); 150 /* EHCI IP internal buffer enable */ 151 iowrite32(0x00000001, hcd->regs + 0x009C); 152 153 return 0; 154 } 155 156 static struct usb_ehci_pdata ehci_pdata __initdata = { 157 .power_on = usb_power_on, 158 .power_off = usb_power_off, 159 .power_suspend = usb_power_off, 160 .pre_setup = ehci_init_internal_buffer, 161 }; 162 163 static struct resource ehci_resources[] __initdata = { 164 DEFINE_RES_MEM(0xffe70000, 0x400), 165 DEFINE_RES_IRQ(gic_iid(0x4c)), 166 }; 167 168 static struct usb_ohci_pdata ohci_pdata __initdata = { 169 .power_on = usb_power_on, 170 .power_off = usb_power_off, 171 .power_suspend = usb_power_off, 172 }; 173 174 static struct resource ohci_resources[] __initdata = { 175 DEFINE_RES_MEM(0xffe70400, 0x400), 176 DEFINE_RES_IRQ(gic_iid(0x4c)), 177 }; 178 179 #define USB_PLATFORM_INFO(hci) \ 180 static struct platform_device_info hci##_info __initdata = { \ 181 .parent = &platform_bus, \ 182 .name = #hci "-platform", \ 183 .id = -1, \ 184 .res = hci##_resources, \ 185 .num_res = ARRAY_SIZE(hci##_resources), \ 186 .data = &hci##_pdata, \ 187 .size_data = sizeof(hci##_pdata), \ 188 .dma_mask = DMA_BIT_MASK(32), \ 189 } 190 191 USB_PLATFORM_INFO(ehci); 192 USB_PLATFORM_INFO(ohci); 193 194 /* Ether */ 195 static struct resource ether_resources[] __initdata = { 196 DEFINE_RES_MEM(0xfde00000, 0x400), 197 DEFINE_RES_IRQ(gic_iid(0x89)), 198 }; 199 200 void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata) 201 { 202 platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, 203 ether_resources, 204 ARRAY_SIZE(ether_resources), 205 pdata, sizeof(*pdata)); 206 } 207 208 /* PFC/GPIO */ 209 static struct resource pfc_resources[] __initdata = { 210 DEFINE_RES_MEM(0xfffc0000, 0x118), 211 }; 212 213 #define R8A7778_GPIO(idx) \ 214 static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \ 215 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 216 DEFINE_RES_IRQ(gic_iid(0x87)), \ 217 }; \ 218 \ 219 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \ 220 .gpio_base = 32 * (idx), \ 221 .irq_base = GPIO_IRQ_BASE(idx), \ 222 .number_of_pins = 32, \ 223 .pctl_name = "pfc-r8a7778", \ 224 } 225 226 R8A7778_GPIO(0); 227 R8A7778_GPIO(1); 228 R8A7778_GPIO(2); 229 R8A7778_GPIO(3); 230 R8A7778_GPIO(4); 231 232 #define r8a7778_register_gpio(idx) \ 233 platform_device_register_resndata( \ 234 &platform_bus, "gpio_rcar", idx, \ 235 r8a7778_gpio##idx##_resources, \ 236 ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ 237 &r8a7778_gpio##idx##_platform_data, \ 238 sizeof(r8a7778_gpio##idx##_platform_data)) 239 240 void __init r8a7778_pinmux_init(void) 241 { 242 platform_device_register_simple( 243 "pfc-r8a7778", -1, 244 pfc_resources, 245 ARRAY_SIZE(pfc_resources)); 246 247 r8a7778_register_gpio(0); 248 r8a7778_register_gpio(1); 249 r8a7778_register_gpio(2); 250 r8a7778_register_gpio(3); 251 r8a7778_register_gpio(4); 252 }; 253 254 /* I2C */ 255 static struct resource i2c_resources[] __initdata = { 256 /* I2C0 */ 257 DEFINE_RES_MEM(0xffc70000, 0x1000), 258 DEFINE_RES_IRQ(gic_iid(0x63)), 259 /* I2C1 */ 260 DEFINE_RES_MEM(0xffc71000, 0x1000), 261 DEFINE_RES_IRQ(gic_iid(0x6e)), 262 /* I2C2 */ 263 DEFINE_RES_MEM(0xffc72000, 0x1000), 264 DEFINE_RES_IRQ(gic_iid(0x6c)), 265 /* I2C3 */ 266 DEFINE_RES_MEM(0xffc73000, 0x1000), 267 DEFINE_RES_IRQ(gic_iid(0x6d)), 268 }; 269 270 static void __init r8a7778_register_i2c(int id) 271 { 272 BUG_ON(id < 0 || id > 3); 273 274 platform_device_register_simple( 275 "i2c-rcar", id, 276 i2c_resources + (2 * id), 2); 277 } 278 279 /* HSPI */ 280 static struct resource hspi_resources[] __initdata = { 281 /* HSPI0 */ 282 DEFINE_RES_MEM(0xfffc7000, 0x18), 283 DEFINE_RES_IRQ(gic_iid(0x5f)), 284 /* HSPI1 */ 285 DEFINE_RES_MEM(0xfffc8000, 0x18), 286 DEFINE_RES_IRQ(gic_iid(0x74)), 287 /* HSPI2 */ 288 DEFINE_RES_MEM(0xfffc6000, 0x18), 289 DEFINE_RES_IRQ(gic_iid(0x75)), 290 }; 291 292 void __init r8a7778_register_hspi(int id) 293 { 294 BUG_ON(id < 0 || id > 2); 295 296 platform_device_register_simple( 297 "sh-hspi", id, 298 hspi_resources + (2 * id), 2); 299 } 300 301 /* VIN */ 302 #define R8A7778_VIN(idx) \ 303 static struct resource vin##idx##_resources[] __initdata = { \ 304 DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ 305 DEFINE_RES_IRQ(gic_iid(0x5a)), \ 306 }; \ 307 \ 308 static struct platform_device_info vin##idx##_info __initdata = { \ 309 .parent = &platform_bus, \ 310 .name = "r8a7778-vin", \ 311 .id = idx, \ 312 .res = vin##idx##_resources, \ 313 .num_res = ARRAY_SIZE(vin##idx##_resources), \ 314 .dma_mask = DMA_BIT_MASK(32), \ 315 } 316 317 R8A7778_VIN(0); 318 R8A7778_VIN(1); 319 320 static struct platform_device_info *vin_info_table[] __initdata = { 321 &vin0_info, 322 &vin1_info, 323 }; 324 325 void __init r8a7778_add_vin_device(int id, struct rcar_vin_platform_data *pdata) 326 { 327 BUG_ON(id < 0 || id > 1); 328 329 vin_info_table[id]->data = pdata; 330 vin_info_table[id]->size_data = sizeof(*pdata); 331 332 platform_device_register_full(vin_info_table[id]); 333 } 334 335 void __init r8a7778_add_dt_devices(void) 336 { 337 int i; 338 339 #ifdef CONFIG_CACHE_L2X0 340 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 341 if (base) { 342 /* 343 * Early BRESP enable, Shared attribute override enable, 64K*16way 344 * don't call iounmap(base) 345 */ 346 l2x0_init(base, 0x40470000, 0x82000fff); 347 } 348 #endif 349 350 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 351 platform_device_register_data(&platform_bus, "sh-sci", i, 352 &scif_platform_data[i], 353 sizeof(struct plat_sci_port)); 354 355 r8a7778_register_tmu(0); 356 r8a7778_register_tmu(1); 357 } 358 359 void __init r8a7778_add_standard_devices(void) 360 { 361 r8a7778_add_dt_devices(); 362 r8a7778_register_i2c(0); 363 r8a7778_register_i2c(1); 364 r8a7778_register_i2c(2); 365 r8a7778_register_i2c(3); 366 r8a7778_register_hspi(0); 367 r8a7778_register_hspi(1); 368 r8a7778_register_hspi(2); 369 } 370 371 void __init r8a7778_init_late(void) 372 { 373 platform_device_register_full(&ehci_info); 374 platform_device_register_full(&ohci_info); 375 } 376 377 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { 378 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 379 .sense_bitfield_width = 2, 380 }; 381 382 static struct resource irqpin_resources[] __initdata = { 383 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 384 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 385 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 386 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 387 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 388 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 389 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 390 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 391 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 392 }; 393 394 void __init r8a7778_init_irq_extpin(int irlm) 395 { 396 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 397 unsigned long tmp; 398 399 if (!icr0) { 400 pr_warn("r8a7778: unable to setup external irq pin mode\n"); 401 return; 402 } 403 404 tmp = ioread32(icr0); 405 if (irlm) 406 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 407 else 408 tmp &= ~(1 << 23); /* IRL mode - not supported */ 409 tmp |= (1 << 21); /* LVLMODE = 1 */ 410 iowrite32(tmp, icr0); 411 iounmap(icr0); 412 413 if (irlm) 414 platform_device_register_resndata( 415 &platform_bus, "renesas_intc_irqpin", -1, 416 irqpin_resources, ARRAY_SIZE(irqpin_resources), 417 &irqpin_platform_data, sizeof(irqpin_platform_data)); 418 } 419 420 void __init r8a7778_init_delay(void) 421 { 422 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 423 } 424 425 #ifdef CONFIG_USE_OF 426 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 427 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 428 429 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 430 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 431 void __init r8a7778_init_irq_dt(void) 432 { 433 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 434 435 BUG_ON(!base); 436 437 irqchip_init(); 438 439 /* route all interrupts to ARM */ 440 __raw_writel(0x73ffffff, base + INT2NTSR0); 441 __raw_writel(0xffffffff, base + INT2NTSR1); 442 443 /* unmask all known interrupts in INTCS2 */ 444 __raw_writel(0x08330773, base + INT2SMSKCR0); 445 __raw_writel(0x00311110, base + INT2SMSKCR1); 446 447 iounmap(base); 448 } 449 450 static const char *r8a7778_compat_dt[] __initdata = { 451 "renesas,r8a7778", 452 NULL, 453 }; 454 455 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 456 .init_early = r8a7778_init_delay, 457 .init_irq = r8a7778_init_irq_dt, 458 .dt_compat = r8a7778_compat_dt, 459 .init_late = r8a7778_init_late, 460 MACHINE_END 461 462 #endif /* CONFIG_USE_OF */ 463