1 /* 2 * r8a7778 processor support 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/io.h> 24 #include <linux/irqchip/arm-gic.h> 25 #include <linux/of.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_data/dma-rcar-hpbdma.h> 28 #include <linux/platform_data/gpio-rcar.h> 29 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 30 #include <linux/platform_device.h> 31 #include <linux/irqchip.h> 32 #include <linux/serial_sci.h> 33 #include <linux/sh_timer.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/usb/phy.h> 36 #include <linux/usb/hcd.h> 37 #include <linux/usb/ehci_pdriver.h> 38 #include <linux/usb/ohci_pdriver.h> 39 #include <linux/dma-mapping.h> 40 #include <mach/irqs.h> 41 #include <mach/r8a7778.h> 42 #include <mach/common.h> 43 #include <asm/mach/arch.h> 44 #include <asm/hardware/cache-l2x0.h> 45 46 /* SCIF */ 47 #define R8A7778_SCIF(index, baseaddr, irq) \ 48 static struct plat_sci_port scif##index##_platform_data = { \ 49 .mapbase = baseaddr, \ 50 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 52 .scbrr_algo_id = SCBRR_ALGO_2, \ 53 .type = PORT_SCIF, \ 54 .irqs = SCIx_IRQ_MUXED(irq), \ 55 } 56 57 R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66)); 58 R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67)); 59 R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68)); 60 R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69)); 61 R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a)); 62 R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b)); 63 64 #define r8a7778_register_scif(index) \ 65 platform_device_register_data(&platform_bus, "sh-sci", index, \ 66 &scif##index##_platform_data, \ 67 sizeof(scif##index##_platform_data)) 68 69 /* TMU */ 70 static struct resource sh_tmu0_resources[] __initdata = { 71 DEFINE_RES_MEM(0xffd80008, 12), 72 DEFINE_RES_IRQ(gic_iid(0x40)), 73 }; 74 75 static struct sh_timer_config sh_tmu0_platform_data __initdata = { 76 .name = "TMU00", 77 .channel_offset = 0x4, 78 .timer_bit = 0, 79 .clockevent_rating = 200, 80 }; 81 82 static struct resource sh_tmu1_resources[] __initdata = { 83 DEFINE_RES_MEM(0xffd80014, 12), 84 DEFINE_RES_IRQ(gic_iid(0x41)), 85 }; 86 87 static struct sh_timer_config sh_tmu1_platform_data __initdata = { 88 .name = "TMU01", 89 .channel_offset = 0x10, 90 .timer_bit = 1, 91 .clocksource_rating = 200, 92 }; 93 94 #define r8a7778_register_tmu(idx) \ 95 platform_device_register_resndata( \ 96 &platform_bus, "sh_tmu", idx, \ 97 sh_tmu##idx##_resources, \ 98 ARRAY_SIZE(sh_tmu##idx##_resources), \ 99 &sh_tmu##idx##_platform_data, \ 100 sizeof(sh_tmu##idx##_platform_data)) 101 102 int r8a7778_usb_phy_power(bool enable) 103 { 104 static struct usb_phy *phy = NULL; 105 int ret = 0; 106 107 if (!phy) 108 phy = usb_get_phy(USB_PHY_TYPE_USB2); 109 110 if (IS_ERR(phy)) { 111 pr_err("kernel doesn't have usb phy driver\n"); 112 return PTR_ERR(phy); 113 } 114 115 if (enable) 116 ret = usb_phy_init(phy); 117 else 118 usb_phy_shutdown(phy); 119 120 return ret; 121 } 122 123 /* USB */ 124 static int usb_power_on(struct platform_device *pdev) 125 { 126 int ret = r8a7778_usb_phy_power(true); 127 128 if (ret) 129 return ret; 130 131 pm_runtime_enable(&pdev->dev); 132 pm_runtime_get_sync(&pdev->dev); 133 134 return 0; 135 } 136 137 static void usb_power_off(struct platform_device *pdev) 138 { 139 if (r8a7778_usb_phy_power(false)) 140 return; 141 142 pm_runtime_put_sync(&pdev->dev); 143 pm_runtime_disable(&pdev->dev); 144 } 145 146 static int ehci_init_internal_buffer(struct usb_hcd *hcd) 147 { 148 /* 149 * Below are recommended values from the datasheet; 150 * see [USB :: Setting of EHCI Internal Buffer]. 151 */ 152 /* EHCI IP internal buffer setting */ 153 iowrite32(0x00ff0040, hcd->regs + 0x0094); 154 /* EHCI IP internal buffer enable */ 155 iowrite32(0x00000001, hcd->regs + 0x009C); 156 157 return 0; 158 } 159 160 static struct usb_ehci_pdata ehci_pdata __initdata = { 161 .power_on = usb_power_on, 162 .power_off = usb_power_off, 163 .power_suspend = usb_power_off, 164 .pre_setup = ehci_init_internal_buffer, 165 }; 166 167 static struct resource ehci_resources[] __initdata = { 168 DEFINE_RES_MEM(0xffe70000, 0x400), 169 DEFINE_RES_IRQ(gic_iid(0x4c)), 170 }; 171 172 static struct usb_ohci_pdata ohci_pdata __initdata = { 173 .power_on = usb_power_on, 174 .power_off = usb_power_off, 175 .power_suspend = usb_power_off, 176 }; 177 178 static struct resource ohci_resources[] __initdata = { 179 DEFINE_RES_MEM(0xffe70400, 0x400), 180 DEFINE_RES_IRQ(gic_iid(0x4c)), 181 }; 182 183 #define USB_PLATFORM_INFO(hci) \ 184 static struct platform_device_info hci##_info __initdata = { \ 185 .parent = &platform_bus, \ 186 .name = #hci "-platform", \ 187 .id = -1, \ 188 .res = hci##_resources, \ 189 .num_res = ARRAY_SIZE(hci##_resources), \ 190 .data = &hci##_pdata, \ 191 .size_data = sizeof(hci##_pdata), \ 192 .dma_mask = DMA_BIT_MASK(32), \ 193 } 194 195 USB_PLATFORM_INFO(ehci); 196 USB_PLATFORM_INFO(ohci); 197 198 /* PFC/GPIO */ 199 static struct resource pfc_resources[] __initdata = { 200 DEFINE_RES_MEM(0xfffc0000, 0x118), 201 }; 202 203 #define R8A7778_GPIO(idx) \ 204 static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \ 205 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 206 DEFINE_RES_IRQ(gic_iid(0x87)), \ 207 }; \ 208 \ 209 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \ 210 .gpio_base = 32 * (idx), \ 211 .irq_base = GPIO_IRQ_BASE(idx), \ 212 .number_of_pins = 32, \ 213 .pctl_name = "pfc-r8a7778", \ 214 } 215 216 R8A7778_GPIO(0); 217 R8A7778_GPIO(1); 218 R8A7778_GPIO(2); 219 R8A7778_GPIO(3); 220 R8A7778_GPIO(4); 221 222 #define r8a7778_register_gpio(idx) \ 223 platform_device_register_resndata( \ 224 &platform_bus, "gpio_rcar", idx, \ 225 r8a7778_gpio##idx##_resources, \ 226 ARRAY_SIZE(r8a7778_gpio##idx##_resources), \ 227 &r8a7778_gpio##idx##_platform_data, \ 228 sizeof(r8a7778_gpio##idx##_platform_data)) 229 230 void __init r8a7778_pinmux_init(void) 231 { 232 platform_device_register_simple( 233 "pfc-r8a7778", -1, 234 pfc_resources, 235 ARRAY_SIZE(pfc_resources)); 236 237 r8a7778_register_gpio(0); 238 r8a7778_register_gpio(1); 239 r8a7778_register_gpio(2); 240 r8a7778_register_gpio(3); 241 r8a7778_register_gpio(4); 242 }; 243 244 /* I2C */ 245 static struct resource i2c_resources[] __initdata = { 246 /* I2C0 */ 247 DEFINE_RES_MEM(0xffc70000, 0x1000), 248 DEFINE_RES_IRQ(gic_iid(0x63)), 249 /* I2C1 */ 250 DEFINE_RES_MEM(0xffc71000, 0x1000), 251 DEFINE_RES_IRQ(gic_iid(0x6e)), 252 /* I2C2 */ 253 DEFINE_RES_MEM(0xffc72000, 0x1000), 254 DEFINE_RES_IRQ(gic_iid(0x6c)), 255 /* I2C3 */ 256 DEFINE_RES_MEM(0xffc73000, 0x1000), 257 DEFINE_RES_IRQ(gic_iid(0x6d)), 258 }; 259 260 static void __init r8a7778_register_i2c(int id) 261 { 262 BUG_ON(id < 0 || id > 3); 263 264 platform_device_register_simple( 265 "i2c-rcar", id, 266 i2c_resources + (2 * id), 2); 267 } 268 269 /* HSPI */ 270 static struct resource hspi_resources[] __initdata = { 271 /* HSPI0 */ 272 DEFINE_RES_MEM(0xfffc7000, 0x18), 273 DEFINE_RES_IRQ(gic_iid(0x5f)), 274 /* HSPI1 */ 275 DEFINE_RES_MEM(0xfffc8000, 0x18), 276 DEFINE_RES_IRQ(gic_iid(0x74)), 277 /* HSPI2 */ 278 DEFINE_RES_MEM(0xfffc6000, 0x18), 279 DEFINE_RES_IRQ(gic_iid(0x75)), 280 }; 281 282 static void __init r8a7778_register_hspi(int id) 283 { 284 BUG_ON(id < 0 || id > 2); 285 286 platform_device_register_simple( 287 "sh-hspi", id, 288 hspi_resources + (2 * id), 2); 289 } 290 291 void __init r8a7778_add_dt_devices(void) 292 { 293 #ifdef CONFIG_CACHE_L2X0 294 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 295 if (base) { 296 /* 297 * Early BRESP enable, Shared attribute override enable, 64K*16way 298 * don't call iounmap(base) 299 */ 300 l2x0_init(base, 0x40470000, 0x82000fff); 301 } 302 #endif 303 304 r8a7778_register_scif(0); 305 r8a7778_register_scif(1); 306 r8a7778_register_scif(2); 307 r8a7778_register_scif(3); 308 r8a7778_register_scif(4); 309 r8a7778_register_scif(5); 310 r8a7778_register_tmu(0); 311 r8a7778_register_tmu(1); 312 } 313 314 /* HPB-DMA */ 315 316 /* Asynchronous mode register (ASYNCMDR) bits */ 317 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */ 318 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */ 319 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */ 320 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */ 321 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ 322 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 323 324 #define HPBDMA_SSI(_id) \ 325 { \ 326 .id = HPBDMA_SLAVE_SSI## _id ##_TX, \ 327 .addr = 0xffd91008 + (_id * 0x40), \ 328 .dcr = HPB_DMAE_DCR_CT | \ 329 HPB_DMAE_DCR_DIP | \ 330 HPB_DMAE_DCR_SPDS_32BIT | \ 331 HPB_DMAE_DCR_DMDL | \ 332 HPB_DMAE_DCR_DPDS_32BIT, \ 333 .port = _id + (_id << 8), \ 334 .dma_ch = (28 + _id), \ 335 }, { \ 336 .id = HPBDMA_SLAVE_SSI## _id ##_RX, \ 337 .addr = 0xffd9100c + (_id * 0x40), \ 338 .dcr = HPB_DMAE_DCR_CT | \ 339 HPB_DMAE_DCR_DIP | \ 340 HPB_DMAE_DCR_SMDL | \ 341 HPB_DMAE_DCR_SPDS_32BIT | \ 342 HPB_DMAE_DCR_DPDS_32BIT, \ 343 .port = _id + (_id << 8), \ 344 .dma_ch = (28 + _id), \ 345 } 346 347 #define HPBDMA_HPBIF(_id) \ 348 { \ 349 .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \ 350 .addr = 0xffda0000 + (_id * 0x1000), \ 351 .dcr = HPB_DMAE_DCR_CT | \ 352 HPB_DMAE_DCR_DIP | \ 353 HPB_DMAE_DCR_SPDS_32BIT | \ 354 HPB_DMAE_DCR_DMDL | \ 355 HPB_DMAE_DCR_DPDS_32BIT, \ 356 .port = 0x1111, \ 357 .dma_ch = (28 + _id), \ 358 }, { \ 359 .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \ 360 .addr = 0xffda0000 + (_id * 0x1000), \ 361 .dcr = HPB_DMAE_DCR_CT | \ 362 HPB_DMAE_DCR_DIP | \ 363 HPB_DMAE_DCR_SMDL | \ 364 HPB_DMAE_DCR_SPDS_32BIT | \ 365 HPB_DMAE_DCR_DPDS_32BIT, \ 366 .port = 0x1111, \ 367 .dma_ch = (28 + _id), \ 368 } 369 370 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 371 { 372 .id = HPBDMA_SLAVE_SDHI0_TX, 373 .addr = 0xffe4c000 + 0x30, 374 .dcr = HPB_DMAE_DCR_SPDS_16BIT | 375 HPB_DMAE_DCR_DMDL | 376 HPB_DMAE_DCR_DPDS_16BIT, 377 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 378 HPB_DMAE_ASYNCRSTR_ASRST22 | 379 HPB_DMAE_ASYNCRSTR_ASRST23, 380 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI, 381 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK, 382 .port = 0x0D0C, 383 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 384 .dma_ch = 21, 385 }, { 386 .id = HPBDMA_SLAVE_SDHI0_RX, 387 .addr = 0xffe4c000 + 0x30, 388 .dcr = HPB_DMAE_DCR_SMDL | 389 HPB_DMAE_DCR_SPDS_16BIT | 390 HPB_DMAE_DCR_DPDS_16BIT, 391 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 | 392 HPB_DMAE_ASYNCRSTR_ASRST22 | 393 HPB_DMAE_ASYNCRSTR_ASRST23, 394 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI, 395 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK, 396 .port = 0x0D0C, 397 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 398 .dma_ch = 22, 399 }, { 400 .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */ 401 .addr = 0xffe60018, 402 .dcr = HPB_DMAE_DCR_SPDS_32BIT | 403 HPB_DMAE_DCR_DMDL | 404 HPB_DMAE_DCR_DPDS_32BIT, 405 .port = 0x0000, 406 .dma_ch = 14, 407 }, { 408 .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */ 409 .addr = 0xffe6001c, 410 .dcr = HPB_DMAE_DCR_SMDL | 411 HPB_DMAE_DCR_SPDS_32BIT | 412 HPB_DMAE_DCR_DPDS_32BIT, 413 .port = 0x0101, 414 .dma_ch = 15, 415 }, 416 417 HPBDMA_SSI(0), 418 HPBDMA_SSI(1), 419 HPBDMA_SSI(2), 420 HPBDMA_SSI(3), 421 HPBDMA_SSI(4), 422 HPBDMA_SSI(5), 423 HPBDMA_SSI(6), 424 HPBDMA_SSI(7), 425 HPBDMA_SSI(8), 426 427 HPBDMA_HPBIF(0), 428 HPBDMA_HPBIF(1), 429 HPBDMA_HPBIF(2), 430 HPBDMA_HPBIF(3), 431 HPBDMA_HPBIF(4), 432 HPBDMA_HPBIF(5), 433 HPBDMA_HPBIF(6), 434 HPBDMA_HPBIF(7), 435 HPBDMA_HPBIF(8), 436 }; 437 438 static const struct hpb_dmae_channel hpb_dmae_channels[] = { 439 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */ 440 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */ 441 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 442 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 443 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */ 444 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */ 445 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */ 446 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */ 447 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */ 448 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */ 449 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */ 450 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */ 451 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */ 452 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */ 453 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */ 454 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */ 455 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */ 456 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */ 457 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */ 458 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */ 459 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */ 460 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */ 461 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */ 462 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */ 463 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */ 464 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */ 465 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */ 466 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */ 467 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */ 468 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */ 469 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */ 470 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */ 471 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */ 472 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */ 473 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */ 474 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */ 475 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */ 476 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */ 477 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */ 478 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */ 479 }; 480 481 static struct hpb_dmae_pdata dma_platform_data __initdata = { 482 .slaves = hpb_dmae_slaves, 483 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves), 484 .channels = hpb_dmae_channels, 485 .num_channels = ARRAY_SIZE(hpb_dmae_channels), 486 .ts_shift = { 487 [XMIT_SZ_8BIT] = 0, 488 [XMIT_SZ_16BIT] = 1, 489 [XMIT_SZ_32BIT] = 2, 490 }, 491 .num_hw_channels = 39, 492 }; 493 494 static struct resource hpb_dmae_resources[] __initdata = { 495 /* Channel registers */ 496 DEFINE_RES_MEM(0xffc08000, 0x1000), 497 /* Common registers */ 498 DEFINE_RES_MEM(0xffc09000, 0x170), 499 /* Asynchronous reset registers */ 500 DEFINE_RES_MEM(0xffc00300, 4), 501 /* Asynchronous mode registers */ 502 DEFINE_RES_MEM(0xffc00400, 4), 503 /* IRQ for DMA channels */ 504 DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ), 505 }; 506 507 static void __init r8a7778_register_hpb_dmae(void) 508 { 509 platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1, 510 hpb_dmae_resources, 511 ARRAY_SIZE(hpb_dmae_resources), 512 &dma_platform_data, 513 sizeof(dma_platform_data)); 514 } 515 516 void __init r8a7778_add_standard_devices(void) 517 { 518 r8a7778_add_dt_devices(); 519 r8a7778_register_i2c(0); 520 r8a7778_register_i2c(1); 521 r8a7778_register_i2c(2); 522 r8a7778_register_i2c(3); 523 r8a7778_register_hspi(0); 524 r8a7778_register_hspi(1); 525 r8a7778_register_hspi(2); 526 527 r8a7778_register_hpb_dmae(); 528 } 529 530 void __init r8a7778_init_late(void) 531 { 532 platform_device_register_full(&ehci_info); 533 platform_device_register_full(&ohci_info); 534 } 535 536 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = { 537 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 538 .sense_bitfield_width = 2, 539 }; 540 541 static struct resource irqpin_resources[] __initdata = { 542 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 543 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 544 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 545 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */ 546 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */ 547 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */ 548 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */ 549 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */ 550 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */ 551 }; 552 553 void __init r8a7778_init_irq_extpin_dt(int irlm) 554 { 555 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE); 556 unsigned long tmp; 557 558 if (!icr0) { 559 pr_warn("r8a7778: unable to setup external irq pin mode\n"); 560 return; 561 } 562 563 tmp = ioread32(icr0); 564 if (irlm) 565 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */ 566 else 567 tmp &= ~(1 << 23); /* IRL mode - not supported */ 568 tmp |= (1 << 21); /* LVLMODE = 1 */ 569 iowrite32(tmp, icr0); 570 iounmap(icr0); 571 } 572 573 void __init r8a7778_init_irq_extpin(int irlm) 574 { 575 r8a7778_init_irq_extpin_dt(irlm); 576 if (irlm) 577 platform_device_register_resndata( 578 &platform_bus, "renesas_intc_irqpin", -1, 579 irqpin_resources, ARRAY_SIZE(irqpin_resources), 580 &irqpin_platform_data, sizeof(irqpin_platform_data)); 581 } 582 583 void __init r8a7778_init_delay(void) 584 { 585 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 586 } 587 588 #ifdef CONFIG_USE_OF 589 #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 590 #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 591 592 #define INT2NTSR0 0x00018 /* 0xfe700018 */ 593 #define INT2NTSR1 0x0002c /* 0xfe70002c */ 594 void __init r8a7778_init_irq_dt(void) 595 { 596 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 597 598 BUG_ON(!base); 599 600 irqchip_init(); 601 602 /* route all interrupts to ARM */ 603 __raw_writel(0x73ffffff, base + INT2NTSR0); 604 __raw_writel(0xffffffff, base + INT2NTSR1); 605 606 /* unmask all known interrupts in INTCS2 */ 607 __raw_writel(0x08330773, base + INT2SMSKCR0); 608 __raw_writel(0x00311110, base + INT2SMSKCR1); 609 610 iounmap(base); 611 } 612 613 static const char *r8a7778_compat_dt[] __initdata = { 614 "renesas,r8a7778", 615 NULL, 616 }; 617 618 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 619 .init_early = r8a7778_init_delay, 620 .init_irq = r8a7778_init_irq_dt, 621 .dt_compat = r8a7778_compat_dt, 622 .init_late = r8a7778_init_late, 623 MACHINE_END 624 625 #endif /* CONFIG_USE_OF */ 626