1 /*
2  * r8a7778 processor support
3  *
4  * Copyright (C) 2013  Renesas Solutions Corp.
5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6  * Copyright (C) 2013  Cogent Embedded, Inc.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; version 2 of the License.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
20  */
21 
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/irqchip/arm-gic.h>
25 #include <linux/of.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_data/dma-rcar-hpbdma.h>
28 #include <linux/platform_data/gpio-rcar.h>
29 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
30 #include <linux/platform_device.h>
31 #include <linux/irqchip.h>
32 #include <linux/serial_sci.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/usb/phy.h>
36 #include <linux/usb/hcd.h>
37 #include <linux/usb/ehci_pdriver.h>
38 #include <linux/usb/ohci_pdriver.h>
39 #include <linux/dma-mapping.h>
40 #include <mach/irqs.h>
41 #include <mach/r8a7778.h>
42 #include <mach/common.h>
43 #include <asm/mach/arch.h>
44 #include <asm/hardware/cache-l2x0.h>
45 
46 /* SCIF */
47 #define R8A7778_SCIF(index, baseaddr, irq)			\
48 static struct plat_sci_port scif##index##_platform_data = {	\
49 	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,	\
50 	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,	\
51 	.type		= PORT_SCIF,				\
52 };								\
53 								\
54 static struct resource scif##index##_resources[] = {		\
55 	DEFINE_RES_MEM(baseaddr, 0x100),			\
56 	DEFINE_RES_IRQ(irq),					\
57 }
58 
59 R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
60 R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
61 R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
62 R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
63 R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
64 R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
65 
66 #define r8a7778_register_scif(index)					       \
67 	platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
68 					  scif##index##_resources,	       \
69 					  ARRAY_SIZE(scif##index##_resources), \
70 					  &scif##index##_platform_data,	       \
71 					  sizeof(scif##index##_platform_data))
72 
73 /* TMU */
74 static struct sh_timer_config sh_tmu0_platform_data = {
75 	.channels_mask = 7,
76 };
77 
78 static struct resource sh_tmu0_resources[] = {
79 	DEFINE_RES_MEM(0xffd80000, 0x30),
80 	DEFINE_RES_IRQ(gic_iid(0x40)),
81 	DEFINE_RES_IRQ(gic_iid(0x41)),
82 	DEFINE_RES_IRQ(gic_iid(0x42)),
83 };
84 
85 #define r8a7778_register_tmu(idx)			\
86 	platform_device_register_resndata(		\
87 		&platform_bus, "sh-tmu", idx,		\
88 		sh_tmu##idx##_resources,		\
89 		ARRAY_SIZE(sh_tmu##idx##_resources),	\
90 		&sh_tmu##idx##_platform_data,		\
91 		sizeof(sh_tmu##idx##_platform_data))
92 
93 int r8a7778_usb_phy_power(bool enable)
94 {
95 	static struct usb_phy *phy = NULL;
96 	int ret = 0;
97 
98 	if (!phy)
99 		phy = usb_get_phy(USB_PHY_TYPE_USB2);
100 
101 	if (IS_ERR(phy)) {
102 		pr_err("kernel doesn't have usb phy driver\n");
103 		return PTR_ERR(phy);
104 	}
105 
106 	if (enable)
107 		ret = usb_phy_init(phy);
108 	else
109 		usb_phy_shutdown(phy);
110 
111 	return ret;
112 }
113 
114 /* USB */
115 static int usb_power_on(struct platform_device *pdev)
116 {
117 	int ret = r8a7778_usb_phy_power(true);
118 
119 	if (ret)
120 		return ret;
121 
122 	pm_runtime_enable(&pdev->dev);
123 	pm_runtime_get_sync(&pdev->dev);
124 
125 	return 0;
126 }
127 
128 static void usb_power_off(struct platform_device *pdev)
129 {
130 	if (r8a7778_usb_phy_power(false))
131 		return;
132 
133 	pm_runtime_put_sync(&pdev->dev);
134 	pm_runtime_disable(&pdev->dev);
135 }
136 
137 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
138 {
139 	/*
140 	 * Below are recommended values from the datasheet;
141 	 * see [USB :: Setting of EHCI Internal Buffer].
142 	 */
143 	/* EHCI IP internal buffer setting */
144 	iowrite32(0x00ff0040, hcd->regs + 0x0094);
145 	/* EHCI IP internal buffer enable */
146 	iowrite32(0x00000001, hcd->regs + 0x009C);
147 
148 	return 0;
149 }
150 
151 static struct usb_ehci_pdata ehci_pdata __initdata = {
152 	.power_on	= usb_power_on,
153 	.power_off	= usb_power_off,
154 	.power_suspend	= usb_power_off,
155 	.pre_setup	= ehci_init_internal_buffer,
156 };
157 
158 static struct resource ehci_resources[] __initdata = {
159 	DEFINE_RES_MEM(0xffe70000, 0x400),
160 	DEFINE_RES_IRQ(gic_iid(0x4c)),
161 };
162 
163 static struct usb_ohci_pdata ohci_pdata __initdata = {
164 	.power_on	= usb_power_on,
165 	.power_off	= usb_power_off,
166 	.power_suspend	= usb_power_off,
167 };
168 
169 static struct resource ohci_resources[] __initdata = {
170 	DEFINE_RES_MEM(0xffe70400, 0x400),
171 	DEFINE_RES_IRQ(gic_iid(0x4c)),
172 };
173 
174 #define USB_PLATFORM_INFO(hci)					\
175 static struct platform_device_info hci##_info __initdata = {	\
176 	.parent		= &platform_bus,			\
177 	.name		= #hci "-platform",			\
178 	.id		= -1,					\
179 	.res		= hci##_resources,			\
180 	.num_res	= ARRAY_SIZE(hci##_resources),		\
181 	.data		= &hci##_pdata,				\
182 	.size_data	= sizeof(hci##_pdata),			\
183 	.dma_mask	= DMA_BIT_MASK(32),			\
184 }
185 
186 USB_PLATFORM_INFO(ehci);
187 USB_PLATFORM_INFO(ohci);
188 
189 /* PFC/GPIO */
190 static struct resource pfc_resources[] __initdata = {
191 	DEFINE_RES_MEM(0xfffc0000, 0x118),
192 };
193 
194 #define R8A7778_GPIO(idx)						\
195 static struct resource r8a7778_gpio##idx##_resources[] __initdata = {	\
196 	DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),		\
197 	DEFINE_RES_IRQ(gic_iid(0x87)),					\
198 };									\
199 									\
200 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
201 	.gpio_base	= 32 * (idx),					\
202 	.irq_base	= GPIO_IRQ_BASE(idx),				\
203 	.number_of_pins	= 32,						\
204 	.pctl_name	= "pfc-r8a7778",				\
205 }
206 
207 R8A7778_GPIO(0);
208 R8A7778_GPIO(1);
209 R8A7778_GPIO(2);
210 R8A7778_GPIO(3);
211 R8A7778_GPIO(4);
212 
213 #define r8a7778_register_gpio(idx)				\
214 	platform_device_register_resndata(			\
215 		&platform_bus, "gpio_rcar", idx,		\
216 		r8a7778_gpio##idx##_resources,			\
217 		ARRAY_SIZE(r8a7778_gpio##idx##_resources),	\
218 		&r8a7778_gpio##idx##_platform_data,		\
219 		sizeof(r8a7778_gpio##idx##_platform_data))
220 
221 void __init r8a7778_pinmux_init(void)
222 {
223 	platform_device_register_simple(
224 		"pfc-r8a7778", -1,
225 		pfc_resources,
226 		ARRAY_SIZE(pfc_resources));
227 
228 	r8a7778_register_gpio(0);
229 	r8a7778_register_gpio(1);
230 	r8a7778_register_gpio(2);
231 	r8a7778_register_gpio(3);
232 	r8a7778_register_gpio(4);
233 };
234 
235 /* I2C */
236 static struct resource i2c_resources[] __initdata = {
237 	/* I2C0 */
238 	DEFINE_RES_MEM(0xffc70000, 0x1000),
239 	DEFINE_RES_IRQ(gic_iid(0x63)),
240 	/* I2C1 */
241 	DEFINE_RES_MEM(0xffc71000, 0x1000),
242 	DEFINE_RES_IRQ(gic_iid(0x6e)),
243 	/* I2C2 */
244 	DEFINE_RES_MEM(0xffc72000, 0x1000),
245 	DEFINE_RES_IRQ(gic_iid(0x6c)),
246 	/* I2C3 */
247 	DEFINE_RES_MEM(0xffc73000, 0x1000),
248 	DEFINE_RES_IRQ(gic_iid(0x6d)),
249 };
250 
251 static void __init r8a7778_register_i2c(int id)
252 {
253 	BUG_ON(id < 0 || id > 3);
254 
255 	platform_device_register_simple(
256 		"i2c-rcar", id,
257 		i2c_resources + (2 * id), 2);
258 }
259 
260 /* HSPI */
261 static struct resource hspi_resources[] __initdata = {
262 	/* HSPI0 */
263 	DEFINE_RES_MEM(0xfffc7000, 0x18),
264 	DEFINE_RES_IRQ(gic_iid(0x5f)),
265 	/* HSPI1 */
266 	DEFINE_RES_MEM(0xfffc8000, 0x18),
267 	DEFINE_RES_IRQ(gic_iid(0x74)),
268 	/* HSPI2 */
269 	DEFINE_RES_MEM(0xfffc6000, 0x18),
270 	DEFINE_RES_IRQ(gic_iid(0x75)),
271 };
272 
273 static void __init r8a7778_register_hspi(int id)
274 {
275 	BUG_ON(id < 0 || id > 2);
276 
277 	platform_device_register_simple(
278 		"sh-hspi", id,
279 		hspi_resources + (2 * id), 2);
280 }
281 
282 void __init r8a7778_add_dt_devices(void)
283 {
284 #ifdef CONFIG_CACHE_L2X0
285 	void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
286 	if (base) {
287 		/*
288 		 * Shared attribute override enable, 64K*16way
289 		 * don't call iounmap(base)
290 		 */
291 		l2x0_init(base, 0x00400000, 0xc20f0fff);
292 	}
293 #endif
294 
295 	r8a7778_register_scif(0);
296 	r8a7778_register_scif(1);
297 	r8a7778_register_scif(2);
298 	r8a7778_register_scif(3);
299 	r8a7778_register_scif(4);
300 	r8a7778_register_scif(5);
301 	r8a7778_register_tmu(0);
302 }
303 
304 /* HPB-DMA */
305 
306 /* Asynchronous mode register (ASYNCMDR) bits */
307 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK	BIT(2)	/* SDHI0 */
308 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE	BIT(2)	/* SDHI0 */
309 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI	0	/* SDHI0 */
310 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK	BIT(1)	/* SDHI0 */
311 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE	BIT(1)	/* SDHI0 */
312 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI	0	/* SDHI0 */
313 
314 #define HPBDMA_SSI(_id)				\
315 {						\
316 	.id	= HPBDMA_SLAVE_SSI## _id ##_TX,	\
317 	.addr	= 0xffd91008 + (_id * 0x40),	\
318 	.dcr	= HPB_DMAE_DCR_CT |		\
319 		  HPB_DMAE_DCR_DIP |		\
320 		  HPB_DMAE_DCR_SPDS_32BIT |	\
321 		  HPB_DMAE_DCR_DMDL |		\
322 		  HPB_DMAE_DCR_DPDS_32BIT,	\
323 	.port   = _id + (_id << 8),		\
324 	.dma_ch = (28 + _id),			\
325 }, {						\
326 	.id	= HPBDMA_SLAVE_SSI## _id ##_RX,	\
327 	.addr	= 0xffd9100c + (_id * 0x40),	\
328 	.dcr	= HPB_DMAE_DCR_CT |		\
329 		  HPB_DMAE_DCR_DIP |		\
330 		  HPB_DMAE_DCR_SMDL |		\
331 		  HPB_DMAE_DCR_SPDS_32BIT |	\
332 		  HPB_DMAE_DCR_DPDS_32BIT,	\
333 	.port   = _id + (_id << 8),		\
334 	.dma_ch = (28 + _id),			\
335 }
336 
337 #define HPBDMA_HPBIF(_id)				\
338 {							\
339 	.id	= HPBDMA_SLAVE_HPBIF## _id ##_TX,	\
340 	.addr	= 0xffda0000 + (_id * 0x1000),		\
341 	.dcr	= HPB_DMAE_DCR_CT |			\
342 		  HPB_DMAE_DCR_DIP |			\
343 		  HPB_DMAE_DCR_SPDS_32BIT |		\
344 		  HPB_DMAE_DCR_DMDL |			\
345 		  HPB_DMAE_DCR_DPDS_32BIT,		\
346 	.port   = 0x1111,				\
347 	.dma_ch = (28 + _id),				\
348 }, {							\
349 	.id	= HPBDMA_SLAVE_HPBIF## _id ##_RX,	\
350 	.addr	= 0xffda0000 + (_id * 0x1000),		\
351 	.dcr	= HPB_DMAE_DCR_CT |			\
352 		  HPB_DMAE_DCR_DIP |			\
353 		  HPB_DMAE_DCR_SMDL |			\
354 		  HPB_DMAE_DCR_SPDS_32BIT |		\
355 		  HPB_DMAE_DCR_DPDS_32BIT,		\
356 	.port   = 0x1111,				\
357 	.dma_ch = (28 + _id),				\
358 }
359 
360 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
361 	{
362 		.id	= HPBDMA_SLAVE_SDHI0_TX,
363 		.addr	= 0xffe4c000 + 0x30,
364 		.dcr	= HPB_DMAE_DCR_SPDS_16BIT |
365 			  HPB_DMAE_DCR_DMDL |
366 			  HPB_DMAE_DCR_DPDS_16BIT,
367 		.rstr	= HPB_DMAE_ASYNCRSTR_ASRST21 |
368 			  HPB_DMAE_ASYNCRSTR_ASRST22 |
369 			  HPB_DMAE_ASYNCRSTR_ASRST23,
370 		.mdr	= HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
371 		.mdm	= HPB_DMAE_ASYNCMDR_ASMD21_MASK,
372 		.port	= 0x0D0C,
373 		.flags	= HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
374 		.dma_ch	= 21,
375 	}, {
376 		.id	= HPBDMA_SLAVE_SDHI0_RX,
377 		.addr	= 0xffe4c000 + 0x30,
378 		.dcr	= HPB_DMAE_DCR_SMDL |
379 			  HPB_DMAE_DCR_SPDS_16BIT |
380 			  HPB_DMAE_DCR_DPDS_16BIT,
381 		.rstr	= HPB_DMAE_ASYNCRSTR_ASRST21 |
382 			  HPB_DMAE_ASYNCRSTR_ASRST22 |
383 			  HPB_DMAE_ASYNCRSTR_ASRST23,
384 		.mdr	= HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
385 		.mdm	= HPB_DMAE_ASYNCMDR_ASMD22_MASK,
386 		.port	= 0x0D0C,
387 		.flags	= HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
388 		.dma_ch	= 22,
389 	}, {
390 		.id	= HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
391 		.addr	= 0xffe60018,
392 		.dcr	= HPB_DMAE_DCR_SPDS_32BIT |
393 			  HPB_DMAE_DCR_DMDL |
394 			  HPB_DMAE_DCR_DPDS_32BIT,
395 		.port	= 0x0000,
396 		.dma_ch	= 14,
397 	}, {
398 		.id	= HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
399 		.addr	= 0xffe6001c,
400 		.dcr	= HPB_DMAE_DCR_SMDL |
401 			  HPB_DMAE_DCR_SPDS_32BIT |
402 			  HPB_DMAE_DCR_DPDS_32BIT,
403 		.port	= 0x0101,
404 		.dma_ch	= 15,
405 	},
406 
407 	HPBDMA_SSI(0),
408 	HPBDMA_SSI(1),
409 	HPBDMA_SSI(2),
410 	HPBDMA_SSI(3),
411 	HPBDMA_SSI(4),
412 	HPBDMA_SSI(5),
413 	HPBDMA_SSI(6),
414 	HPBDMA_SSI(7),
415 	HPBDMA_SSI(8),
416 
417 	HPBDMA_HPBIF(0),
418 	HPBDMA_HPBIF(1),
419 	HPBDMA_HPBIF(2),
420 	HPBDMA_HPBIF(3),
421 	HPBDMA_HPBIF(4),
422 	HPBDMA_HPBIF(5),
423 	HPBDMA_HPBIF(6),
424 	HPBDMA_HPBIF(7),
425 	HPBDMA_HPBIF(8),
426 };
427 
428 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
429 	HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
430 	HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
431 	HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
432 	HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
433 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX),   /* ch. 28 */
434 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX),   /* ch. 28 */
435 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
436 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
437 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX),   /* ch. 29 */
438 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX),   /* ch. 29 */
439 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
440 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
441 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX),   /* ch. 30 */
442 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX),   /* ch. 30 */
443 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
444 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
445 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX),   /* ch. 31 */
446 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX),   /* ch. 31 */
447 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
448 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
449 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX),   /* ch. 32 */
450 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX),   /* ch. 32 */
451 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
452 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
453 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX),   /* ch. 33 */
454 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX),   /* ch. 33 */
455 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
456 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
457 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX),   /* ch. 34 */
458 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX),   /* ch. 34 */
459 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
460 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
461 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX),   /* ch. 35 */
462 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX),   /* ch. 35 */
463 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
464 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
465 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX),   /* ch. 36 */
466 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX),   /* ch. 36 */
467 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
468 	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
469 };
470 
471 static struct hpb_dmae_pdata dma_platform_data __initdata = {
472 	.slaves			= hpb_dmae_slaves,
473 	.num_slaves		= ARRAY_SIZE(hpb_dmae_slaves),
474 	.channels		= hpb_dmae_channels,
475 	.num_channels		= ARRAY_SIZE(hpb_dmae_channels),
476 	.ts_shift		= {
477 		[XMIT_SZ_8BIT]	= 0,
478 		[XMIT_SZ_16BIT]	= 1,
479 		[XMIT_SZ_32BIT]	= 2,
480 	},
481 	.num_hw_channels	= 39,
482 };
483 
484 static struct resource hpb_dmae_resources[] __initdata = {
485 	/* Channel registers */
486 	DEFINE_RES_MEM(0xffc08000, 0x1000),
487 	/* Common registers */
488 	DEFINE_RES_MEM(0xffc09000, 0x170),
489 	/* Asynchronous reset registers */
490 	DEFINE_RES_MEM(0xffc00300, 4),
491 	/* Asynchronous mode registers */
492 	DEFINE_RES_MEM(0xffc00400, 4),
493 	/* IRQ for DMA channels */
494 	DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
495 };
496 
497 static void __init r8a7778_register_hpb_dmae(void)
498 {
499 	platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
500 					  hpb_dmae_resources,
501 					  ARRAY_SIZE(hpb_dmae_resources),
502 					  &dma_platform_data,
503 					  sizeof(dma_platform_data));
504 }
505 
506 void __init r8a7778_add_standard_devices(void)
507 {
508 	r8a7778_add_dt_devices();
509 	r8a7778_register_i2c(0);
510 	r8a7778_register_i2c(1);
511 	r8a7778_register_i2c(2);
512 	r8a7778_register_i2c(3);
513 	r8a7778_register_hspi(0);
514 	r8a7778_register_hspi(1);
515 	r8a7778_register_hspi(2);
516 
517 	r8a7778_register_hpb_dmae();
518 }
519 
520 void __init r8a7778_init_late(void)
521 {
522 	platform_device_register_full(&ehci_info);
523 	platform_device_register_full(&ohci_info);
524 }
525 
526 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
527 	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
528 	.sense_bitfield_width = 2,
529 };
530 
531 static struct resource irqpin_resources[] __initdata = {
532 	DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
533 	DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
534 	DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
535 	DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
536 	DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
537 	DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
538 	DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
539 	DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
540 	DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
541 };
542 
543 void __init r8a7778_init_irq_extpin_dt(int irlm)
544 {
545 	void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
546 	unsigned long tmp;
547 
548 	if (!icr0) {
549 		pr_warn("r8a7778: unable to setup external irq pin mode\n");
550 		return;
551 	}
552 
553 	tmp = ioread32(icr0);
554 	if (irlm)
555 		tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
556 	else
557 		tmp &= ~(1 << 23); /* IRL mode - not supported */
558 	tmp |= (1 << 21); /* LVLMODE = 1 */
559 	iowrite32(tmp, icr0);
560 	iounmap(icr0);
561 }
562 
563 void __init r8a7778_init_irq_extpin(int irlm)
564 {
565 	r8a7778_init_irq_extpin_dt(irlm);
566 	if (irlm)
567 		platform_device_register_resndata(
568 			&platform_bus, "renesas_intc_irqpin", -1,
569 			irqpin_resources, ARRAY_SIZE(irqpin_resources),
570 			&irqpin_platform_data, sizeof(irqpin_platform_data));
571 }
572 
573 void __init r8a7778_init_delay(void)
574 {
575 	shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
576 }
577 
578 #ifdef CONFIG_USE_OF
579 #define INT2SMSKCR0	0x82288 /* 0xfe782288 */
580 #define INT2SMSKCR1	0x8228c /* 0xfe78228c */
581 
582 #define INT2NTSR0	0x00018 /* 0xfe700018 */
583 #define INT2NTSR1	0x0002c /* 0xfe70002c */
584 void __init r8a7778_init_irq_dt(void)
585 {
586 	void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
587 
588 	BUG_ON(!base);
589 
590 	irqchip_init();
591 
592 	/* route all interrupts to ARM */
593 	__raw_writel(0x73ffffff, base + INT2NTSR0);
594 	__raw_writel(0xffffffff, base + INT2NTSR1);
595 
596 	/* unmask all known interrupts in INTCS2 */
597 	__raw_writel(0x08330773, base + INT2SMSKCR0);
598 	__raw_writel(0x00311110, base + INT2SMSKCR1);
599 
600 	iounmap(base);
601 }
602 
603 static const char *r8a7778_compat_dt[] __initdata = {
604 	"renesas,r8a7778",
605 	NULL,
606 };
607 
608 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
609 	.init_early	= r8a7778_init_delay,
610 	.init_irq	= r8a7778_init_irq_dt,
611 	.dt_compat	= r8a7778_compat_dt,
612 	.init_late      = r8a7778_init_late,
613 MACHINE_END
614 
615 #endif /* CONFIG_USE_OF */
616